1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 * OMAP54xx PRCM MPU instance offset macros
 4 *
 5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
 6 *
 7 * Paul Walmsley (paul@pwsan.com)
 8 * Rajendra Nayak (rnayak@ti.com)
 9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 */
17
18#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H
19#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H
20
21#include "prcm_mpu_44xx_54xx.h"
22#include "common.h"
23
24#define OMAP54XX_PRCM_MPU_BASE			0x48243000
25
26#define OMAP54XX_PRCM_MPU_REGADDR(inst, reg)				\
27	OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE + (inst) + (reg))
28
29/* PRCM_MPU instances */
30#define OMAP54XX_PRCM_MPU_OCP_SOCKET_INST	0x0000
31#define OMAP54XX_PRCM_MPU_DEVICE_INST		0x0200
32#define OMAP54XX_PRCM_MPU_PRM_C0_INST		0x0400
33#define OMAP54XX_PRCM_MPU_CM_C0_INST		0x0600
34#define OMAP54XX_PRCM_MPU_PRM_C1_INST		0x0800
35#define OMAP54XX_PRCM_MPU_CM_C1_INST		0x0a00
36
37/* PRCM_MPU clockdomain register offsets (from instance start) */
38#define OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS	0x0000
39#define OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS	0x0000
40
41
42/*
43 * PRCM_MPU
44 *
45 * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
46 * point of view the PRCM_MPU is a single entity. It shares the same
47 * programming model as the global PRCM and thus can be assimilate as two new
48 * MOD inside the PRCM
49 */
50
51/* PRCM_MPU.PRCM_MPU_OCP_SOCKET register offsets */
52#define OMAP54XX_REVISION_PRCM_MPU_OFFSET			0x0000
53
54/* PRCM_MPU.PRCM_MPU_DEVICE register offsets */
55#define OMAP54XX_PRCM_MPU_PRM_RSTST_OFFSET			0x0000
56#define OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET		0x0004
57#define OMAP54XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET		0x0010
58#define OMAP54XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET	0x0014
59
60/* PRCM_MPU.PRCM_MPU_PRM_C0 register offsets */
61#define OMAP54XX_PM_CPU0_PWRSTCTRL_OFFSET			0x0000
62#define OMAP54XX_PM_CPU0_PWRSTST_OFFSET				0x0004
63#define OMAP54XX_RM_CPU0_CPU0_RSTCTRL_OFFSET			0x0010
64#define OMAP54XX_RM_CPU0_CPU0_RSTST_OFFSET			0x0014
65#define OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET			0x0024
66
67/* PRCM_MPU.PRCM_MPU_CM_C0 register offsets */
68#define OMAP54XX_CM_CPU0_CLKSTCTRL_OFFSET			0x0000
69#define OMAP54XX_CM_CPU0_CPU0_CLKCTRL_OFFSET			0x0020
70#define OMAP54XX_CM_CPU0_CPU0_CLKCTRL				OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C0_INST, 0x0020)
71
72/* PRCM_MPU.PRCM_MPU_PRM_C1 register offsets */
73#define OMAP54XX_PM_CPU1_PWRSTCTRL_OFFSET			0x0000
74#define OMAP54XX_PM_CPU1_PWRSTST_OFFSET				0x0004
75#define OMAP54XX_RM_CPU1_CPU1_RSTCTRL_OFFSET			0x0010
76#define OMAP54XX_RM_CPU1_CPU1_RSTST_OFFSET			0x0014
77#define OMAP54XX_RM_CPU1_CPU1_CONTEXT_OFFSET			0x0024
78
79/* PRCM_MPU.PRCM_MPU_CM_C1 register offsets */
80#define OMAP54XX_CM_CPU1_CLKSTCTRL_OFFSET			0x0000
81#define OMAP54XX_CM_CPU1_CPU1_CLKCTRL_OFFSET			0x0020
82#define OMAP54XX_CM_CPU1_CPU1_CLKCTRL				OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C1_INST, 0x0020)
83
84#endif