1/*
  2 * OMAP3-specific clock framework functions
  3 *
  4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
  5 * Copyright (C) 2007-2010 Nokia Corporation
  6 *
  7 * Paul Walmsley
  8 * Jouni Högander
  9 *
 10 * Parts of this code are based on code written by
 11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
 12 *
 13 * This program is free software; you can redistribute it and/or modify
 14 * it under the terms of the GNU General Public License version 2 as
 15 * published by the Free Software Foundation.
 16 */
 17#undef DEBUG
 18
 19#include <linux/kernel.h>
 20#include <linux/errno.h>
 21#include <linux/clk.h>
 22#include <linux/io.h>
 23
 24#include <plat/hardware.h>
 25#include <plat/clock.h>
 26
 27#include "clock.h"
 28#include "clock3xxx.h"
 29#include "prm2xxx_3xxx.h"
 30#include "prm-regbits-34xx.h"
 31#include "cm2xxx_3xxx.h"
 32#include "cm-regbits-34xx.h"
 33
 34/*
 35 * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
 36 * that are sourced by DPLL5, and both of these require this clock
 37 * to be at 120 MHz for proper operation.
 38 */
 39#define DPLL5_FREQ_FOR_USBHOST		120000000
 40
 41/* needed by omap3_core_dpll_m2_set_rate() */
 42struct clk *sdrc_ick_p, *arm_fck_p;
 43
 44int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
 45{
 46	/*
 47	 * According to the 12-5 CDP code from TI, "Limitation 2.5"
 48	 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
 49	 * on DPLL4.
 50	 */
 51	if (omap_rev() == OMAP3430_REV_ES1_0) {
 52		pr_err("clock: DPLL4 cannot change rate due to "
 53		       "silicon 'Limitation 2.5' on 3430ES1.\n");
 54		return -EINVAL;
 55	}
 56
 57	return omap3_noncore_dpll_set_rate(clk, rate);
 58}
 59
 60void __init omap3_clk_lock_dpll5(void)
 61{
 62	struct clk *dpll5_clk;
 63	struct clk *dpll5_m2_clk;
 64
 65	dpll5_clk = clk_get(NULL, "dpll5_ck");
 66	clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
 67	clk_enable(dpll5_clk);
 68
 69	/* Program dpll5_m2_clk divider for no division */
 70	dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
 71	clk_enable(dpll5_m2_clk);
 72	clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
 73
 74	clk_disable(dpll5_m2_clk);
 75	clk_disable(dpll5_clk);
 76	return;
 77}
 78
 79/* Common clock code */
 80
 81/*
 82 * Switch the MPU rate if specified on cmdline.  We cannot do this
 83 * early until cmdline is parsed.  XXX This should be removed from the
 84 * clock code and handled by the OPP layer code in the near future.
 85 */
 86static int __init omap3xxx_clk_arch_init(void)
 87{
 88	int ret;
 89
 90	if (!cpu_is_omap34xx())
 91		return 0;
 92
 93	ret = omap2_clk_switch_mpurate_at_boot("dpll1_ck");
 94	if (!ret)
 95		omap2_clk_print_new_rates("osc_sys_ck", "core_ck", "arm_fck");
 96
 97	return ret;
 98}
 99
100arch_initcall(omap3xxx_clk_arch_init);
101
102