1/*
  2 * linux/arch/arm/mach-at91/irq.c
  3 *
  4 *  Copyright (C) 2004 SAN People
  5 *  Copyright (C) 2004 ATMEL
  6 *  Copyright (C) Rick Bronson
  7 *
  8 * This program is free software; you can redistribute it and/or modify
  9 * it under the terms of the GNU General Public License as published by
 10 * the Free Software Foundation; either version 2 of the License, or
 11 * (at your option) any later version.
 12 *
 13 * This program is distributed in the hope that it will be useful,
 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16 * GNU General Public License for more details.
 17 *
 18 * You should have received a copy of the GNU General Public License
 19 * along with this program; if not, write to the Free Software
 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 21 */
 22
 23#include <linux/init.h>
 24#include <linux/module.h>
 25#include <linux/mm.h>
 26#include <linux/types.h>
 27#include <linux/irq.h>
 28#include <linux/of.h>
 29#include <linux/of_address.h>
 30#include <linux/of_irq.h>
 31#include <linux/irqdomain.h>
 32#include <linux/err.h>
 33
 34#include <mach/hardware.h>
 35#include <asm/irq.h>
 36#include <asm/setup.h>
 37
 38#include <asm/mach/arch.h>
 39#include <asm/mach/irq.h>
 40#include <asm/mach/map.h>
 41
 42void __iomem *at91_aic_base;
 43static struct irq_domain *at91_aic_domain;
 44static struct device_node *at91_aic_np;
 45
 46static void at91_aic_mask_irq(struct irq_data *d)
 47{
 48	/* Disable interrupt on AIC */
 49	at91_aic_write(AT91_AIC_IDCR, 1 << d->hwirq);
 50}
 51
 52static void at91_aic_unmask_irq(struct irq_data *d)
 53{
 54	/* Enable interrupt on AIC */
 55	at91_aic_write(AT91_AIC_IECR, 1 << d->hwirq);
 56}
 57
 58unsigned int at91_extern_irq;
 59
 60#define is_extern_irq(hwirq) ((1 << (hwirq)) & at91_extern_irq)
 61
 62static int at91_aic_set_type(struct irq_data *d, unsigned type)
 63{
 64	unsigned int smr, srctype;
 65
 66	switch (type) {
 67	case IRQ_TYPE_LEVEL_HIGH:
 68		srctype = AT91_AIC_SRCTYPE_HIGH;
 69		break;
 70	case IRQ_TYPE_EDGE_RISING:
 71		srctype = AT91_AIC_SRCTYPE_RISING;
 72		break;
 73	case IRQ_TYPE_LEVEL_LOW:
 74		if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq))		/* only supported on external interrupts */
 75			srctype = AT91_AIC_SRCTYPE_LOW;
 76		else
 77			return -EINVAL;
 78		break;
 79	case IRQ_TYPE_EDGE_FALLING:
 80		if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq))		/* only supported on external interrupts */
 81			srctype = AT91_AIC_SRCTYPE_FALLING;
 82		else
 83			return -EINVAL;
 84		break;
 85	default:
 86		return -EINVAL;
 87	}
 88
 89	smr = at91_aic_read(AT91_AIC_SMR(d->hwirq)) & ~AT91_AIC_SRCTYPE;
 90	at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
 91	return 0;
 92}
 93
 94#ifdef CONFIG_PM
 95
 96static u32 wakeups;
 97static u32 backups;
 98
 99static int at91_aic_set_wake(struct irq_data *d, unsigned value)
100{
101	if (unlikely(d->hwirq >= NR_AIC_IRQS))
102		return -EINVAL;
103
104	if (value)
105		wakeups |= (1 << d->hwirq);
106	else
107		wakeups &= ~(1 << d->hwirq);
108
109	return 0;
110}
111
112void at91_irq_suspend(void)
113{
114	backups = at91_aic_read(AT91_AIC_IMR);
115	at91_aic_write(AT91_AIC_IDCR, backups);
116	at91_aic_write(AT91_AIC_IECR, wakeups);
117}
118
119void at91_irq_resume(void)
120{
121	at91_aic_write(AT91_AIC_IDCR, wakeups);
122	at91_aic_write(AT91_AIC_IECR, backups);
123}
124
125#else
126#define at91_aic_set_wake	NULL
127#endif
128
129static struct irq_chip at91_aic_chip = {
130	.name		= "AIC",
131	.irq_ack	= at91_aic_mask_irq,
132	.irq_mask	= at91_aic_mask_irq,
133	.irq_unmask	= at91_aic_unmask_irq,
134	.irq_set_type	= at91_aic_set_type,
135	.irq_set_wake	= at91_aic_set_wake,
136};
137
138static void __init at91_aic_hw_init(unsigned int spu_vector)
139{
140	int i;
141
142	/*
143	 * Perform 8 End Of Interrupt Command to make sure AIC
144	 * will not Lock out nIRQ
145	 */
146	for (i = 0; i < 8; i++)
147		at91_aic_write(AT91_AIC_EOICR, 0);
148
149	/*
150	 * Spurious Interrupt ID in Spurious Vector Register.
151	 * When there is no current interrupt, the IRQ Vector Register
152	 * reads the value stored in AIC_SPU
153	 */
154	at91_aic_write(AT91_AIC_SPU, spu_vector);
155
156	/* No debugging in AIC: Debug (Protect) Control Register */
157	at91_aic_write(AT91_AIC_DCR, 0);
158
159	/* Disable and clear all interrupts initially */
160	at91_aic_write(AT91_AIC_IDCR, 0xFFFFFFFF);
161	at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
162}
163
164#if defined(CONFIG_OF)
165static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq,
166							irq_hw_number_t hw)
167{
168	/* Put virq number in Source Vector Register */
169	at91_aic_write(AT91_AIC_SVR(hw), virq);
170
171	/* Active Low interrupt, without priority */
172	at91_aic_write(AT91_AIC_SMR(hw), AT91_AIC_SRCTYPE_LOW);
173
174	irq_set_chip_and_handler(virq, &at91_aic_chip, handle_level_irq);
175	set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
176
177	return 0;
178}
179
180static struct irq_domain_ops at91_aic_irq_ops = {
181	.map	= at91_aic_irq_map,
182	.xlate	= irq_domain_xlate_twocell,
183};
184
185int __init at91_aic_of_init(struct device_node *node,
186				     struct device_node *parent)
187{
188	at91_aic_base = of_iomap(node, 0);
189	at91_aic_np = node;
190
191	at91_aic_domain = irq_domain_add_linear(at91_aic_np, NR_AIC_IRQS,
192						&at91_aic_irq_ops, NULL);
193	if (!at91_aic_domain)
194		panic("Unable to add AIC irq domain (DT)\n");
195
196	irq_set_default_host(at91_aic_domain);
197
198	at91_aic_hw_init(NR_AIC_IRQS);
199
200	return 0;
201}
202#endif
203
204/*
205 * Initialize the AIC interrupt controller.
206 */
207void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
208{
209	unsigned int i;
210	int irq_base;
211
212	at91_aic_base = ioremap(AT91_AIC, 512);
213	if (!at91_aic_base)
214		panic("Unable to ioremap AIC registers\n");
215
216	/* Add irq domain for AIC */
217	irq_base = irq_alloc_descs(-1, 0, NR_AIC_IRQS, 0);
218	if (irq_base < 0) {
219		WARN(1, "Cannot allocate irq_descs, assuming pre-allocated\n");
220		irq_base = 0;
221	}
222	at91_aic_domain = irq_domain_add_legacy(at91_aic_np, NR_AIC_IRQS,
223						irq_base, 0,
224						&irq_domain_simple_ops, NULL);
225
226	if (!at91_aic_domain)
227		panic("Unable to add AIC irq domain\n");
228
229	irq_set_default_host(at91_aic_domain);
230
231	/*
232	 * The IVR is used by macro get_irqnr_and_base to read and verify.
233	 * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
234	 */
235	for (i = 0; i < NR_AIC_IRQS; i++) {
236		/* Put hardware irq number in Source Vector Register: */
237		at91_aic_write(AT91_AIC_SVR(i), i);
238		/* Active Low interrupt, with the specified priority */
239		at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
240
241		irq_set_chip_and_handler(i, &at91_aic_chip, handle_level_irq);
242		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
243	}
244
245	at91_aic_hw_init(NR_AIC_IRQS);
246}