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1/*
2 * On-Chip devices setup code for the AT91SAM9G45 family
3 *
4 * Copyright (C) 2009 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12#include <asm/mach/arch.h>
13#include <asm/mach/map.h>
14
15#include <linux/dma-mapping.h>
16#include <linux/gpio.h>
17#include <linux/clk.h>
18#include <linux/platform_device.h>
19#include <linux/i2c-gpio.h>
20#include <linux/atmel-mci.h>
21
22#include <linux/platform_data/at91_adc.h>
23
24#include <linux/fb.h>
25#include <video/atmel_lcdc.h>
26
27#include <mach/at91_adc.h>
28#include <mach/board.h>
29#include <mach/at91sam9g45.h>
30#include <mach/at91sam9g45_matrix.h>
31#include <mach/at91_matrix.h>
32#include <mach/at91sam9_smc.h>
33#include <mach/at_hdmac.h>
34#include <mach/atmel-mci.h>
35
36#include <media/atmel-isi.h>
37
38#include "generic.h"
39#include "clock.h"
40
41
42/* --------------------------------------------------------------------
43 * HDMAC - AHB DMA Controller
44 * -------------------------------------------------------------------- */
45
46#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
47static u64 hdmac_dmamask = DMA_BIT_MASK(32);
48
49static struct resource hdmac_resources[] = {
50 [0] = {
51 .start = AT91SAM9G45_BASE_DMA,
52 .end = AT91SAM9G45_BASE_DMA + SZ_512 - 1,
53 .flags = IORESOURCE_MEM,
54 },
55 [1] = {
56 .start = AT91SAM9G45_ID_DMA,
57 .end = AT91SAM9G45_ID_DMA,
58 .flags = IORESOURCE_IRQ,
59 },
60};
61
62static struct platform_device at_hdmac_device = {
63 .name = "at91sam9g45_dma",
64 .id = -1,
65 .dev = {
66 .dma_mask = &hdmac_dmamask,
67 .coherent_dma_mask = DMA_BIT_MASK(32),
68 },
69 .resource = hdmac_resources,
70 .num_resources = ARRAY_SIZE(hdmac_resources),
71};
72
73void __init at91_add_device_hdmac(void)
74{
75 platform_device_register(&at_hdmac_device);
76}
77#else
78void __init at91_add_device_hdmac(void) {}
79#endif
80
81
82/* --------------------------------------------------------------------
83 * USB Host (OHCI)
84 * -------------------------------------------------------------------- */
85
86#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
87static u64 ohci_dmamask = DMA_BIT_MASK(32);
88static struct at91_usbh_data usbh_ohci_data;
89
90static struct resource usbh_ohci_resources[] = {
91 [0] = {
92 .start = AT91SAM9G45_OHCI_BASE,
93 .end = AT91SAM9G45_OHCI_BASE + SZ_1M - 1,
94 .flags = IORESOURCE_MEM,
95 },
96 [1] = {
97 .start = AT91SAM9G45_ID_UHPHS,
98 .end = AT91SAM9G45_ID_UHPHS,
99 .flags = IORESOURCE_IRQ,
100 },
101};
102
103static struct platform_device at91_usbh_ohci_device = {
104 .name = "at91_ohci",
105 .id = -1,
106 .dev = {
107 .dma_mask = &ohci_dmamask,
108 .coherent_dma_mask = DMA_BIT_MASK(32),
109 .platform_data = &usbh_ohci_data,
110 },
111 .resource = usbh_ohci_resources,
112 .num_resources = ARRAY_SIZE(usbh_ohci_resources),
113};
114
115void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
116{
117 int i;
118
119 if (!data)
120 return;
121
122 /* Enable VBus control for UHP ports */
123 for (i = 0; i < data->ports; i++) {
124 if (gpio_is_valid(data->vbus_pin[i]))
125 at91_set_gpio_output(data->vbus_pin[i],
126 data->vbus_pin_active_low[i]);
127 }
128
129 /* Enable overcurrent notification */
130 for (i = 0; i < data->ports; i++) {
131 if (gpio_is_valid(data->overcurrent_pin[i]))
132 at91_set_gpio_input(data->overcurrent_pin[i], 1);
133 }
134
135 usbh_ohci_data = *data;
136 platform_device_register(&at91_usbh_ohci_device);
137}
138#else
139void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
140#endif
141
142
143/* --------------------------------------------------------------------
144 * USB Host HS (EHCI)
145 * Needs an OHCI host for low and full speed management
146 * -------------------------------------------------------------------- */
147
148#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
149static u64 ehci_dmamask = DMA_BIT_MASK(32);
150static struct at91_usbh_data usbh_ehci_data;
151
152static struct resource usbh_ehci_resources[] = {
153 [0] = {
154 .start = AT91SAM9G45_EHCI_BASE,
155 .end = AT91SAM9G45_EHCI_BASE + SZ_1M - 1,
156 .flags = IORESOURCE_MEM,
157 },
158 [1] = {
159 .start = AT91SAM9G45_ID_UHPHS,
160 .end = AT91SAM9G45_ID_UHPHS,
161 .flags = IORESOURCE_IRQ,
162 },
163};
164
165static struct platform_device at91_usbh_ehci_device = {
166 .name = "atmel-ehci",
167 .id = -1,
168 .dev = {
169 .dma_mask = &ehci_dmamask,
170 .coherent_dma_mask = DMA_BIT_MASK(32),
171 .platform_data = &usbh_ehci_data,
172 },
173 .resource = usbh_ehci_resources,
174 .num_resources = ARRAY_SIZE(usbh_ehci_resources),
175};
176
177void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
178{
179 int i;
180
181 if (!data)
182 return;
183
184 /* Enable VBus control for UHP ports */
185 for (i = 0; i < data->ports; i++) {
186 if (gpio_is_valid(data->vbus_pin[i]))
187 at91_set_gpio_output(data->vbus_pin[i],
188 data->vbus_pin_active_low[i]);
189 }
190
191 usbh_ehci_data = *data;
192 platform_device_register(&at91_usbh_ehci_device);
193}
194#else
195void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) {}
196#endif
197
198
199/* --------------------------------------------------------------------
200 * USB HS Device (Gadget)
201 * -------------------------------------------------------------------- */
202
203#if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE)
204static struct resource usba_udc_resources[] = {
205 [0] = {
206 .start = AT91SAM9G45_UDPHS_FIFO,
207 .end = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1,
208 .flags = IORESOURCE_MEM,
209 },
210 [1] = {
211 .start = AT91SAM9G45_BASE_UDPHS,
212 .end = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1,
213 .flags = IORESOURCE_MEM,
214 },
215 [2] = {
216 .start = AT91SAM9G45_ID_UDPHS,
217 .end = AT91SAM9G45_ID_UDPHS,
218 .flags = IORESOURCE_IRQ,
219 },
220};
221
222#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
223 [idx] = { \
224 .name = nam, \
225 .index = idx, \
226 .fifo_size = maxpkt, \
227 .nr_banks = maxbk, \
228 .can_dma = dma, \
229 .can_isoc = isoc, \
230 }
231
232static struct usba_ep_data usba_udc_ep[] __initdata = {
233 EP("ep0", 0, 64, 1, 0, 0),
234 EP("ep1", 1, 1024, 2, 1, 1),
235 EP("ep2", 2, 1024, 2, 1, 1),
236 EP("ep3", 3, 1024, 3, 1, 0),
237 EP("ep4", 4, 1024, 3, 1, 0),
238 EP("ep5", 5, 1024, 3, 1, 1),
239 EP("ep6", 6, 1024, 3, 1, 1),
240};
241
242#undef EP
243
244/*
245 * pdata doesn't have room for any endpoints, so we need to
246 * append room for the ones we need right after it.
247 */
248static struct {
249 struct usba_platform_data pdata;
250 struct usba_ep_data ep[7];
251} usba_udc_data;
252
253static struct platform_device at91_usba_udc_device = {
254 .name = "atmel_usba_udc",
255 .id = -1,
256 .dev = {
257 .platform_data = &usba_udc_data.pdata,
258 },
259 .resource = usba_udc_resources,
260 .num_resources = ARRAY_SIZE(usba_udc_resources),
261};
262
263void __init at91_add_device_usba(struct usba_platform_data *data)
264{
265 usba_udc_data.pdata.vbus_pin = -EINVAL;
266 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
267 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
268
269 if (data && gpio_is_valid(data->vbus_pin)) {
270 at91_set_gpio_input(data->vbus_pin, 0);
271 at91_set_deglitch(data->vbus_pin, 1);
272 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
273 }
274
275 /* Pullup pin is handled internally by USB device peripheral */
276
277 platform_device_register(&at91_usba_udc_device);
278}
279#else
280void __init at91_add_device_usba(struct usba_platform_data *data) {}
281#endif
282
283
284/* --------------------------------------------------------------------
285 * Ethernet
286 * -------------------------------------------------------------------- */
287
288#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
289static u64 eth_dmamask = DMA_BIT_MASK(32);
290static struct macb_platform_data eth_data;
291
292static struct resource eth_resources[] = {
293 [0] = {
294 .start = AT91SAM9G45_BASE_EMAC,
295 .end = AT91SAM9G45_BASE_EMAC + SZ_16K - 1,
296 .flags = IORESOURCE_MEM,
297 },
298 [1] = {
299 .start = AT91SAM9G45_ID_EMAC,
300 .end = AT91SAM9G45_ID_EMAC,
301 .flags = IORESOURCE_IRQ,
302 },
303};
304
305static struct platform_device at91sam9g45_eth_device = {
306 .name = "macb",
307 .id = -1,
308 .dev = {
309 .dma_mask = ð_dmamask,
310 .coherent_dma_mask = DMA_BIT_MASK(32),
311 .platform_data = ð_data,
312 },
313 .resource = eth_resources,
314 .num_resources = ARRAY_SIZE(eth_resources),
315};
316
317void __init at91_add_device_eth(struct macb_platform_data *data)
318{
319 if (!data)
320 return;
321
322 if (gpio_is_valid(data->phy_irq_pin)) {
323 at91_set_gpio_input(data->phy_irq_pin, 0);
324 at91_set_deglitch(data->phy_irq_pin, 1);
325 }
326
327 /* Pins used for MII and RMII */
328 at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */
329 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */
330 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
331 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
332 at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */
333 at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */
334 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */
335 at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */
336 at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */
337 at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */
338
339 if (!data->is_rmii) {
340 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */
341 at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */
342 at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */
343 at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */
344 at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */
345 at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */
346 at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */
347 at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */
348 }
349
350 eth_data = *data;
351 platform_device_register(&at91sam9g45_eth_device);
352}
353#else
354void __init at91_add_device_eth(struct macb_platform_data *data) {}
355#endif
356
357
358/* --------------------------------------------------------------------
359 * MMC / SD
360 * -------------------------------------------------------------------- */
361
362#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
363static u64 mmc_dmamask = DMA_BIT_MASK(32);
364static struct mci_platform_data mmc0_data, mmc1_data;
365
366static struct resource mmc0_resources[] = {
367 [0] = {
368 .start = AT91SAM9G45_BASE_MCI0,
369 .end = AT91SAM9G45_BASE_MCI0 + SZ_16K - 1,
370 .flags = IORESOURCE_MEM,
371 },
372 [1] = {
373 .start = AT91SAM9G45_ID_MCI0,
374 .end = AT91SAM9G45_ID_MCI0,
375 .flags = IORESOURCE_IRQ,
376 },
377};
378
379static struct platform_device at91sam9g45_mmc0_device = {
380 .name = "atmel_mci",
381 .id = 0,
382 .dev = {
383 .dma_mask = &mmc_dmamask,
384 .coherent_dma_mask = DMA_BIT_MASK(32),
385 .platform_data = &mmc0_data,
386 },
387 .resource = mmc0_resources,
388 .num_resources = ARRAY_SIZE(mmc0_resources),
389};
390
391static struct resource mmc1_resources[] = {
392 [0] = {
393 .start = AT91SAM9G45_BASE_MCI1,
394 .end = AT91SAM9G45_BASE_MCI1 + SZ_16K - 1,
395 .flags = IORESOURCE_MEM,
396 },
397 [1] = {
398 .start = AT91SAM9G45_ID_MCI1,
399 .end = AT91SAM9G45_ID_MCI1,
400 .flags = IORESOURCE_IRQ,
401 },
402};
403
404static struct platform_device at91sam9g45_mmc1_device = {
405 .name = "atmel_mci",
406 .id = 1,
407 .dev = {
408 .dma_mask = &mmc_dmamask,
409 .coherent_dma_mask = DMA_BIT_MASK(32),
410 .platform_data = &mmc1_data,
411 },
412 .resource = mmc1_resources,
413 .num_resources = ARRAY_SIZE(mmc1_resources),
414};
415
416/* Consider only one slot : slot 0 */
417void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
418{
419
420 if (!data)
421 return;
422
423 /* Must have at least one usable slot */
424 if (!data->slot[0].bus_width)
425 return;
426
427#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
428 {
429 struct at_dma_slave *atslave;
430 struct mci_dma_data *alt_atslave;
431
432 alt_atslave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
433 atslave = &alt_atslave->sdata;
434
435 /* DMA slave channel configuration */
436 atslave->dma_dev = &at_hdmac_device.dev;
437 atslave->cfg = ATC_FIFOCFG_HALFFIFO
438 | ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW;
439 if (mmc_id == 0) /* MCI0 */
440 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI0)
441 | ATC_DST_PER(AT_DMA_ID_MCI0);
442
443 else /* MCI1 */
444 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI1)
445 | ATC_DST_PER(AT_DMA_ID_MCI1);
446
447 data->dma_slave = alt_atslave;
448 }
449#endif
450
451
452 /* input/irq */
453 if (gpio_is_valid(data->slot[0].detect_pin)) {
454 at91_set_gpio_input(data->slot[0].detect_pin, 1);
455 at91_set_deglitch(data->slot[0].detect_pin, 1);
456 }
457 if (gpio_is_valid(data->slot[0].wp_pin))
458 at91_set_gpio_input(data->slot[0].wp_pin, 1);
459
460 if (mmc_id == 0) { /* MCI0 */
461
462 /* CLK */
463 at91_set_A_periph(AT91_PIN_PA0, 0);
464
465 /* CMD */
466 at91_set_A_periph(AT91_PIN_PA1, 1);
467
468 /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
469 at91_set_A_periph(AT91_PIN_PA2, 1);
470 if (data->slot[0].bus_width == 4) {
471 at91_set_A_periph(AT91_PIN_PA3, 1);
472 at91_set_A_periph(AT91_PIN_PA4, 1);
473 at91_set_A_periph(AT91_PIN_PA5, 1);
474 if (data->slot[0].bus_width == 8) {
475 at91_set_A_periph(AT91_PIN_PA6, 1);
476 at91_set_A_periph(AT91_PIN_PA7, 1);
477 at91_set_A_periph(AT91_PIN_PA8, 1);
478 at91_set_A_periph(AT91_PIN_PA9, 1);
479 }
480 }
481
482 mmc0_data = *data;
483 platform_device_register(&at91sam9g45_mmc0_device);
484
485 } else { /* MCI1 */
486
487 /* CLK */
488 at91_set_A_periph(AT91_PIN_PA31, 0);
489
490 /* CMD */
491 at91_set_A_periph(AT91_PIN_PA22, 1);
492
493 /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
494 at91_set_A_periph(AT91_PIN_PA23, 1);
495 if (data->slot[0].bus_width == 4) {
496 at91_set_A_periph(AT91_PIN_PA24, 1);
497 at91_set_A_periph(AT91_PIN_PA25, 1);
498 at91_set_A_periph(AT91_PIN_PA26, 1);
499 if (data->slot[0].bus_width == 8) {
500 at91_set_A_periph(AT91_PIN_PA27, 1);
501 at91_set_A_periph(AT91_PIN_PA28, 1);
502 at91_set_A_periph(AT91_PIN_PA29, 1);
503 at91_set_A_periph(AT91_PIN_PA30, 1);
504 }
505 }
506
507 mmc1_data = *data;
508 platform_device_register(&at91sam9g45_mmc1_device);
509
510 }
511}
512#else
513void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
514#endif
515
516
517/* --------------------------------------------------------------------
518 * NAND / SmartMedia
519 * -------------------------------------------------------------------- */
520
521#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
522static struct atmel_nand_data nand_data;
523
524#define NAND_BASE AT91_CHIPSELECT_3
525
526static struct resource nand_resources[] = {
527 [0] = {
528 .start = NAND_BASE,
529 .end = NAND_BASE + SZ_256M - 1,
530 .flags = IORESOURCE_MEM,
531 },
532 [1] = {
533 .start = AT91SAM9G45_BASE_ECC,
534 .end = AT91SAM9G45_BASE_ECC + SZ_512 - 1,
535 .flags = IORESOURCE_MEM,
536 }
537};
538
539static struct platform_device at91sam9g45_nand_device = {
540 .name = "atmel_nand",
541 .id = -1,
542 .dev = {
543 .platform_data = &nand_data,
544 },
545 .resource = nand_resources,
546 .num_resources = ARRAY_SIZE(nand_resources),
547};
548
549void __init at91_add_device_nand(struct atmel_nand_data *data)
550{
551 unsigned long csa;
552
553 if (!data)
554 return;
555
556 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
557 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
558
559 /* enable pin */
560 if (gpio_is_valid(data->enable_pin))
561 at91_set_gpio_output(data->enable_pin, 1);
562
563 /* ready/busy pin */
564 if (gpio_is_valid(data->rdy_pin))
565 at91_set_gpio_input(data->rdy_pin, 1);
566
567 /* card detect pin */
568 if (gpio_is_valid(data->det_pin))
569 at91_set_gpio_input(data->det_pin, 1);
570
571 nand_data = *data;
572 platform_device_register(&at91sam9g45_nand_device);
573}
574#else
575void __init at91_add_device_nand(struct atmel_nand_data *data) {}
576#endif
577
578
579/* --------------------------------------------------------------------
580 * TWI (i2c)
581 * -------------------------------------------------------------------- */
582
583/*
584 * Prefer the GPIO code since the TWI controller isn't robust
585 * (gets overruns and underruns under load) and can only issue
586 * repeated STARTs in one scenario (the driver doesn't yet handle them).
587 */
588#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
589static struct i2c_gpio_platform_data pdata_i2c0 = {
590 .sda_pin = AT91_PIN_PA20,
591 .sda_is_open_drain = 1,
592 .scl_pin = AT91_PIN_PA21,
593 .scl_is_open_drain = 1,
594 .udelay = 5, /* ~100 kHz */
595};
596
597static struct platform_device at91sam9g45_twi0_device = {
598 .name = "i2c-gpio",
599 .id = 0,
600 .dev.platform_data = &pdata_i2c0,
601};
602
603static struct i2c_gpio_platform_data pdata_i2c1 = {
604 .sda_pin = AT91_PIN_PB10,
605 .sda_is_open_drain = 1,
606 .scl_pin = AT91_PIN_PB11,
607 .scl_is_open_drain = 1,
608 .udelay = 5, /* ~100 kHz */
609};
610
611static struct platform_device at91sam9g45_twi1_device = {
612 .name = "i2c-gpio",
613 .id = 1,
614 .dev.platform_data = &pdata_i2c1,
615};
616
617void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
618{
619 i2c_register_board_info(i2c_id, devices, nr_devices);
620
621 if (i2c_id == 0) {
622 at91_set_GPIO_periph(AT91_PIN_PA20, 1); /* TWD (SDA) */
623 at91_set_multi_drive(AT91_PIN_PA20, 1);
624
625 at91_set_GPIO_periph(AT91_PIN_PA21, 1); /* TWCK (SCL) */
626 at91_set_multi_drive(AT91_PIN_PA21, 1);
627
628 platform_device_register(&at91sam9g45_twi0_device);
629 } else {
630 at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* TWD (SDA) */
631 at91_set_multi_drive(AT91_PIN_PB10, 1);
632
633 at91_set_GPIO_periph(AT91_PIN_PB11, 1); /* TWCK (SCL) */
634 at91_set_multi_drive(AT91_PIN_PB11, 1);
635
636 platform_device_register(&at91sam9g45_twi1_device);
637 }
638}
639
640#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
641static struct resource twi0_resources[] = {
642 [0] = {
643 .start = AT91SAM9G45_BASE_TWI0,
644 .end = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1,
645 .flags = IORESOURCE_MEM,
646 },
647 [1] = {
648 .start = AT91SAM9G45_ID_TWI0,
649 .end = AT91SAM9G45_ID_TWI0,
650 .flags = IORESOURCE_IRQ,
651 },
652};
653
654static struct platform_device at91sam9g45_twi0_device = {
655 .name = "at91_i2c",
656 .id = 0,
657 .resource = twi0_resources,
658 .num_resources = ARRAY_SIZE(twi0_resources),
659};
660
661static struct resource twi1_resources[] = {
662 [0] = {
663 .start = AT91SAM9G45_BASE_TWI1,
664 .end = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1,
665 .flags = IORESOURCE_MEM,
666 },
667 [1] = {
668 .start = AT91SAM9G45_ID_TWI1,
669 .end = AT91SAM9G45_ID_TWI1,
670 .flags = IORESOURCE_IRQ,
671 },
672};
673
674static struct platform_device at91sam9g45_twi1_device = {
675 .name = "at91_i2c",
676 .id = 1,
677 .resource = twi1_resources,
678 .num_resources = ARRAY_SIZE(twi1_resources),
679};
680
681void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
682{
683 i2c_register_board_info(i2c_id, devices, nr_devices);
684
685 /* pins used for TWI interface */
686 if (i2c_id == 0) {
687 at91_set_A_periph(AT91_PIN_PA20, 0); /* TWD */
688 at91_set_multi_drive(AT91_PIN_PA20, 1);
689
690 at91_set_A_periph(AT91_PIN_PA21, 0); /* TWCK */
691 at91_set_multi_drive(AT91_PIN_PA21, 1);
692
693 platform_device_register(&at91sam9g45_twi0_device);
694 } else {
695 at91_set_A_periph(AT91_PIN_PB10, 0); /* TWD */
696 at91_set_multi_drive(AT91_PIN_PB10, 1);
697
698 at91_set_A_periph(AT91_PIN_PB11, 0); /* TWCK */
699 at91_set_multi_drive(AT91_PIN_PB11, 1);
700
701 platform_device_register(&at91sam9g45_twi1_device);
702 }
703}
704#else
705void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
706#endif
707
708
709/* --------------------------------------------------------------------
710 * SPI
711 * -------------------------------------------------------------------- */
712
713#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
714static u64 spi_dmamask = DMA_BIT_MASK(32);
715
716static struct resource spi0_resources[] = {
717 [0] = {
718 .start = AT91SAM9G45_BASE_SPI0,
719 .end = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
720 .flags = IORESOURCE_MEM,
721 },
722 [1] = {
723 .start = AT91SAM9G45_ID_SPI0,
724 .end = AT91SAM9G45_ID_SPI0,
725 .flags = IORESOURCE_IRQ,
726 },
727};
728
729static struct platform_device at91sam9g45_spi0_device = {
730 .name = "atmel_spi",
731 .id = 0,
732 .dev = {
733 .dma_mask = &spi_dmamask,
734 .coherent_dma_mask = DMA_BIT_MASK(32),
735 },
736 .resource = spi0_resources,
737 .num_resources = ARRAY_SIZE(spi0_resources),
738};
739
740static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
741
742static struct resource spi1_resources[] = {
743 [0] = {
744 .start = AT91SAM9G45_BASE_SPI1,
745 .end = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
746 .flags = IORESOURCE_MEM,
747 },
748 [1] = {
749 .start = AT91SAM9G45_ID_SPI1,
750 .end = AT91SAM9G45_ID_SPI1,
751 .flags = IORESOURCE_IRQ,
752 },
753};
754
755static struct platform_device at91sam9g45_spi1_device = {
756 .name = "atmel_spi",
757 .id = 1,
758 .dev = {
759 .dma_mask = &spi_dmamask,
760 .coherent_dma_mask = DMA_BIT_MASK(32),
761 },
762 .resource = spi1_resources,
763 .num_resources = ARRAY_SIZE(spi1_resources),
764};
765
766static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
767
768void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
769{
770 int i;
771 unsigned long cs_pin;
772 short enable_spi0 = 0;
773 short enable_spi1 = 0;
774
775 /* Choose SPI chip-selects */
776 for (i = 0; i < nr_devices; i++) {
777 if (devices[i].controller_data)
778 cs_pin = (unsigned long) devices[i].controller_data;
779 else if (devices[i].bus_num == 0)
780 cs_pin = spi0_standard_cs[devices[i].chip_select];
781 else
782 cs_pin = spi1_standard_cs[devices[i].chip_select];
783
784 if (!gpio_is_valid(cs_pin))
785 continue;
786
787 if (devices[i].bus_num == 0)
788 enable_spi0 = 1;
789 else
790 enable_spi1 = 1;
791
792 /* enable chip-select pin */
793 at91_set_gpio_output(cs_pin, 1);
794
795 /* pass chip-select pin to driver */
796 devices[i].controller_data = (void *) cs_pin;
797 }
798
799 spi_register_board_info(devices, nr_devices);
800
801 /* Configure SPI bus(es) */
802 if (enable_spi0) {
803 at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */
804 at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */
805 at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */
806
807 platform_device_register(&at91sam9g45_spi0_device);
808 }
809 if (enable_spi1) {
810 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */
811 at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */
812 at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */
813
814 platform_device_register(&at91sam9g45_spi1_device);
815 }
816}
817#else
818void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
819#endif
820
821
822/* --------------------------------------------------------------------
823 * AC97
824 * -------------------------------------------------------------------- */
825
826#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
827static u64 ac97_dmamask = DMA_BIT_MASK(32);
828static struct ac97c_platform_data ac97_data;
829
830static struct resource ac97_resources[] = {
831 [0] = {
832 .start = AT91SAM9G45_BASE_AC97C,
833 .end = AT91SAM9G45_BASE_AC97C + SZ_16K - 1,
834 .flags = IORESOURCE_MEM,
835 },
836 [1] = {
837 .start = AT91SAM9G45_ID_AC97C,
838 .end = AT91SAM9G45_ID_AC97C,
839 .flags = IORESOURCE_IRQ,
840 },
841};
842
843static struct platform_device at91sam9g45_ac97_device = {
844 .name = "atmel_ac97c",
845 .id = 0,
846 .dev = {
847 .dma_mask = &ac97_dmamask,
848 .coherent_dma_mask = DMA_BIT_MASK(32),
849 .platform_data = &ac97_data,
850 },
851 .resource = ac97_resources,
852 .num_resources = ARRAY_SIZE(ac97_resources),
853};
854
855void __init at91_add_device_ac97(struct ac97c_platform_data *data)
856{
857 if (!data)
858 return;
859
860 at91_set_A_periph(AT91_PIN_PD8, 0); /* AC97FS */
861 at91_set_A_periph(AT91_PIN_PD9, 0); /* AC97CK */
862 at91_set_A_periph(AT91_PIN_PD7, 0); /* AC97TX */
863 at91_set_A_periph(AT91_PIN_PD6, 0); /* AC97RX */
864
865 /* reset */
866 if (gpio_is_valid(data->reset_pin))
867 at91_set_gpio_output(data->reset_pin, 0);
868
869 ac97_data = *data;
870 platform_device_register(&at91sam9g45_ac97_device);
871}
872#else
873void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
874#endif
875
876/* --------------------------------------------------------------------
877 * Image Sensor Interface
878 * -------------------------------------------------------------------- */
879#if defined(CONFIG_VIDEO_ATMEL_ISI) || defined(CONFIG_VIDEO_ATMEL_ISI_MODULE)
880static u64 isi_dmamask = DMA_BIT_MASK(32);
881static struct isi_platform_data isi_data;
882
883struct resource isi_resources[] = {
884 [0] = {
885 .start = AT91SAM9G45_BASE_ISI,
886 .end = AT91SAM9G45_BASE_ISI + SZ_16K - 1,
887 .flags = IORESOURCE_MEM,
888 },
889 [1] = {
890 .start = AT91SAM9G45_ID_ISI,
891 .end = AT91SAM9G45_ID_ISI,
892 .flags = IORESOURCE_IRQ,
893 },
894};
895
896static struct platform_device at91sam9g45_isi_device = {
897 .name = "atmel_isi",
898 .id = 0,
899 .dev = {
900 .dma_mask = &isi_dmamask,
901 .coherent_dma_mask = DMA_BIT_MASK(32),
902 .platform_data = &isi_data,
903 },
904 .resource = isi_resources,
905 .num_resources = ARRAY_SIZE(isi_resources),
906};
907
908static struct clk_lookup isi_mck_lookups[] = {
909 CLKDEV_CON_DEV_ID("isi_mck", "atmel_isi.0", NULL),
910};
911
912void __init at91_add_device_isi(struct isi_platform_data *data,
913 bool use_pck_as_mck)
914{
915 struct clk *pck;
916 struct clk *parent;
917
918 if (!data)
919 return;
920 isi_data = *data;
921
922 at91_set_A_periph(AT91_PIN_PB20, 0); /* ISI_D0 */
923 at91_set_A_periph(AT91_PIN_PB21, 0); /* ISI_D1 */
924 at91_set_A_periph(AT91_PIN_PB22, 0); /* ISI_D2 */
925 at91_set_A_periph(AT91_PIN_PB23, 0); /* ISI_D3 */
926 at91_set_A_periph(AT91_PIN_PB24, 0); /* ISI_D4 */
927 at91_set_A_periph(AT91_PIN_PB25, 0); /* ISI_D5 */
928 at91_set_A_periph(AT91_PIN_PB26, 0); /* ISI_D6 */
929 at91_set_A_periph(AT91_PIN_PB27, 0); /* ISI_D7 */
930 at91_set_A_periph(AT91_PIN_PB28, 0); /* ISI_PCK */
931 at91_set_A_periph(AT91_PIN_PB30, 0); /* ISI_HSYNC */
932 at91_set_A_periph(AT91_PIN_PB29, 0); /* ISI_VSYNC */
933 at91_set_B_periph(AT91_PIN_PB8, 0); /* ISI_PD8 */
934 at91_set_B_periph(AT91_PIN_PB9, 0); /* ISI_PD9 */
935 at91_set_B_periph(AT91_PIN_PB10, 0); /* ISI_PD10 */
936 at91_set_B_periph(AT91_PIN_PB11, 0); /* ISI_PD11 */
937
938 platform_device_register(&at91sam9g45_isi_device);
939
940 if (use_pck_as_mck) {
941 at91_set_B_periph(AT91_PIN_PB31, 0); /* ISI_MCK (PCK1) */
942
943 pck = clk_get(NULL, "pck1");
944 parent = clk_get(NULL, "plla");
945
946 BUG_ON(IS_ERR(pck) || IS_ERR(parent));
947
948 if (clk_set_parent(pck, parent)) {
949 pr_err("Failed to set PCK's parent\n");
950 } else {
951 /* Register PCK as ISI_MCK */
952 isi_mck_lookups[0].clk = pck;
953 clkdev_add_table(isi_mck_lookups,
954 ARRAY_SIZE(isi_mck_lookups));
955 }
956
957 clk_put(pck);
958 clk_put(parent);
959 }
960}
961#else
962void __init at91_add_device_isi(struct isi_platform_data *data,
963 bool use_pck_as_mck) {}
964#endif
965
966
967/* --------------------------------------------------------------------
968 * LCD Controller
969 * -------------------------------------------------------------------- */
970
971#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
972static u64 lcdc_dmamask = DMA_BIT_MASK(32);
973static struct atmel_lcdfb_info lcdc_data;
974
975static struct resource lcdc_resources[] = {
976 [0] = {
977 .start = AT91SAM9G45_LCDC_BASE,
978 .end = AT91SAM9G45_LCDC_BASE + SZ_4K - 1,
979 .flags = IORESOURCE_MEM,
980 },
981 [1] = {
982 .start = AT91SAM9G45_ID_LCDC,
983 .end = AT91SAM9G45_ID_LCDC,
984 .flags = IORESOURCE_IRQ,
985 },
986};
987
988static struct platform_device at91_lcdc_device = {
989 .name = "atmel_lcdfb",
990 .id = 0,
991 .dev = {
992 .dma_mask = &lcdc_dmamask,
993 .coherent_dma_mask = DMA_BIT_MASK(32),
994 .platform_data = &lcdc_data,
995 },
996 .resource = lcdc_resources,
997 .num_resources = ARRAY_SIZE(lcdc_resources),
998};
999
1000void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
1001{
1002 if (!data)
1003 return;
1004
1005 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
1006
1007 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
1008 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
1009 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
1010 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
1011 at91_set_A_periph(AT91_PIN_PE6, 0); /* LCDDEN */
1012 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
1013 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
1014 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
1015 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
1016 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
1017 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
1018 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
1019 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
1020 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
1021 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
1022 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
1023 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
1024 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
1025 at91_set_A_periph(AT91_PIN_PE20, 0); /* LCDD13 */
1026 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
1027 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
1028 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
1029 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
1030 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
1031 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
1032 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
1033 at91_set_A_periph(AT91_PIN_PE28, 0); /* LCDD21 */
1034 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
1035 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
1036
1037 lcdc_data = *data;
1038 platform_device_register(&at91_lcdc_device);
1039}
1040#else
1041void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
1042#endif
1043
1044
1045/* --------------------------------------------------------------------
1046 * Timer/Counter block
1047 * -------------------------------------------------------------------- */
1048
1049#ifdef CONFIG_ATMEL_TCLIB
1050static struct resource tcb0_resources[] = {
1051 [0] = {
1052 .start = AT91SAM9G45_BASE_TCB0,
1053 .end = AT91SAM9G45_BASE_TCB0 + SZ_256 - 1,
1054 .flags = IORESOURCE_MEM,
1055 },
1056 [1] = {
1057 .start = AT91SAM9G45_ID_TCB,
1058 .end = AT91SAM9G45_ID_TCB,
1059 .flags = IORESOURCE_IRQ,
1060 },
1061};
1062
1063static struct platform_device at91sam9g45_tcb0_device = {
1064 .name = "atmel_tcb",
1065 .id = 0,
1066 .resource = tcb0_resources,
1067 .num_resources = ARRAY_SIZE(tcb0_resources),
1068};
1069
1070/* TCB1 begins with TC3 */
1071static struct resource tcb1_resources[] = {
1072 [0] = {
1073 .start = AT91SAM9G45_BASE_TCB1,
1074 .end = AT91SAM9G45_BASE_TCB1 + SZ_256 - 1,
1075 .flags = IORESOURCE_MEM,
1076 },
1077 [1] = {
1078 .start = AT91SAM9G45_ID_TCB,
1079 .end = AT91SAM9G45_ID_TCB,
1080 .flags = IORESOURCE_IRQ,
1081 },
1082};
1083
1084static struct platform_device at91sam9g45_tcb1_device = {
1085 .name = "atmel_tcb",
1086 .id = 1,
1087 .resource = tcb1_resources,
1088 .num_resources = ARRAY_SIZE(tcb1_resources),
1089};
1090
1091static void __init at91_add_device_tc(void)
1092{
1093 platform_device_register(&at91sam9g45_tcb0_device);
1094 platform_device_register(&at91sam9g45_tcb1_device);
1095}
1096#else
1097static void __init at91_add_device_tc(void) { }
1098#endif
1099
1100
1101/* --------------------------------------------------------------------
1102 * RTC
1103 * -------------------------------------------------------------------- */
1104
1105#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
1106static struct resource rtc_resources[] = {
1107 [0] = {
1108 .start = AT91SAM9G45_BASE_RTC,
1109 .end = AT91SAM9G45_BASE_RTC + SZ_256 - 1,
1110 .flags = IORESOURCE_MEM,
1111 },
1112 [1] = {
1113 .start = AT91_ID_SYS,
1114 .end = AT91_ID_SYS,
1115 .flags = IORESOURCE_IRQ,
1116 },
1117};
1118
1119static struct platform_device at91sam9g45_rtc_device = {
1120 .name = "at91_rtc",
1121 .id = -1,
1122 .resource = rtc_resources,
1123 .num_resources = ARRAY_SIZE(rtc_resources),
1124};
1125
1126static void __init at91_add_device_rtc(void)
1127{
1128 platform_device_register(&at91sam9g45_rtc_device);
1129}
1130#else
1131static void __init at91_add_device_rtc(void) {}
1132#endif
1133
1134
1135/* --------------------------------------------------------------------
1136 * Touchscreen
1137 * -------------------------------------------------------------------- */
1138
1139#if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
1140static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
1141static struct at91_tsadcc_data tsadcc_data;
1142
1143static struct resource tsadcc_resources[] = {
1144 [0] = {
1145 .start = AT91SAM9G45_BASE_TSC,
1146 .end = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
1147 .flags = IORESOURCE_MEM,
1148 },
1149 [1] = {
1150 .start = AT91SAM9G45_ID_TSC,
1151 .end = AT91SAM9G45_ID_TSC,
1152 .flags = IORESOURCE_IRQ,
1153 }
1154};
1155
1156static struct platform_device at91sam9g45_tsadcc_device = {
1157 .name = "atmel_tsadcc",
1158 .id = -1,
1159 .dev = {
1160 .dma_mask = &tsadcc_dmamask,
1161 .coherent_dma_mask = DMA_BIT_MASK(32),
1162 .platform_data = &tsadcc_data,
1163 },
1164 .resource = tsadcc_resources,
1165 .num_resources = ARRAY_SIZE(tsadcc_resources),
1166};
1167
1168void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data)
1169{
1170 if (!data)
1171 return;
1172
1173 at91_set_gpio_input(AT91_PIN_PD20, 0); /* AD0_XR */
1174 at91_set_gpio_input(AT91_PIN_PD21, 0); /* AD1_XL */
1175 at91_set_gpio_input(AT91_PIN_PD22, 0); /* AD2_YT */
1176 at91_set_gpio_input(AT91_PIN_PD23, 0); /* AD3_TB */
1177
1178 tsadcc_data = *data;
1179 platform_device_register(&at91sam9g45_tsadcc_device);
1180}
1181#else
1182void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {}
1183#endif
1184
1185
1186/* --------------------------------------------------------------------
1187 * ADC
1188 * -------------------------------------------------------------------- */
1189
1190#if IS_ENABLED(CONFIG_AT91_ADC)
1191static struct at91_adc_data adc_data;
1192
1193static struct resource adc_resources[] = {
1194 [0] = {
1195 .start = AT91SAM9G45_BASE_TSC,
1196 .end = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
1197 .flags = IORESOURCE_MEM,
1198 },
1199 [1] = {
1200 .start = AT91SAM9G45_ID_TSC,
1201 .end = AT91SAM9G45_ID_TSC,
1202 .flags = IORESOURCE_IRQ,
1203 }
1204};
1205
1206static struct platform_device at91_adc_device = {
1207 .name = "at91_adc",
1208 .id = -1,
1209 .dev = {
1210 .platform_data = &adc_data,
1211 },
1212 .resource = adc_resources,
1213 .num_resources = ARRAY_SIZE(adc_resources),
1214};
1215
1216static struct at91_adc_trigger at91_adc_triggers[] = {
1217 [0] = {
1218 .name = "external-rising",
1219 .value = 1,
1220 .is_external = true,
1221 },
1222 [1] = {
1223 .name = "external-falling",
1224 .value = 2,
1225 .is_external = true,
1226 },
1227 [2] = {
1228 .name = "external-any",
1229 .value = 3,
1230 .is_external = true,
1231 },
1232 [3] = {
1233 .name = "continuous",
1234 .value = 6,
1235 .is_external = false,
1236 },
1237};
1238
1239static struct at91_adc_reg_desc at91_adc_register_g45 = {
1240 .channel_base = AT91_ADC_CHR(0),
1241 .drdy_mask = AT91_ADC_DRDY,
1242 .status_register = AT91_ADC_SR,
1243 .trigger_register = 0x08,
1244};
1245
1246void __init at91_add_device_adc(struct at91_adc_data *data)
1247{
1248 if (!data)
1249 return;
1250
1251 if (test_bit(0, &data->channels_used))
1252 at91_set_gpio_input(AT91_PIN_PD20, 0);
1253 if (test_bit(1, &data->channels_used))
1254 at91_set_gpio_input(AT91_PIN_PD21, 0);
1255 if (test_bit(2, &data->channels_used))
1256 at91_set_gpio_input(AT91_PIN_PD22, 0);
1257 if (test_bit(3, &data->channels_used))
1258 at91_set_gpio_input(AT91_PIN_PD23, 0);
1259 if (test_bit(4, &data->channels_used))
1260 at91_set_gpio_input(AT91_PIN_PD24, 0);
1261 if (test_bit(5, &data->channels_used))
1262 at91_set_gpio_input(AT91_PIN_PD25, 0);
1263 if (test_bit(6, &data->channels_used))
1264 at91_set_gpio_input(AT91_PIN_PD26, 0);
1265 if (test_bit(7, &data->channels_used))
1266 at91_set_gpio_input(AT91_PIN_PD27, 0);
1267
1268 if (data->use_external_triggers)
1269 at91_set_A_periph(AT91_PIN_PD28, 0);
1270
1271 data->num_channels = 8;
1272 data->startup_time = 40;
1273 data->registers = &at91_adc_register_g45;
1274 data->trigger_number = 4;
1275 data->trigger_list = at91_adc_triggers;
1276
1277 adc_data = *data;
1278 platform_device_register(&at91_adc_device);
1279}
1280#else
1281void __init at91_add_device_adc(struct at91_adc_data *data) {}
1282#endif
1283
1284/* --------------------------------------------------------------------
1285 * RTT
1286 * -------------------------------------------------------------------- */
1287
1288static struct resource rtt_resources[] = {
1289 {
1290 .start = AT91SAM9G45_BASE_RTT,
1291 .end = AT91SAM9G45_BASE_RTT + SZ_16 - 1,
1292 .flags = IORESOURCE_MEM,
1293 }, {
1294 .flags = IORESOURCE_MEM,
1295 }
1296};
1297
1298static struct platform_device at91sam9g45_rtt_device = {
1299 .name = "at91_rtt",
1300 .id = 0,
1301 .resource = rtt_resources,
1302};
1303
1304#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
1305static void __init at91_add_device_rtt_rtc(void)
1306{
1307 at91sam9g45_rtt_device.name = "rtc-at91sam9";
1308 /*
1309 * The second resource is needed:
1310 * GPBR will serve as the storage for RTC time offset
1311 */
1312 at91sam9g45_rtt_device.num_resources = 2;
1313 rtt_resources[1].start = AT91SAM9G45_BASE_GPBR +
1314 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
1315 rtt_resources[1].end = rtt_resources[1].start + 3;
1316}
1317#else
1318static void __init at91_add_device_rtt_rtc(void)
1319{
1320 /* Only one resource is needed: RTT not used as RTC */
1321 at91sam9g45_rtt_device.num_resources = 1;
1322}
1323#endif
1324
1325static void __init at91_add_device_rtt(void)
1326{
1327 at91_add_device_rtt_rtc();
1328 platform_device_register(&at91sam9g45_rtt_device);
1329}
1330
1331
1332/* --------------------------------------------------------------------
1333 * TRNG
1334 * -------------------------------------------------------------------- */
1335
1336#if defined(CONFIG_HW_RANDOM_ATMEL) || defined(CONFIG_HW_RANDOM_ATMEL_MODULE)
1337static struct resource trng_resources[] = {
1338 {
1339 .start = AT91SAM9G45_BASE_TRNG,
1340 .end = AT91SAM9G45_BASE_TRNG + SZ_16K - 1,
1341 .flags = IORESOURCE_MEM,
1342 },
1343};
1344
1345static struct platform_device at91sam9g45_trng_device = {
1346 .name = "atmel-trng",
1347 .id = -1,
1348 .resource = trng_resources,
1349 .num_resources = ARRAY_SIZE(trng_resources),
1350};
1351
1352static void __init at91_add_device_trng(void)
1353{
1354 platform_device_register(&at91sam9g45_trng_device);
1355}
1356#else
1357static void __init at91_add_device_trng(void) {}
1358#endif
1359
1360/* --------------------------------------------------------------------
1361 * Watchdog
1362 * -------------------------------------------------------------------- */
1363
1364#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
1365static struct resource wdt_resources[] = {
1366 {
1367 .start = AT91SAM9G45_BASE_WDT,
1368 .end = AT91SAM9G45_BASE_WDT + SZ_16 - 1,
1369 .flags = IORESOURCE_MEM,
1370 }
1371};
1372
1373static struct platform_device at91sam9g45_wdt_device = {
1374 .name = "at91_wdt",
1375 .id = -1,
1376 .resource = wdt_resources,
1377 .num_resources = ARRAY_SIZE(wdt_resources),
1378};
1379
1380static void __init at91_add_device_watchdog(void)
1381{
1382 platform_device_register(&at91sam9g45_wdt_device);
1383}
1384#else
1385static void __init at91_add_device_watchdog(void) {}
1386#endif
1387
1388
1389/* --------------------------------------------------------------------
1390 * PWM
1391 * --------------------------------------------------------------------*/
1392
1393#if defined(CONFIG_ATMEL_PWM) || defined(CONFIG_ATMEL_PWM_MODULE)
1394static u32 pwm_mask;
1395
1396static struct resource pwm_resources[] = {
1397 [0] = {
1398 .start = AT91SAM9G45_BASE_PWMC,
1399 .end = AT91SAM9G45_BASE_PWMC + SZ_16K - 1,
1400 .flags = IORESOURCE_MEM,
1401 },
1402 [1] = {
1403 .start = AT91SAM9G45_ID_PWMC,
1404 .end = AT91SAM9G45_ID_PWMC,
1405 .flags = IORESOURCE_IRQ,
1406 },
1407};
1408
1409static struct platform_device at91sam9g45_pwm0_device = {
1410 .name = "atmel_pwm",
1411 .id = -1,
1412 .dev = {
1413 .platform_data = &pwm_mask,
1414 },
1415 .resource = pwm_resources,
1416 .num_resources = ARRAY_SIZE(pwm_resources),
1417};
1418
1419void __init at91_add_device_pwm(u32 mask)
1420{
1421 if (mask & (1 << AT91_PWM0))
1422 at91_set_B_periph(AT91_PIN_PD24, 1); /* enable PWM0 */
1423
1424 if (mask & (1 << AT91_PWM1))
1425 at91_set_B_periph(AT91_PIN_PD31, 1); /* enable PWM1 */
1426
1427 if (mask & (1 << AT91_PWM2))
1428 at91_set_B_periph(AT91_PIN_PD26, 1); /* enable PWM2 */
1429
1430 if (mask & (1 << AT91_PWM3))
1431 at91_set_B_periph(AT91_PIN_PD0, 1); /* enable PWM3 */
1432
1433 pwm_mask = mask;
1434
1435 platform_device_register(&at91sam9g45_pwm0_device);
1436}
1437#else
1438void __init at91_add_device_pwm(u32 mask) {}
1439#endif
1440
1441
1442/* --------------------------------------------------------------------
1443 * SSC -- Synchronous Serial Controller
1444 * -------------------------------------------------------------------- */
1445
1446#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
1447static u64 ssc0_dmamask = DMA_BIT_MASK(32);
1448
1449static struct resource ssc0_resources[] = {
1450 [0] = {
1451 .start = AT91SAM9G45_BASE_SSC0,
1452 .end = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1,
1453 .flags = IORESOURCE_MEM,
1454 },
1455 [1] = {
1456 .start = AT91SAM9G45_ID_SSC0,
1457 .end = AT91SAM9G45_ID_SSC0,
1458 .flags = IORESOURCE_IRQ,
1459 },
1460};
1461
1462static struct platform_device at91sam9g45_ssc0_device = {
1463 .name = "ssc",
1464 .id = 0,
1465 .dev = {
1466 .dma_mask = &ssc0_dmamask,
1467 .coherent_dma_mask = DMA_BIT_MASK(32),
1468 },
1469 .resource = ssc0_resources,
1470 .num_resources = ARRAY_SIZE(ssc0_resources),
1471};
1472
1473static inline void configure_ssc0_pins(unsigned pins)
1474{
1475 if (pins & ATMEL_SSC_TF)
1476 at91_set_A_periph(AT91_PIN_PD1, 1);
1477 if (pins & ATMEL_SSC_TK)
1478 at91_set_A_periph(AT91_PIN_PD0, 1);
1479 if (pins & ATMEL_SSC_TD)
1480 at91_set_A_periph(AT91_PIN_PD2, 1);
1481 if (pins & ATMEL_SSC_RD)
1482 at91_set_A_periph(AT91_PIN_PD3, 1);
1483 if (pins & ATMEL_SSC_RK)
1484 at91_set_A_periph(AT91_PIN_PD4, 1);
1485 if (pins & ATMEL_SSC_RF)
1486 at91_set_A_periph(AT91_PIN_PD5, 1);
1487}
1488
1489static u64 ssc1_dmamask = DMA_BIT_MASK(32);
1490
1491static struct resource ssc1_resources[] = {
1492 [0] = {
1493 .start = AT91SAM9G45_BASE_SSC1,
1494 .end = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1,
1495 .flags = IORESOURCE_MEM,
1496 },
1497 [1] = {
1498 .start = AT91SAM9G45_ID_SSC1,
1499 .end = AT91SAM9G45_ID_SSC1,
1500 .flags = IORESOURCE_IRQ,
1501 },
1502};
1503
1504static struct platform_device at91sam9g45_ssc1_device = {
1505 .name = "ssc",
1506 .id = 1,
1507 .dev = {
1508 .dma_mask = &ssc1_dmamask,
1509 .coherent_dma_mask = DMA_BIT_MASK(32),
1510 },
1511 .resource = ssc1_resources,
1512 .num_resources = ARRAY_SIZE(ssc1_resources),
1513};
1514
1515static inline void configure_ssc1_pins(unsigned pins)
1516{
1517 if (pins & ATMEL_SSC_TF)
1518 at91_set_A_periph(AT91_PIN_PD14, 1);
1519 if (pins & ATMEL_SSC_TK)
1520 at91_set_A_periph(AT91_PIN_PD12, 1);
1521 if (pins & ATMEL_SSC_TD)
1522 at91_set_A_periph(AT91_PIN_PD10, 1);
1523 if (pins & ATMEL_SSC_RD)
1524 at91_set_A_periph(AT91_PIN_PD11, 1);
1525 if (pins & ATMEL_SSC_RK)
1526 at91_set_A_periph(AT91_PIN_PD13, 1);
1527 if (pins & ATMEL_SSC_RF)
1528 at91_set_A_periph(AT91_PIN_PD15, 1);
1529}
1530
1531/*
1532 * SSC controllers are accessed through library code, instead of any
1533 * kind of all-singing/all-dancing driver. For example one could be
1534 * used by a particular I2S audio codec's driver, while another one
1535 * on the same system might be used by a custom data capture driver.
1536 */
1537void __init at91_add_device_ssc(unsigned id, unsigned pins)
1538{
1539 struct platform_device *pdev;
1540
1541 /*
1542 * NOTE: caller is responsible for passing information matching
1543 * "pins" to whatever will be using each particular controller.
1544 */
1545 switch (id) {
1546 case AT91SAM9G45_ID_SSC0:
1547 pdev = &at91sam9g45_ssc0_device;
1548 configure_ssc0_pins(pins);
1549 break;
1550 case AT91SAM9G45_ID_SSC1:
1551 pdev = &at91sam9g45_ssc1_device;
1552 configure_ssc1_pins(pins);
1553 break;
1554 default:
1555 return;
1556 }
1557
1558 platform_device_register(pdev);
1559}
1560
1561#else
1562void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1563#endif
1564
1565
1566/* --------------------------------------------------------------------
1567 * UART
1568 * -------------------------------------------------------------------- */
1569
1570#if defined(CONFIG_SERIAL_ATMEL)
1571static struct resource dbgu_resources[] = {
1572 [0] = {
1573 .start = AT91SAM9G45_BASE_DBGU,
1574 .end = AT91SAM9G45_BASE_DBGU + SZ_512 - 1,
1575 .flags = IORESOURCE_MEM,
1576 },
1577 [1] = {
1578 .start = AT91_ID_SYS,
1579 .end = AT91_ID_SYS,
1580 .flags = IORESOURCE_IRQ,
1581 },
1582};
1583
1584static struct atmel_uart_data dbgu_data = {
1585 .use_dma_tx = 0,
1586 .use_dma_rx = 0,
1587};
1588
1589static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1590
1591static struct platform_device at91sam9g45_dbgu_device = {
1592 .name = "atmel_usart",
1593 .id = 0,
1594 .dev = {
1595 .dma_mask = &dbgu_dmamask,
1596 .coherent_dma_mask = DMA_BIT_MASK(32),
1597 .platform_data = &dbgu_data,
1598 },
1599 .resource = dbgu_resources,
1600 .num_resources = ARRAY_SIZE(dbgu_resources),
1601};
1602
1603static inline void configure_dbgu_pins(void)
1604{
1605 at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */
1606 at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */
1607}
1608
1609static struct resource uart0_resources[] = {
1610 [0] = {
1611 .start = AT91SAM9G45_BASE_US0,
1612 .end = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
1613 .flags = IORESOURCE_MEM,
1614 },
1615 [1] = {
1616 .start = AT91SAM9G45_ID_US0,
1617 .end = AT91SAM9G45_ID_US0,
1618 .flags = IORESOURCE_IRQ,
1619 },
1620};
1621
1622static struct atmel_uart_data uart0_data = {
1623 .use_dma_tx = 1,
1624 .use_dma_rx = 1,
1625};
1626
1627static u64 uart0_dmamask = DMA_BIT_MASK(32);
1628
1629static struct platform_device at91sam9g45_uart0_device = {
1630 .name = "atmel_usart",
1631 .id = 1,
1632 .dev = {
1633 .dma_mask = &uart0_dmamask,
1634 .coherent_dma_mask = DMA_BIT_MASK(32),
1635 .platform_data = &uart0_data,
1636 },
1637 .resource = uart0_resources,
1638 .num_resources = ARRAY_SIZE(uart0_resources),
1639};
1640
1641static inline void configure_usart0_pins(unsigned pins)
1642{
1643 at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */
1644 at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */
1645
1646 if (pins & ATMEL_UART_RTS)
1647 at91_set_B_periph(AT91_PIN_PB17, 0); /* RTS0 */
1648 if (pins & ATMEL_UART_CTS)
1649 at91_set_B_periph(AT91_PIN_PB15, 0); /* CTS0 */
1650}
1651
1652static struct resource uart1_resources[] = {
1653 [0] = {
1654 .start = AT91SAM9G45_BASE_US1,
1655 .end = AT91SAM9G45_BASE_US1 + SZ_16K - 1,
1656 .flags = IORESOURCE_MEM,
1657 },
1658 [1] = {
1659 .start = AT91SAM9G45_ID_US1,
1660 .end = AT91SAM9G45_ID_US1,
1661 .flags = IORESOURCE_IRQ,
1662 },
1663};
1664
1665static struct atmel_uart_data uart1_data = {
1666 .use_dma_tx = 1,
1667 .use_dma_rx = 1,
1668};
1669
1670static u64 uart1_dmamask = DMA_BIT_MASK(32);
1671
1672static struct platform_device at91sam9g45_uart1_device = {
1673 .name = "atmel_usart",
1674 .id = 2,
1675 .dev = {
1676 .dma_mask = &uart1_dmamask,
1677 .coherent_dma_mask = DMA_BIT_MASK(32),
1678 .platform_data = &uart1_data,
1679 },
1680 .resource = uart1_resources,
1681 .num_resources = ARRAY_SIZE(uart1_resources),
1682};
1683
1684static inline void configure_usart1_pins(unsigned pins)
1685{
1686 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */
1687 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */
1688
1689 if (pins & ATMEL_UART_RTS)
1690 at91_set_A_periph(AT91_PIN_PD16, 0); /* RTS1 */
1691 if (pins & ATMEL_UART_CTS)
1692 at91_set_A_periph(AT91_PIN_PD17, 0); /* CTS1 */
1693}
1694
1695static struct resource uart2_resources[] = {
1696 [0] = {
1697 .start = AT91SAM9G45_BASE_US2,
1698 .end = AT91SAM9G45_BASE_US2 + SZ_16K - 1,
1699 .flags = IORESOURCE_MEM,
1700 },
1701 [1] = {
1702 .start = AT91SAM9G45_ID_US2,
1703 .end = AT91SAM9G45_ID_US2,
1704 .flags = IORESOURCE_IRQ,
1705 },
1706};
1707
1708static struct atmel_uart_data uart2_data = {
1709 .use_dma_tx = 1,
1710 .use_dma_rx = 1,
1711};
1712
1713static u64 uart2_dmamask = DMA_BIT_MASK(32);
1714
1715static struct platform_device at91sam9g45_uart2_device = {
1716 .name = "atmel_usart",
1717 .id = 3,
1718 .dev = {
1719 .dma_mask = &uart2_dmamask,
1720 .coherent_dma_mask = DMA_BIT_MASK(32),
1721 .platform_data = &uart2_data,
1722 },
1723 .resource = uart2_resources,
1724 .num_resources = ARRAY_SIZE(uart2_resources),
1725};
1726
1727static inline void configure_usart2_pins(unsigned pins)
1728{
1729 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD2 */
1730 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD2 */
1731
1732 if (pins & ATMEL_UART_RTS)
1733 at91_set_B_periph(AT91_PIN_PC9, 0); /* RTS2 */
1734 if (pins & ATMEL_UART_CTS)
1735 at91_set_B_periph(AT91_PIN_PC11, 0); /* CTS2 */
1736}
1737
1738static struct resource uart3_resources[] = {
1739 [0] = {
1740 .start = AT91SAM9G45_BASE_US3,
1741 .end = AT91SAM9G45_BASE_US3 + SZ_16K - 1,
1742 .flags = IORESOURCE_MEM,
1743 },
1744 [1] = {
1745 .start = AT91SAM9G45_ID_US3,
1746 .end = AT91SAM9G45_ID_US3,
1747 .flags = IORESOURCE_IRQ,
1748 },
1749};
1750
1751static struct atmel_uart_data uart3_data = {
1752 .use_dma_tx = 1,
1753 .use_dma_rx = 1,
1754};
1755
1756static u64 uart3_dmamask = DMA_BIT_MASK(32);
1757
1758static struct platform_device at91sam9g45_uart3_device = {
1759 .name = "atmel_usart",
1760 .id = 4,
1761 .dev = {
1762 .dma_mask = &uart3_dmamask,
1763 .coherent_dma_mask = DMA_BIT_MASK(32),
1764 .platform_data = &uart3_data,
1765 },
1766 .resource = uart3_resources,
1767 .num_resources = ARRAY_SIZE(uart3_resources),
1768};
1769
1770static inline void configure_usart3_pins(unsigned pins)
1771{
1772 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD3 */
1773 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD3 */
1774
1775 if (pins & ATMEL_UART_RTS)
1776 at91_set_B_periph(AT91_PIN_PA23, 0); /* RTS3 */
1777 if (pins & ATMEL_UART_CTS)
1778 at91_set_B_periph(AT91_PIN_PA24, 0); /* CTS3 */
1779}
1780
1781static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1782
1783void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1784{
1785 struct platform_device *pdev;
1786 struct atmel_uart_data *pdata;
1787
1788 switch (id) {
1789 case 0: /* DBGU */
1790 pdev = &at91sam9g45_dbgu_device;
1791 configure_dbgu_pins();
1792 break;
1793 case AT91SAM9G45_ID_US0:
1794 pdev = &at91sam9g45_uart0_device;
1795 configure_usart0_pins(pins);
1796 break;
1797 case AT91SAM9G45_ID_US1:
1798 pdev = &at91sam9g45_uart1_device;
1799 configure_usart1_pins(pins);
1800 break;
1801 case AT91SAM9G45_ID_US2:
1802 pdev = &at91sam9g45_uart2_device;
1803 configure_usart2_pins(pins);
1804 break;
1805 case AT91SAM9G45_ID_US3:
1806 pdev = &at91sam9g45_uart3_device;
1807 configure_usart3_pins(pins);
1808 break;
1809 default:
1810 return;
1811 }
1812 pdata = pdev->dev.platform_data;
1813 pdata->num = portnr; /* update to mapped ID */
1814
1815 if (portnr < ATMEL_MAX_UART)
1816 at91_uarts[portnr] = pdev;
1817}
1818
1819void __init at91_add_device_serial(void)
1820{
1821 int i;
1822
1823 for (i = 0; i < ATMEL_MAX_UART; i++) {
1824 if (at91_uarts[i])
1825 platform_device_register(at91_uarts[i]);
1826 }
1827}
1828#else
1829void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1830void __init at91_add_device_serial(void) {}
1831#endif
1832
1833
1834/* -------------------------------------------------------------------- */
1835/*
1836 * These devices are always present and don't need any board-specific
1837 * setup.
1838 */
1839static int __init at91_add_standard_devices(void)
1840{
1841 if (of_have_populated_dt())
1842 return 0;
1843
1844 at91_add_device_hdmac();
1845 at91_add_device_rtc();
1846 at91_add_device_rtt();
1847 at91_add_device_trng();
1848 at91_add_device_watchdog();
1849 at91_add_device_tc();
1850 return 0;
1851}
1852
1853arch_initcall(at91_add_standard_devices);