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1/*
2 * Copyright (c) 2006 Ben Dooks
3 * Copyright 2006-2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10*/
11
12#include <linux/init.h>
13#include <linux/spinlock.h>
14#include <linux/workqueue.h>
15#include <linux/interrupt.h>
16#include <linux/delay.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/clk.h>
20#include <linux/platform_device.h>
21#include <linux/gpio.h>
22#include <linux/io.h>
23#include <linux/slab.h>
24
25#include <linux/spi/spi.h>
26#include <linux/spi/spi_bitbang.h>
27#include <linux/spi/s3c24xx.h>
28#include <linux/module.h>
29
30#include <plat/regs-spi.h>
31
32#include <plat/fiq.h>
33#include <asm/fiq.h>
34
35#include "spi-s3c24xx-fiq.h"
36
37/**
38 * s3c24xx_spi_devstate - per device data
39 * @hz: Last frequency calculated for @sppre field.
40 * @mode: Last mode setting for the @spcon field.
41 * @spcon: Value to write to the SPCON register.
42 * @sppre: Value to write to the SPPRE register.
43 */
44struct s3c24xx_spi_devstate {
45 unsigned int hz;
46 unsigned int mode;
47 u8 spcon;
48 u8 sppre;
49};
50
51enum spi_fiq_mode {
52 FIQ_MODE_NONE = 0,
53 FIQ_MODE_TX = 1,
54 FIQ_MODE_RX = 2,
55 FIQ_MODE_TXRX = 3,
56};
57
58struct s3c24xx_spi {
59 /* bitbang has to be first */
60 struct spi_bitbang bitbang;
61 struct completion done;
62
63 void __iomem *regs;
64 int irq;
65 int len;
66 int count;
67
68 struct fiq_handler fiq_handler;
69 enum spi_fiq_mode fiq_mode;
70 unsigned char fiq_inuse;
71 unsigned char fiq_claimed;
72
73 void (*set_cs)(struct s3c2410_spi_info *spi,
74 int cs, int pol);
75
76 /* data buffers */
77 const unsigned char *tx;
78 unsigned char *rx;
79
80 struct clk *clk;
81 struct resource *ioarea;
82 struct spi_master *master;
83 struct spi_device *curdev;
84 struct device *dev;
85 struct s3c2410_spi_info *pdata;
86};
87
88
89#define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
90#define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
91
92static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
93{
94 return spi_master_get_devdata(sdev->master);
95}
96
97static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
98{
99 gpio_set_value(spi->pin_cs, pol);
100}
101
102static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
103{
104 struct s3c24xx_spi_devstate *cs = spi->controller_state;
105 struct s3c24xx_spi *hw = to_hw(spi);
106 unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
107
108 /* change the chipselect state and the state of the spi engine clock */
109
110 switch (value) {
111 case BITBANG_CS_INACTIVE:
112 hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
113 writeb(cs->spcon, hw->regs + S3C2410_SPCON);
114 break;
115
116 case BITBANG_CS_ACTIVE:
117 writeb(cs->spcon | S3C2410_SPCON_ENSCK,
118 hw->regs + S3C2410_SPCON);
119 hw->set_cs(hw->pdata, spi->chip_select, cspol);
120 break;
121 }
122}
123
124static int s3c24xx_spi_update_state(struct spi_device *spi,
125 struct spi_transfer *t)
126{
127 struct s3c24xx_spi *hw = to_hw(spi);
128 struct s3c24xx_spi_devstate *cs = spi->controller_state;
129 unsigned int bpw;
130 unsigned int hz;
131 unsigned int div;
132 unsigned long clk;
133
134 bpw = t ? t->bits_per_word : spi->bits_per_word;
135 hz = t ? t->speed_hz : spi->max_speed_hz;
136
137 if (!bpw)
138 bpw = 8;
139
140 if (!hz)
141 hz = spi->max_speed_hz;
142
143 if (bpw != 8) {
144 dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
145 return -EINVAL;
146 }
147
148 if (spi->mode != cs->mode) {
149 u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK;
150
151 if (spi->mode & SPI_CPHA)
152 spcon |= S3C2410_SPCON_CPHA_FMTB;
153
154 if (spi->mode & SPI_CPOL)
155 spcon |= S3C2410_SPCON_CPOL_HIGH;
156
157 cs->mode = spi->mode;
158 cs->spcon = spcon;
159 }
160
161 if (cs->hz != hz) {
162 clk = clk_get_rate(hw->clk);
163 div = DIV_ROUND_UP(clk, hz * 2) - 1;
164
165 if (div > 255)
166 div = 255;
167
168 dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n",
169 div, hz, clk / (2 * (div + 1)));
170
171 cs->hz = hz;
172 cs->sppre = div;
173 }
174
175 return 0;
176}
177
178static int s3c24xx_spi_setupxfer(struct spi_device *spi,
179 struct spi_transfer *t)
180{
181 struct s3c24xx_spi_devstate *cs = spi->controller_state;
182 struct s3c24xx_spi *hw = to_hw(spi);
183 int ret;
184
185 ret = s3c24xx_spi_update_state(spi, t);
186 if (!ret)
187 writeb(cs->sppre, hw->regs + S3C2410_SPPRE);
188
189 return ret;
190}
191
192static int s3c24xx_spi_setup(struct spi_device *spi)
193{
194 struct s3c24xx_spi_devstate *cs = spi->controller_state;
195 struct s3c24xx_spi *hw = to_hw(spi);
196 int ret;
197
198 /* allocate settings on the first call */
199 if (!cs) {
200 cs = kzalloc(sizeof(struct s3c24xx_spi_devstate), GFP_KERNEL);
201 if (!cs) {
202 dev_err(&spi->dev, "no memory for controller state\n");
203 return -ENOMEM;
204 }
205
206 cs->spcon = SPCON_DEFAULT;
207 cs->hz = -1;
208 spi->controller_state = cs;
209 }
210
211 /* initialise the state from the device */
212 ret = s3c24xx_spi_update_state(spi, NULL);
213 if (ret)
214 return ret;
215
216 spin_lock(&hw->bitbang.lock);
217 if (!hw->bitbang.busy) {
218 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
219 /* need to ndelay for 0.5 clocktick ? */
220 }
221 spin_unlock(&hw->bitbang.lock);
222
223 return 0;
224}
225
226static void s3c24xx_spi_cleanup(struct spi_device *spi)
227{
228 kfree(spi->controller_state);
229}
230
231static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
232{
233 return hw->tx ? hw->tx[count] : 0;
234}
235
236#ifdef CONFIG_SPI_S3C24XX_FIQ
237/* Support for FIQ based pseudo-DMA to improve the transfer speed.
238 *
239 * This code uses the assembly helper in spi_s3c24xx_spi.S which is
240 * used by the FIQ core to move data between main memory and the peripheral
241 * block. Since this is code running on the processor, there is no problem
242 * with cache coherency of the buffers, so we can use any buffer we like.
243 */
244
245/**
246 * struct spi_fiq_code - FIQ code and header
247 * @length: The length of the code fragment, excluding this header.
248 * @ack_offset: The offset from @data to the word to place the IRQ ACK bit at.
249 * @data: The code itself to install as a FIQ handler.
250 */
251struct spi_fiq_code {
252 u32 length;
253 u32 ack_offset;
254 u8 data[0];
255};
256
257extern struct spi_fiq_code s3c24xx_spi_fiq_txrx;
258extern struct spi_fiq_code s3c24xx_spi_fiq_tx;
259extern struct spi_fiq_code s3c24xx_spi_fiq_rx;
260
261/**
262 * ack_bit - turn IRQ into IRQ acknowledgement bit
263 * @irq: The interrupt number
264 *
265 * Returns the bit to write to the interrupt acknowledge register.
266 */
267static inline u32 ack_bit(unsigned int irq)
268{
269 return 1 << (irq - IRQ_EINT0);
270}
271
272/**
273 * s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer
274 * @hw: The hardware state.
275 *
276 * Claim the FIQ handler (only one can be active at any one time) and
277 * then setup the correct transfer code for this transfer.
278 *
279 * This call updates all the necessary state information if successful,
280 * so the caller does not need to do anything more than start the transfer
281 * as normal, since the IRQ will have been re-routed to the FIQ handler.
282*/
283void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw)
284{
285 struct pt_regs regs;
286 enum spi_fiq_mode mode;
287 struct spi_fiq_code *code;
288 int ret;
289
290 if (!hw->fiq_claimed) {
291 /* try and claim fiq if we haven't got it, and if not
292 * then return and simply use another transfer method */
293
294 ret = claim_fiq(&hw->fiq_handler);
295 if (ret)
296 return;
297 }
298
299 if (hw->tx && !hw->rx)
300 mode = FIQ_MODE_TX;
301 else if (hw->rx && !hw->tx)
302 mode = FIQ_MODE_RX;
303 else
304 mode = FIQ_MODE_TXRX;
305
306 regs.uregs[fiq_rspi] = (long)hw->regs;
307 regs.uregs[fiq_rrx] = (long)hw->rx;
308 regs.uregs[fiq_rtx] = (long)hw->tx + 1;
309 regs.uregs[fiq_rcount] = hw->len - 1;
310 regs.uregs[fiq_rirq] = (long)S3C24XX_VA_IRQ;
311
312 set_fiq_regs(®s);
313
314 if (hw->fiq_mode != mode) {
315 u32 *ack_ptr;
316
317 hw->fiq_mode = mode;
318
319 switch (mode) {
320 case FIQ_MODE_TX:
321 code = &s3c24xx_spi_fiq_tx;
322 break;
323 case FIQ_MODE_RX:
324 code = &s3c24xx_spi_fiq_rx;
325 break;
326 case FIQ_MODE_TXRX:
327 code = &s3c24xx_spi_fiq_txrx;
328 break;
329 default:
330 code = NULL;
331 }
332
333 BUG_ON(!code);
334
335 ack_ptr = (u32 *)&code->data[code->ack_offset];
336 *ack_ptr = ack_bit(hw->irq);
337
338 set_fiq_handler(&code->data, code->length);
339 }
340
341 s3c24xx_set_fiq(hw->irq, true);
342
343 hw->fiq_mode = mode;
344 hw->fiq_inuse = 1;
345}
346
347/**
348 * s3c24xx_spi_fiqop - FIQ core code callback
349 * @pw: Data registered with the handler
350 * @release: Whether this is a release or a return.
351 *
352 * Called by the FIQ code when another module wants to use the FIQ, so
353 * return whether we are currently using this or not and then update our
354 * internal state.
355 */
356static int s3c24xx_spi_fiqop(void *pw, int release)
357{
358 struct s3c24xx_spi *hw = pw;
359 int ret = 0;
360
361 if (release) {
362 if (hw->fiq_inuse)
363 ret = -EBUSY;
364
365 /* note, we do not need to unroute the FIQ, as the FIQ
366 * vector code de-routes it to signal the end of transfer */
367
368 hw->fiq_mode = FIQ_MODE_NONE;
369 hw->fiq_claimed = 0;
370 } else {
371 hw->fiq_claimed = 1;
372 }
373
374 return ret;
375}
376
377/**
378 * s3c24xx_spi_initfiq - setup the information for the FIQ core
379 * @hw: The hardware state.
380 *
381 * Setup the fiq_handler block to pass to the FIQ core.
382 */
383static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw)
384{
385 hw->fiq_handler.dev_id = hw;
386 hw->fiq_handler.name = dev_name(hw->dev);
387 hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop;
388}
389
390/**
391 * s3c24xx_spi_usefiq - return if we should be using FIQ.
392 * @hw: The hardware state.
393 *
394 * Return true if the platform data specifies whether this channel is
395 * allowed to use the FIQ.
396 */
397static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw)
398{
399 return hw->pdata->use_fiq;
400}
401
402/**
403 * s3c24xx_spi_usingfiq - return if channel is using FIQ
404 * @spi: The hardware state.
405 *
406 * Return whether the channel is currently using the FIQ (separate from
407 * whether the FIQ is claimed).
408 */
409static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *spi)
410{
411 return spi->fiq_inuse;
412}
413#else
414
415static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *s) { }
416static inline void s3c24xx_spi_tryfiq(struct s3c24xx_spi *s) { }
417static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *s) { return false; }
418static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *s) { return false; }
419
420#endif /* CONFIG_SPI_S3C24XX_FIQ */
421
422static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
423{
424 struct s3c24xx_spi *hw = to_hw(spi);
425
426 hw->tx = t->tx_buf;
427 hw->rx = t->rx_buf;
428 hw->len = t->len;
429 hw->count = 0;
430
431 init_completion(&hw->done);
432
433 hw->fiq_inuse = 0;
434 if (s3c24xx_spi_usefiq(hw) && t->len >= 3)
435 s3c24xx_spi_tryfiq(hw);
436
437 /* send the first byte */
438 writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
439
440 wait_for_completion(&hw->done);
441 return hw->count;
442}
443
444static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
445{
446 struct s3c24xx_spi *hw = dev;
447 unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
448 unsigned int count = hw->count;
449
450 if (spsta & S3C2410_SPSTA_DCOL) {
451 dev_dbg(hw->dev, "data-collision\n");
452 complete(&hw->done);
453 goto irq_done;
454 }
455
456 if (!(spsta & S3C2410_SPSTA_READY)) {
457 dev_dbg(hw->dev, "spi not ready for tx?\n");
458 complete(&hw->done);
459 goto irq_done;
460 }
461
462 if (!s3c24xx_spi_usingfiq(hw)) {
463 hw->count++;
464
465 if (hw->rx)
466 hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
467
468 count++;
469
470 if (count < hw->len)
471 writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
472 else
473 complete(&hw->done);
474 } else {
475 hw->count = hw->len;
476 hw->fiq_inuse = 0;
477
478 if (hw->rx)
479 hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT);
480
481 complete(&hw->done);
482 }
483
484 irq_done:
485 return IRQ_HANDLED;
486}
487
488static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
489{
490 /* for the moment, permanently enable the clock */
491
492 clk_enable(hw->clk);
493
494 /* program defaults into the registers */
495
496 writeb(0xff, hw->regs + S3C2410_SPPRE);
497 writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
498 writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
499
500 if (hw->pdata) {
501 if (hw->set_cs == s3c24xx_spi_gpiocs)
502 gpio_direction_output(hw->pdata->pin_cs, 1);
503
504 if (hw->pdata->gpio_setup)
505 hw->pdata->gpio_setup(hw->pdata, 1);
506 }
507}
508
509static int __devinit s3c24xx_spi_probe(struct platform_device *pdev)
510{
511 struct s3c2410_spi_info *pdata;
512 struct s3c24xx_spi *hw;
513 struct spi_master *master;
514 struct resource *res;
515 int err = 0;
516
517 master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
518 if (master == NULL) {
519 dev_err(&pdev->dev, "No memory for spi_master\n");
520 err = -ENOMEM;
521 goto err_nomem;
522 }
523
524 hw = spi_master_get_devdata(master);
525 memset(hw, 0, sizeof(struct s3c24xx_spi));
526
527 hw->master = spi_master_get(master);
528 hw->pdata = pdata = pdev->dev.platform_data;
529 hw->dev = &pdev->dev;
530
531 if (pdata == NULL) {
532 dev_err(&pdev->dev, "No platform data supplied\n");
533 err = -ENOENT;
534 goto err_no_pdata;
535 }
536
537 platform_set_drvdata(pdev, hw);
538 init_completion(&hw->done);
539
540 /* initialise fiq handler */
541
542 s3c24xx_spi_initfiq(hw);
543
544 /* setup the master state. */
545
546 /* the spi->mode bits understood by this driver: */
547 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
548
549 master->num_chipselect = hw->pdata->num_cs;
550 master->bus_num = pdata->bus_num;
551
552 /* setup the state for the bitbang driver */
553
554 hw->bitbang.master = hw->master;
555 hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
556 hw->bitbang.chipselect = s3c24xx_spi_chipsel;
557 hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
558
559 hw->master->setup = s3c24xx_spi_setup;
560 hw->master->cleanup = s3c24xx_spi_cleanup;
561
562 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
563
564 /* find and map our resources */
565
566 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
567 if (res == NULL) {
568 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
569 err = -ENOENT;
570 goto err_no_iores;
571 }
572
573 hw->ioarea = request_mem_region(res->start, resource_size(res),
574 pdev->name);
575
576 if (hw->ioarea == NULL) {
577 dev_err(&pdev->dev, "Cannot reserve region\n");
578 err = -ENXIO;
579 goto err_no_iores;
580 }
581
582 hw->regs = ioremap(res->start, resource_size(res));
583 if (hw->regs == NULL) {
584 dev_err(&pdev->dev, "Cannot map IO\n");
585 err = -ENXIO;
586 goto err_no_iomap;
587 }
588
589 hw->irq = platform_get_irq(pdev, 0);
590 if (hw->irq < 0) {
591 dev_err(&pdev->dev, "No IRQ specified\n");
592 err = -ENOENT;
593 goto err_no_irq;
594 }
595
596 err = request_irq(hw->irq, s3c24xx_spi_irq, 0, pdev->name, hw);
597 if (err) {
598 dev_err(&pdev->dev, "Cannot claim IRQ\n");
599 goto err_no_irq;
600 }
601
602 hw->clk = clk_get(&pdev->dev, "spi");
603 if (IS_ERR(hw->clk)) {
604 dev_err(&pdev->dev, "No clock for device\n");
605 err = PTR_ERR(hw->clk);
606 goto err_no_clk;
607 }
608
609 /* setup any gpio we can */
610
611 if (!pdata->set_cs) {
612 if (pdata->pin_cs < 0) {
613 dev_err(&pdev->dev, "No chipselect pin\n");
614 goto err_register;
615 }
616
617 err = gpio_request(pdata->pin_cs, dev_name(&pdev->dev));
618 if (err) {
619 dev_err(&pdev->dev, "Failed to get gpio for cs\n");
620 goto err_register;
621 }
622
623 hw->set_cs = s3c24xx_spi_gpiocs;
624 gpio_direction_output(pdata->pin_cs, 1);
625 } else
626 hw->set_cs = pdata->set_cs;
627
628 s3c24xx_spi_initialsetup(hw);
629
630 /* register our spi controller */
631
632 err = spi_bitbang_start(&hw->bitbang);
633 if (err) {
634 dev_err(&pdev->dev, "Failed to register SPI master\n");
635 goto err_register;
636 }
637
638 return 0;
639
640 err_register:
641 if (hw->set_cs == s3c24xx_spi_gpiocs)
642 gpio_free(pdata->pin_cs);
643
644 clk_disable(hw->clk);
645 clk_put(hw->clk);
646
647 err_no_clk:
648 free_irq(hw->irq, hw);
649
650 err_no_irq:
651 iounmap(hw->regs);
652
653 err_no_iomap:
654 release_resource(hw->ioarea);
655 kfree(hw->ioarea);
656
657 err_no_iores:
658 err_no_pdata:
659 spi_master_put(hw->master);
660
661 err_nomem:
662 return err;
663}
664
665static int __devexit s3c24xx_spi_remove(struct platform_device *dev)
666{
667 struct s3c24xx_spi *hw = platform_get_drvdata(dev);
668
669 platform_set_drvdata(dev, NULL);
670
671 spi_bitbang_stop(&hw->bitbang);
672
673 clk_disable(hw->clk);
674 clk_put(hw->clk);
675
676 free_irq(hw->irq, hw);
677 iounmap(hw->regs);
678
679 if (hw->set_cs == s3c24xx_spi_gpiocs)
680 gpio_free(hw->pdata->pin_cs);
681
682 release_resource(hw->ioarea);
683 kfree(hw->ioarea);
684
685 spi_master_put(hw->master);
686 return 0;
687}
688
689
690#ifdef CONFIG_PM
691
692static int s3c24xx_spi_suspend(struct device *dev)
693{
694 struct s3c24xx_spi *hw = platform_get_drvdata(to_platform_device(dev));
695
696 if (hw->pdata && hw->pdata->gpio_setup)
697 hw->pdata->gpio_setup(hw->pdata, 0);
698
699 clk_disable(hw->clk);
700 return 0;
701}
702
703static int s3c24xx_spi_resume(struct device *dev)
704{
705 struct s3c24xx_spi *hw = platform_get_drvdata(to_platform_device(dev));
706
707 s3c24xx_spi_initialsetup(hw);
708 return 0;
709}
710
711static const struct dev_pm_ops s3c24xx_spi_pmops = {
712 .suspend = s3c24xx_spi_suspend,
713 .resume = s3c24xx_spi_resume,
714};
715
716#define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops
717#else
718#define S3C24XX_SPI_PMOPS NULL
719#endif /* CONFIG_PM */
720
721MODULE_ALIAS("platform:s3c2410-spi");
722static struct platform_driver s3c24xx_spi_driver = {
723 .probe = s3c24xx_spi_probe,
724 .remove = __devexit_p(s3c24xx_spi_remove),
725 .driver = {
726 .name = "s3c2410-spi",
727 .owner = THIS_MODULE,
728 .pm = S3C24XX_SPI_PMOPS,
729 },
730};
731module_platform_driver(s3c24xx_spi_driver);
732
733MODULE_DESCRIPTION("S3C24XX SPI Driver");
734MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
735MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2006 Ben Dooks
4 * Copyright 2006-2009 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6*/
7
8#include <linux/spinlock.h>
9#include <linux/interrupt.h>
10#include <linux/delay.h>
11#include <linux/errno.h>
12#include <linux/err.h>
13#include <linux/clk.h>
14#include <linux/platform_device.h>
15#include <linux/gpio.h>
16#include <linux/io.h>
17#include <linux/slab.h>
18
19#include <linux/spi/spi.h>
20#include <linux/spi/spi_bitbang.h>
21#include <linux/spi/s3c24xx.h>
22#include <linux/module.h>
23
24#include <plat/regs-spi.h>
25
26#include <asm/fiq.h>
27
28#include "spi-s3c24xx-fiq.h"
29
30/**
31 * s3c24xx_spi_devstate - per device data
32 * @hz: Last frequency calculated for @sppre field.
33 * @mode: Last mode setting for the @spcon field.
34 * @spcon: Value to write to the SPCON register.
35 * @sppre: Value to write to the SPPRE register.
36 */
37struct s3c24xx_spi_devstate {
38 unsigned int hz;
39 unsigned int mode;
40 u8 spcon;
41 u8 sppre;
42};
43
44enum spi_fiq_mode {
45 FIQ_MODE_NONE = 0,
46 FIQ_MODE_TX = 1,
47 FIQ_MODE_RX = 2,
48 FIQ_MODE_TXRX = 3,
49};
50
51struct s3c24xx_spi {
52 /* bitbang has to be first */
53 struct spi_bitbang bitbang;
54 struct completion done;
55
56 void __iomem *regs;
57 int irq;
58 int len;
59 int count;
60
61 struct fiq_handler fiq_handler;
62 enum spi_fiq_mode fiq_mode;
63 unsigned char fiq_inuse;
64 unsigned char fiq_claimed;
65
66 void (*set_cs)(struct s3c2410_spi_info *spi,
67 int cs, int pol);
68
69 /* data buffers */
70 const unsigned char *tx;
71 unsigned char *rx;
72
73 struct clk *clk;
74 struct spi_master *master;
75 struct spi_device *curdev;
76 struct device *dev;
77 struct s3c2410_spi_info *pdata;
78};
79
80#define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
81#define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
82
83static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
84{
85 return spi_master_get_devdata(sdev->master);
86}
87
88static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
89{
90 gpio_set_value(spi->pin_cs, pol);
91}
92
93static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
94{
95 struct s3c24xx_spi_devstate *cs = spi->controller_state;
96 struct s3c24xx_spi *hw = to_hw(spi);
97 unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
98
99 /* change the chipselect state and the state of the spi engine clock */
100
101 switch (value) {
102 case BITBANG_CS_INACTIVE:
103 hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
104 writeb(cs->spcon, hw->regs + S3C2410_SPCON);
105 break;
106
107 case BITBANG_CS_ACTIVE:
108 writeb(cs->spcon | S3C2410_SPCON_ENSCK,
109 hw->regs + S3C2410_SPCON);
110 hw->set_cs(hw->pdata, spi->chip_select, cspol);
111 break;
112 }
113}
114
115static int s3c24xx_spi_update_state(struct spi_device *spi,
116 struct spi_transfer *t)
117{
118 struct s3c24xx_spi *hw = to_hw(spi);
119 struct s3c24xx_spi_devstate *cs = spi->controller_state;
120 unsigned int hz;
121 unsigned int div;
122 unsigned long clk;
123
124 hz = t ? t->speed_hz : spi->max_speed_hz;
125
126 if (!hz)
127 hz = spi->max_speed_hz;
128
129 if (spi->mode != cs->mode) {
130 u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK;
131
132 if (spi->mode & SPI_CPHA)
133 spcon |= S3C2410_SPCON_CPHA_FMTB;
134
135 if (spi->mode & SPI_CPOL)
136 spcon |= S3C2410_SPCON_CPOL_HIGH;
137
138 cs->mode = spi->mode;
139 cs->spcon = spcon;
140 }
141
142 if (cs->hz != hz) {
143 clk = clk_get_rate(hw->clk);
144 div = DIV_ROUND_UP(clk, hz * 2) - 1;
145
146 if (div > 255)
147 div = 255;
148
149 dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n",
150 div, hz, clk / (2 * (div + 1)));
151
152 cs->hz = hz;
153 cs->sppre = div;
154 }
155
156 return 0;
157}
158
159static int s3c24xx_spi_setupxfer(struct spi_device *spi,
160 struct spi_transfer *t)
161{
162 struct s3c24xx_spi_devstate *cs = spi->controller_state;
163 struct s3c24xx_spi *hw = to_hw(spi);
164 int ret;
165
166 ret = s3c24xx_spi_update_state(spi, t);
167 if (!ret)
168 writeb(cs->sppre, hw->regs + S3C2410_SPPRE);
169
170 return ret;
171}
172
173static int s3c24xx_spi_setup(struct spi_device *spi)
174{
175 struct s3c24xx_spi_devstate *cs = spi->controller_state;
176 struct s3c24xx_spi *hw = to_hw(spi);
177 int ret;
178
179 /* allocate settings on the first call */
180 if (!cs) {
181 cs = devm_kzalloc(&spi->dev,
182 sizeof(struct s3c24xx_spi_devstate),
183 GFP_KERNEL);
184 if (!cs)
185 return -ENOMEM;
186
187 cs->spcon = SPCON_DEFAULT;
188 cs->hz = -1;
189 spi->controller_state = cs;
190 }
191
192 /* initialise the state from the device */
193 ret = s3c24xx_spi_update_state(spi, NULL);
194 if (ret)
195 return ret;
196
197 mutex_lock(&hw->bitbang.lock);
198 if (!hw->bitbang.busy) {
199 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
200 /* need to ndelay for 0.5 clocktick ? */
201 }
202 mutex_unlock(&hw->bitbang.lock);
203
204 return 0;
205}
206
207static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
208{
209 return hw->tx ? hw->tx[count] : 0;
210}
211
212#ifdef CONFIG_SPI_S3C24XX_FIQ
213/* Support for FIQ based pseudo-DMA to improve the transfer speed.
214 *
215 * This code uses the assembly helper in spi_s3c24xx_spi.S which is
216 * used by the FIQ core to move data between main memory and the peripheral
217 * block. Since this is code running on the processor, there is no problem
218 * with cache coherency of the buffers, so we can use any buffer we like.
219 */
220
221/**
222 * struct spi_fiq_code - FIQ code and header
223 * @length: The length of the code fragment, excluding this header.
224 * @ack_offset: The offset from @data to the word to place the IRQ ACK bit at.
225 * @data: The code itself to install as a FIQ handler.
226 */
227struct spi_fiq_code {
228 u32 length;
229 u32 ack_offset;
230 u8 data[0];
231};
232
233extern struct spi_fiq_code s3c24xx_spi_fiq_txrx;
234extern struct spi_fiq_code s3c24xx_spi_fiq_tx;
235extern struct spi_fiq_code s3c24xx_spi_fiq_rx;
236
237/**
238 * ack_bit - turn IRQ into IRQ acknowledgement bit
239 * @irq: The interrupt number
240 *
241 * Returns the bit to write to the interrupt acknowledge register.
242 */
243static inline u32 ack_bit(unsigned int irq)
244{
245 return 1 << (irq - IRQ_EINT0);
246}
247
248/**
249 * s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer
250 * @hw: The hardware state.
251 *
252 * Claim the FIQ handler (only one can be active at any one time) and
253 * then setup the correct transfer code for this transfer.
254 *
255 * This call updates all the necessary state information if successful,
256 * so the caller does not need to do anything more than start the transfer
257 * as normal, since the IRQ will have been re-routed to the FIQ handler.
258*/
259static void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw)
260{
261 struct pt_regs regs;
262 enum spi_fiq_mode mode;
263 struct spi_fiq_code *code;
264 int ret;
265
266 if (!hw->fiq_claimed) {
267 /* try and claim fiq if we haven't got it, and if not
268 * then return and simply use another transfer method */
269
270 ret = claim_fiq(&hw->fiq_handler);
271 if (ret)
272 return;
273 }
274
275 if (hw->tx && !hw->rx)
276 mode = FIQ_MODE_TX;
277 else if (hw->rx && !hw->tx)
278 mode = FIQ_MODE_RX;
279 else
280 mode = FIQ_MODE_TXRX;
281
282 regs.uregs[fiq_rspi] = (long)hw->regs;
283 regs.uregs[fiq_rrx] = (long)hw->rx;
284 regs.uregs[fiq_rtx] = (long)hw->tx + 1;
285 regs.uregs[fiq_rcount] = hw->len - 1;
286 regs.uregs[fiq_rirq] = (long)S3C24XX_VA_IRQ;
287
288 set_fiq_regs(®s);
289
290 if (hw->fiq_mode != mode) {
291 u32 *ack_ptr;
292
293 hw->fiq_mode = mode;
294
295 switch (mode) {
296 case FIQ_MODE_TX:
297 code = &s3c24xx_spi_fiq_tx;
298 break;
299 case FIQ_MODE_RX:
300 code = &s3c24xx_spi_fiq_rx;
301 break;
302 case FIQ_MODE_TXRX:
303 code = &s3c24xx_spi_fiq_txrx;
304 break;
305 default:
306 code = NULL;
307 }
308
309 BUG_ON(!code);
310
311 ack_ptr = (u32 *)&code->data[code->ack_offset];
312 *ack_ptr = ack_bit(hw->irq);
313
314 set_fiq_handler(&code->data, code->length);
315 }
316
317 s3c24xx_set_fiq(hw->irq, true);
318
319 hw->fiq_mode = mode;
320 hw->fiq_inuse = 1;
321}
322
323/**
324 * s3c24xx_spi_fiqop - FIQ core code callback
325 * @pw: Data registered with the handler
326 * @release: Whether this is a release or a return.
327 *
328 * Called by the FIQ code when another module wants to use the FIQ, so
329 * return whether we are currently using this or not and then update our
330 * internal state.
331 */
332static int s3c24xx_spi_fiqop(void *pw, int release)
333{
334 struct s3c24xx_spi *hw = pw;
335 int ret = 0;
336
337 if (release) {
338 if (hw->fiq_inuse)
339 ret = -EBUSY;
340
341 /* note, we do not need to unroute the FIQ, as the FIQ
342 * vector code de-routes it to signal the end of transfer */
343
344 hw->fiq_mode = FIQ_MODE_NONE;
345 hw->fiq_claimed = 0;
346 } else {
347 hw->fiq_claimed = 1;
348 }
349
350 return ret;
351}
352
353/**
354 * s3c24xx_spi_initfiq - setup the information for the FIQ core
355 * @hw: The hardware state.
356 *
357 * Setup the fiq_handler block to pass to the FIQ core.
358 */
359static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw)
360{
361 hw->fiq_handler.dev_id = hw;
362 hw->fiq_handler.name = dev_name(hw->dev);
363 hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop;
364}
365
366/**
367 * s3c24xx_spi_usefiq - return if we should be using FIQ.
368 * @hw: The hardware state.
369 *
370 * Return true if the platform data specifies whether this channel is
371 * allowed to use the FIQ.
372 */
373static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw)
374{
375 return hw->pdata->use_fiq;
376}
377
378/**
379 * s3c24xx_spi_usingfiq - return if channel is using FIQ
380 * @spi: The hardware state.
381 *
382 * Return whether the channel is currently using the FIQ (separate from
383 * whether the FIQ is claimed).
384 */
385static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *spi)
386{
387 return spi->fiq_inuse;
388}
389#else
390
391static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *s) { }
392static inline void s3c24xx_spi_tryfiq(struct s3c24xx_spi *s) { }
393static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *s) { return false; }
394static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *s) { return false; }
395
396#endif /* CONFIG_SPI_S3C24XX_FIQ */
397
398static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
399{
400 struct s3c24xx_spi *hw = to_hw(spi);
401
402 hw->tx = t->tx_buf;
403 hw->rx = t->rx_buf;
404 hw->len = t->len;
405 hw->count = 0;
406
407 init_completion(&hw->done);
408
409 hw->fiq_inuse = 0;
410 if (s3c24xx_spi_usefiq(hw) && t->len >= 3)
411 s3c24xx_spi_tryfiq(hw);
412
413 /* send the first byte */
414 writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
415
416 wait_for_completion(&hw->done);
417 return hw->count;
418}
419
420static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
421{
422 struct s3c24xx_spi *hw = dev;
423 unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
424 unsigned int count = hw->count;
425
426 if (spsta & S3C2410_SPSTA_DCOL) {
427 dev_dbg(hw->dev, "data-collision\n");
428 complete(&hw->done);
429 goto irq_done;
430 }
431
432 if (!(spsta & S3C2410_SPSTA_READY)) {
433 dev_dbg(hw->dev, "spi not ready for tx?\n");
434 complete(&hw->done);
435 goto irq_done;
436 }
437
438 if (!s3c24xx_spi_usingfiq(hw)) {
439 hw->count++;
440
441 if (hw->rx)
442 hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
443
444 count++;
445
446 if (count < hw->len)
447 writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
448 else
449 complete(&hw->done);
450 } else {
451 hw->count = hw->len;
452 hw->fiq_inuse = 0;
453
454 if (hw->rx)
455 hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT);
456
457 complete(&hw->done);
458 }
459
460 irq_done:
461 return IRQ_HANDLED;
462}
463
464static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
465{
466 /* for the moment, permanently enable the clock */
467
468 clk_enable(hw->clk);
469
470 /* program defaults into the registers */
471
472 writeb(0xff, hw->regs + S3C2410_SPPRE);
473 writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
474 writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
475
476 if (hw->pdata) {
477 if (hw->set_cs == s3c24xx_spi_gpiocs)
478 gpio_direction_output(hw->pdata->pin_cs, 1);
479
480 if (hw->pdata->gpio_setup)
481 hw->pdata->gpio_setup(hw->pdata, 1);
482 }
483}
484
485static int s3c24xx_spi_probe(struct platform_device *pdev)
486{
487 struct s3c2410_spi_info *pdata;
488 struct s3c24xx_spi *hw;
489 struct spi_master *master;
490 int err = 0;
491
492 master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
493 if (master == NULL) {
494 dev_err(&pdev->dev, "No memory for spi_master\n");
495 return -ENOMEM;
496 }
497
498 hw = spi_master_get_devdata(master);
499
500 hw->master = master;
501 hw->pdata = pdata = dev_get_platdata(&pdev->dev);
502 hw->dev = &pdev->dev;
503
504 if (pdata == NULL) {
505 dev_err(&pdev->dev, "No platform data supplied\n");
506 err = -ENOENT;
507 goto err_no_pdata;
508 }
509
510 platform_set_drvdata(pdev, hw);
511 init_completion(&hw->done);
512
513 /* initialise fiq handler */
514
515 s3c24xx_spi_initfiq(hw);
516
517 /* setup the master state. */
518
519 /* the spi->mode bits understood by this driver: */
520 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
521
522 master->num_chipselect = hw->pdata->num_cs;
523 master->bus_num = pdata->bus_num;
524 master->bits_per_word_mask = SPI_BPW_MASK(8);
525
526 /* setup the state for the bitbang driver */
527
528 hw->bitbang.master = hw->master;
529 hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
530 hw->bitbang.chipselect = s3c24xx_spi_chipsel;
531 hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
532
533 hw->master->setup = s3c24xx_spi_setup;
534
535 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
536
537 /* find and map our resources */
538 hw->regs = devm_platform_ioremap_resource(pdev, 0);
539 if (IS_ERR(hw->regs)) {
540 err = PTR_ERR(hw->regs);
541 goto err_no_pdata;
542 }
543
544 hw->irq = platform_get_irq(pdev, 0);
545 if (hw->irq < 0) {
546 err = -ENOENT;
547 goto err_no_pdata;
548 }
549
550 err = devm_request_irq(&pdev->dev, hw->irq, s3c24xx_spi_irq, 0,
551 pdev->name, hw);
552 if (err) {
553 dev_err(&pdev->dev, "Cannot claim IRQ\n");
554 goto err_no_pdata;
555 }
556
557 hw->clk = devm_clk_get(&pdev->dev, "spi");
558 if (IS_ERR(hw->clk)) {
559 dev_err(&pdev->dev, "No clock for device\n");
560 err = PTR_ERR(hw->clk);
561 goto err_no_pdata;
562 }
563
564 /* setup any gpio we can */
565
566 if (!pdata->set_cs) {
567 if (pdata->pin_cs < 0) {
568 dev_err(&pdev->dev, "No chipselect pin\n");
569 err = -EINVAL;
570 goto err_register;
571 }
572
573 err = devm_gpio_request(&pdev->dev, pdata->pin_cs,
574 dev_name(&pdev->dev));
575 if (err) {
576 dev_err(&pdev->dev, "Failed to get gpio for cs\n");
577 goto err_register;
578 }
579
580 hw->set_cs = s3c24xx_spi_gpiocs;
581 gpio_direction_output(pdata->pin_cs, 1);
582 } else
583 hw->set_cs = pdata->set_cs;
584
585 s3c24xx_spi_initialsetup(hw);
586
587 /* register our spi controller */
588
589 err = spi_bitbang_start(&hw->bitbang);
590 if (err) {
591 dev_err(&pdev->dev, "Failed to register SPI master\n");
592 goto err_register;
593 }
594
595 return 0;
596
597 err_register:
598 clk_disable(hw->clk);
599
600 err_no_pdata:
601 spi_master_put(hw->master);
602 return err;
603}
604
605static int s3c24xx_spi_remove(struct platform_device *dev)
606{
607 struct s3c24xx_spi *hw = platform_get_drvdata(dev);
608
609 spi_bitbang_stop(&hw->bitbang);
610 clk_disable(hw->clk);
611 spi_master_put(hw->master);
612 return 0;
613}
614
615
616#ifdef CONFIG_PM
617
618static int s3c24xx_spi_suspend(struct device *dev)
619{
620 struct s3c24xx_spi *hw = dev_get_drvdata(dev);
621 int ret;
622
623 ret = spi_master_suspend(hw->master);
624 if (ret)
625 return ret;
626
627 if (hw->pdata && hw->pdata->gpio_setup)
628 hw->pdata->gpio_setup(hw->pdata, 0);
629
630 clk_disable(hw->clk);
631 return 0;
632}
633
634static int s3c24xx_spi_resume(struct device *dev)
635{
636 struct s3c24xx_spi *hw = dev_get_drvdata(dev);
637
638 s3c24xx_spi_initialsetup(hw);
639 return spi_master_resume(hw->master);
640}
641
642static const struct dev_pm_ops s3c24xx_spi_pmops = {
643 .suspend = s3c24xx_spi_suspend,
644 .resume = s3c24xx_spi_resume,
645};
646
647#define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops
648#else
649#define S3C24XX_SPI_PMOPS NULL
650#endif /* CONFIG_PM */
651
652MODULE_ALIAS("platform:s3c2410-spi");
653static struct platform_driver s3c24xx_spi_driver = {
654 .probe = s3c24xx_spi_probe,
655 .remove = s3c24xx_spi_remove,
656 .driver = {
657 .name = "s3c2410-spi",
658 .pm = S3C24XX_SPI_PMOPS,
659 },
660};
661module_platform_driver(s3c24xx_spi_driver);
662
663MODULE_DESCRIPTION("S3C24XX SPI Driver");
664MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
665MODULE_LICENSE("GPL");