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1/*
2 * Special handling for DW core on Intel MID platform
3 *
4 * Copyright (c) 2009, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 */
19
20#include <linux/dma-mapping.h>
21#include <linux/dmaengine.h>
22#include <linux/interrupt.h>
23#include <linux/slab.h>
24#include <linux/spi/spi.h>
25#include <linux/types.h>
26
27#include "spi-dw.h"
28
29#ifdef CONFIG_SPI_DW_MID_DMA
30#include <linux/intel_mid_dma.h>
31#include <linux/pci.h>
32
33struct mid_dma {
34 struct intel_mid_dma_slave dmas_tx;
35 struct intel_mid_dma_slave dmas_rx;
36};
37
38static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
39{
40 struct dw_spi *dws = param;
41
42 return dws->dmac && (&dws->dmac->dev == chan->device->dev);
43}
44
45static int mid_spi_dma_init(struct dw_spi *dws)
46{
47 struct mid_dma *dw_dma = dws->dma_priv;
48 struct intel_mid_dma_slave *rxs, *txs;
49 dma_cap_mask_t mask;
50
51 /*
52 * Get pci device for DMA controller, currently it could only
53 * be the DMA controller of either Moorestown or Medfield
54 */
55 dws->dmac = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0813, NULL);
56 if (!dws->dmac)
57 dws->dmac = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
58
59 dma_cap_zero(mask);
60 dma_cap_set(DMA_SLAVE, mask);
61
62 /* 1. Init rx channel */
63 dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
64 if (!dws->rxchan)
65 goto err_exit;
66 rxs = &dw_dma->dmas_rx;
67 rxs->hs_mode = LNW_DMA_HW_HS;
68 rxs->cfg_mode = LNW_DMA_PER_TO_MEM;
69 dws->rxchan->private = rxs;
70
71 /* 2. Init tx channel */
72 dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
73 if (!dws->txchan)
74 goto free_rxchan;
75 txs = &dw_dma->dmas_tx;
76 txs->hs_mode = LNW_DMA_HW_HS;
77 txs->cfg_mode = LNW_DMA_MEM_TO_PER;
78 dws->txchan->private = txs;
79
80 dws->dma_inited = 1;
81 return 0;
82
83free_rxchan:
84 dma_release_channel(dws->rxchan);
85err_exit:
86 return -1;
87
88}
89
90static void mid_spi_dma_exit(struct dw_spi *dws)
91{
92 dma_release_channel(dws->txchan);
93 dma_release_channel(dws->rxchan);
94}
95
96/*
97 * dws->dma_chan_done is cleared before the dma transfer starts,
98 * callback for rx/tx channel will each increment it by 1.
99 * Reaching 2 means the whole spi transaction is done.
100 */
101static void dw_spi_dma_done(void *arg)
102{
103 struct dw_spi *dws = arg;
104
105 if (++dws->dma_chan_done != 2)
106 return;
107 dw_spi_xfer_done(dws);
108}
109
110static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
111{
112 struct dma_async_tx_descriptor *txdesc = NULL, *rxdesc = NULL;
113 struct dma_chan *txchan, *rxchan;
114 struct dma_slave_config txconf, rxconf;
115 u16 dma_ctrl = 0;
116
117 /* 1. setup DMA related registers */
118 if (cs_change) {
119 spi_enable_chip(dws, 0);
120 dw_writew(dws, DW_SPI_DMARDLR, 0xf);
121 dw_writew(dws, DW_SPI_DMATDLR, 0x10);
122 if (dws->tx_dma)
123 dma_ctrl |= 0x2;
124 if (dws->rx_dma)
125 dma_ctrl |= 0x1;
126 dw_writew(dws, DW_SPI_DMACR, dma_ctrl);
127 spi_enable_chip(dws, 1);
128 }
129
130 dws->dma_chan_done = 0;
131 txchan = dws->txchan;
132 rxchan = dws->rxchan;
133
134 /* 2. Prepare the TX dma transfer */
135 txconf.direction = DMA_MEM_TO_DEV;
136 txconf.dst_addr = dws->dma_addr;
137 txconf.dst_maxburst = LNW_DMA_MSIZE_16;
138 txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
139 txconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
140 txconf.device_fc = false;
141
142 txchan->device->device_control(txchan, DMA_SLAVE_CONFIG,
143 (unsigned long) &txconf);
144
145 memset(&dws->tx_sgl, 0, sizeof(dws->tx_sgl));
146 dws->tx_sgl.dma_address = dws->tx_dma;
147 dws->tx_sgl.length = dws->len;
148
149 txdesc = dmaengine_prep_slave_sg(txchan,
150 &dws->tx_sgl,
151 1,
152 DMA_MEM_TO_DEV,
153 DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_DEST_UNMAP);
154 txdesc->callback = dw_spi_dma_done;
155 txdesc->callback_param = dws;
156
157 /* 3. Prepare the RX dma transfer */
158 rxconf.direction = DMA_DEV_TO_MEM;
159 rxconf.src_addr = dws->dma_addr;
160 rxconf.src_maxburst = LNW_DMA_MSIZE_16;
161 rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
162 rxconf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
163 rxconf.device_fc = false;
164
165 rxchan->device->device_control(rxchan, DMA_SLAVE_CONFIG,
166 (unsigned long) &rxconf);
167
168 memset(&dws->rx_sgl, 0, sizeof(dws->rx_sgl));
169 dws->rx_sgl.dma_address = dws->rx_dma;
170 dws->rx_sgl.length = dws->len;
171
172 rxdesc = dmaengine_prep_slave_sg(rxchan,
173 &dws->rx_sgl,
174 1,
175 DMA_DEV_TO_MEM,
176 DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_DEST_UNMAP);
177 rxdesc->callback = dw_spi_dma_done;
178 rxdesc->callback_param = dws;
179
180 /* rx must be started before tx due to spi instinct */
181 rxdesc->tx_submit(rxdesc);
182 txdesc->tx_submit(txdesc);
183 return 0;
184}
185
186static struct dw_spi_dma_ops mid_dma_ops = {
187 .dma_init = mid_spi_dma_init,
188 .dma_exit = mid_spi_dma_exit,
189 .dma_transfer = mid_spi_dma_transfer,
190};
191#endif
192
193/* Some specific info for SPI0 controller on Moorestown */
194
195/* HW info for MRST CLk Control Unit, one 32b reg */
196#define MRST_SPI_CLK_BASE 100000000 /* 100m */
197#define MRST_CLK_SPI0_REG 0xff11d86c
198#define CLK_SPI_BDIV_OFFSET 0
199#define CLK_SPI_BDIV_MASK 0x00000007
200#define CLK_SPI_CDIV_OFFSET 9
201#define CLK_SPI_CDIV_MASK 0x00000e00
202#define CLK_SPI_DISABLE_OFFSET 8
203
204int dw_spi_mid_init(struct dw_spi *dws)
205{
206 void __iomem *clk_reg;
207 u32 clk_cdiv;
208
209 clk_reg = ioremap_nocache(MRST_CLK_SPI0_REG, 16);
210 if (!clk_reg)
211 return -ENOMEM;
212
213 /* get SPI controller operating freq info */
214 clk_cdiv = (readl(clk_reg) & CLK_SPI_CDIV_MASK) >> CLK_SPI_CDIV_OFFSET;
215 dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
216 iounmap(clk_reg);
217
218 dws->num_cs = 16;
219 dws->fifo_len = 40; /* FIFO has 40 words buffer */
220
221#ifdef CONFIG_SPI_DW_MID_DMA
222 dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);
223 if (!dws->dma_priv)
224 return -ENOMEM;
225 dws->dma_ops = &mid_dma_ops;
226#endif
227 return 0;
228}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Special handling for DW core on Intel MID platform
4 *
5 * Copyright (c) 2009, 2014 Intel Corporation.
6 */
7
8#include <linux/dma-mapping.h>
9#include <linux/dmaengine.h>
10#include <linux/interrupt.h>
11#include <linux/slab.h>
12#include <linux/spi/spi.h>
13#include <linux/types.h>
14
15#include "spi-dw.h"
16
17#ifdef CONFIG_SPI_DW_MID_DMA
18#include <linux/pci.h>
19#include <linux/platform_data/dma-dw.h>
20
21#define RX_BUSY 0
22#define TX_BUSY 1
23
24static struct dw_dma_slave mid_dma_tx = { .dst_id = 1 };
25static struct dw_dma_slave mid_dma_rx = { .src_id = 0 };
26
27static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
28{
29 struct dw_dma_slave *s = param;
30
31 if (s->dma_dev != chan->device->dev)
32 return false;
33
34 chan->private = s;
35 return true;
36}
37
38static int mid_spi_dma_init(struct dw_spi *dws)
39{
40 struct pci_dev *dma_dev;
41 struct dw_dma_slave *tx = dws->dma_tx;
42 struct dw_dma_slave *rx = dws->dma_rx;
43 dma_cap_mask_t mask;
44
45 /*
46 * Get pci device for DMA controller, currently it could only
47 * be the DMA controller of Medfield
48 */
49 dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
50 if (!dma_dev)
51 return -ENODEV;
52
53 dma_cap_zero(mask);
54 dma_cap_set(DMA_SLAVE, mask);
55
56 /* 1. Init rx channel */
57 rx->dma_dev = &dma_dev->dev;
58 dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, rx);
59 if (!dws->rxchan)
60 goto err_exit;
61 dws->master->dma_rx = dws->rxchan;
62
63 /* 2. Init tx channel */
64 tx->dma_dev = &dma_dev->dev;
65 dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, tx);
66 if (!dws->txchan)
67 goto free_rxchan;
68 dws->master->dma_tx = dws->txchan;
69
70 dws->dma_inited = 1;
71 return 0;
72
73free_rxchan:
74 dma_release_channel(dws->rxchan);
75err_exit:
76 return -EBUSY;
77}
78
79static void mid_spi_dma_exit(struct dw_spi *dws)
80{
81 if (!dws->dma_inited)
82 return;
83
84 dmaengine_terminate_sync(dws->txchan);
85 dma_release_channel(dws->txchan);
86
87 dmaengine_terminate_sync(dws->rxchan);
88 dma_release_channel(dws->rxchan);
89}
90
91static irqreturn_t dma_transfer(struct dw_spi *dws)
92{
93 u16 irq_status = dw_readl(dws, DW_SPI_ISR);
94
95 if (!irq_status)
96 return IRQ_NONE;
97
98 dw_readl(dws, DW_SPI_ICR);
99 spi_reset_chip(dws);
100
101 dev_err(&dws->master->dev, "%s: FIFO overrun/underrun\n", __func__);
102 dws->master->cur_msg->status = -EIO;
103 spi_finalize_current_transfer(dws->master);
104 return IRQ_HANDLED;
105}
106
107static bool mid_spi_can_dma(struct spi_controller *master,
108 struct spi_device *spi, struct spi_transfer *xfer)
109{
110 struct dw_spi *dws = spi_controller_get_devdata(master);
111
112 if (!dws->dma_inited)
113 return false;
114
115 return xfer->len > dws->fifo_len;
116}
117
118static enum dma_slave_buswidth convert_dma_width(u32 dma_width) {
119 if (dma_width == 1)
120 return DMA_SLAVE_BUSWIDTH_1_BYTE;
121 else if (dma_width == 2)
122 return DMA_SLAVE_BUSWIDTH_2_BYTES;
123
124 return DMA_SLAVE_BUSWIDTH_UNDEFINED;
125}
126
127/*
128 * dws->dma_chan_busy is set before the dma transfer starts, callback for tx
129 * channel will clear a corresponding bit.
130 */
131static void dw_spi_dma_tx_done(void *arg)
132{
133 struct dw_spi *dws = arg;
134
135 clear_bit(TX_BUSY, &dws->dma_chan_busy);
136 if (test_bit(RX_BUSY, &dws->dma_chan_busy))
137 return;
138 spi_finalize_current_transfer(dws->master);
139}
140
141static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws,
142 struct spi_transfer *xfer)
143{
144 struct dma_slave_config txconf;
145 struct dma_async_tx_descriptor *txdesc;
146
147 if (!xfer->tx_buf)
148 return NULL;
149
150 txconf.direction = DMA_MEM_TO_DEV;
151 txconf.dst_addr = dws->dma_addr;
152 txconf.dst_maxburst = 16;
153 txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
154 txconf.dst_addr_width = convert_dma_width(dws->dma_width);
155 txconf.device_fc = false;
156
157 dmaengine_slave_config(dws->txchan, &txconf);
158
159 txdesc = dmaengine_prep_slave_sg(dws->txchan,
160 xfer->tx_sg.sgl,
161 xfer->tx_sg.nents,
162 DMA_MEM_TO_DEV,
163 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
164 if (!txdesc)
165 return NULL;
166
167 txdesc->callback = dw_spi_dma_tx_done;
168 txdesc->callback_param = dws;
169
170 return txdesc;
171}
172
173/*
174 * dws->dma_chan_busy is set before the dma transfer starts, callback for rx
175 * channel will clear a corresponding bit.
176 */
177static void dw_spi_dma_rx_done(void *arg)
178{
179 struct dw_spi *dws = arg;
180
181 clear_bit(RX_BUSY, &dws->dma_chan_busy);
182 if (test_bit(TX_BUSY, &dws->dma_chan_busy))
183 return;
184 spi_finalize_current_transfer(dws->master);
185}
186
187static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws,
188 struct spi_transfer *xfer)
189{
190 struct dma_slave_config rxconf;
191 struct dma_async_tx_descriptor *rxdesc;
192
193 if (!xfer->rx_buf)
194 return NULL;
195
196 rxconf.direction = DMA_DEV_TO_MEM;
197 rxconf.src_addr = dws->dma_addr;
198 rxconf.src_maxburst = 16;
199 rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
200 rxconf.src_addr_width = convert_dma_width(dws->dma_width);
201 rxconf.device_fc = false;
202
203 dmaengine_slave_config(dws->rxchan, &rxconf);
204
205 rxdesc = dmaengine_prep_slave_sg(dws->rxchan,
206 xfer->rx_sg.sgl,
207 xfer->rx_sg.nents,
208 DMA_DEV_TO_MEM,
209 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
210 if (!rxdesc)
211 return NULL;
212
213 rxdesc->callback = dw_spi_dma_rx_done;
214 rxdesc->callback_param = dws;
215
216 return rxdesc;
217}
218
219static int mid_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
220{
221 u16 dma_ctrl = 0;
222
223 dw_writel(dws, DW_SPI_DMARDLR, 0xf);
224 dw_writel(dws, DW_SPI_DMATDLR, 0x10);
225
226 if (xfer->tx_buf)
227 dma_ctrl |= SPI_DMA_TDMAE;
228 if (xfer->rx_buf)
229 dma_ctrl |= SPI_DMA_RDMAE;
230 dw_writel(dws, DW_SPI_DMACR, dma_ctrl);
231
232 /* Set the interrupt mask */
233 spi_umask_intr(dws, SPI_INT_TXOI | SPI_INT_RXUI | SPI_INT_RXOI);
234
235 dws->transfer_handler = dma_transfer;
236
237 return 0;
238}
239
240static int mid_spi_dma_transfer(struct dw_spi *dws, struct spi_transfer *xfer)
241{
242 struct dma_async_tx_descriptor *txdesc, *rxdesc;
243
244 /* Prepare the TX dma transfer */
245 txdesc = dw_spi_dma_prepare_tx(dws, xfer);
246
247 /* Prepare the RX dma transfer */
248 rxdesc = dw_spi_dma_prepare_rx(dws, xfer);
249
250 /* rx must be started before tx due to spi instinct */
251 if (rxdesc) {
252 set_bit(RX_BUSY, &dws->dma_chan_busy);
253 dmaengine_submit(rxdesc);
254 dma_async_issue_pending(dws->rxchan);
255 }
256
257 if (txdesc) {
258 set_bit(TX_BUSY, &dws->dma_chan_busy);
259 dmaengine_submit(txdesc);
260 dma_async_issue_pending(dws->txchan);
261 }
262
263 return 0;
264}
265
266static void mid_spi_dma_stop(struct dw_spi *dws)
267{
268 if (test_bit(TX_BUSY, &dws->dma_chan_busy)) {
269 dmaengine_terminate_sync(dws->txchan);
270 clear_bit(TX_BUSY, &dws->dma_chan_busy);
271 }
272 if (test_bit(RX_BUSY, &dws->dma_chan_busy)) {
273 dmaengine_terminate_sync(dws->rxchan);
274 clear_bit(RX_BUSY, &dws->dma_chan_busy);
275 }
276}
277
278static const struct dw_spi_dma_ops mid_dma_ops = {
279 .dma_init = mid_spi_dma_init,
280 .dma_exit = mid_spi_dma_exit,
281 .dma_setup = mid_spi_dma_setup,
282 .can_dma = mid_spi_can_dma,
283 .dma_transfer = mid_spi_dma_transfer,
284 .dma_stop = mid_spi_dma_stop,
285};
286#endif
287
288/* Some specific info for SPI0 controller on Intel MID */
289
290/* HW info for MRST Clk Control Unit, 32b reg per controller */
291#define MRST_SPI_CLK_BASE 100000000 /* 100m */
292#define MRST_CLK_SPI_REG 0xff11d86c
293#define CLK_SPI_BDIV_OFFSET 0
294#define CLK_SPI_BDIV_MASK 0x00000007
295#define CLK_SPI_CDIV_OFFSET 9
296#define CLK_SPI_CDIV_MASK 0x00000e00
297#define CLK_SPI_DISABLE_OFFSET 8
298
299int dw_spi_mid_init(struct dw_spi *dws)
300{
301 void __iomem *clk_reg;
302 u32 clk_cdiv;
303
304 clk_reg = ioremap_nocache(MRST_CLK_SPI_REG, 16);
305 if (!clk_reg)
306 return -ENOMEM;
307
308 /* Get SPI controller operating freq info */
309 clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));
310 clk_cdiv &= CLK_SPI_CDIV_MASK;
311 clk_cdiv >>= CLK_SPI_CDIV_OFFSET;
312 dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
313
314 iounmap(clk_reg);
315
316#ifdef CONFIG_SPI_DW_MID_DMA
317 dws->dma_tx = &mid_dma_tx;
318 dws->dma_rx = &mid_dma_rx;
319 dws->dma_ops = &mid_dma_ops;
320#endif
321 return 0;
322}