Loading...
1/*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
4 * JZ4740 SoC RTC driver
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * You should have received a copy of the GNU General Public License along
12 * with this program; if not, write to the Free Software Foundation, Inc.,
13 * 675 Mass Ave, Cambridge, MA 02139, USA.
14 *
15 */
16
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/rtc.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23
24#define JZ_REG_RTC_CTRL 0x00
25#define JZ_REG_RTC_SEC 0x04
26#define JZ_REG_RTC_SEC_ALARM 0x08
27#define JZ_REG_RTC_REGULATOR 0x0C
28#define JZ_REG_RTC_HIBERNATE 0x20
29#define JZ_REG_RTC_SCRATCHPAD 0x34
30
31#define JZ_RTC_CTRL_WRDY BIT(7)
32#define JZ_RTC_CTRL_1HZ BIT(6)
33#define JZ_RTC_CTRL_1HZ_IRQ BIT(5)
34#define JZ_RTC_CTRL_AF BIT(4)
35#define JZ_RTC_CTRL_AF_IRQ BIT(3)
36#define JZ_RTC_CTRL_AE BIT(2)
37#define JZ_RTC_CTRL_ENABLE BIT(0)
38
39struct jz4740_rtc {
40 struct resource *mem;
41 void __iomem *base;
42
43 struct rtc_device *rtc;
44
45 unsigned int irq;
46
47 spinlock_t lock;
48};
49
50static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
51{
52 return readl(rtc->base + reg);
53}
54
55static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
56{
57 uint32_t ctrl;
58 int timeout = 1000;
59
60 do {
61 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
62 } while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout);
63
64 return timeout ? 0 : -EIO;
65}
66
67static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
68 uint32_t val)
69{
70 int ret;
71 ret = jz4740_rtc_wait_write_ready(rtc);
72 if (ret == 0)
73 writel(val, rtc->base + reg);
74
75 return ret;
76}
77
78static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
79 bool set)
80{
81 int ret;
82 unsigned long flags;
83 uint32_t ctrl;
84
85 spin_lock_irqsave(&rtc->lock, flags);
86
87 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
88
89 /* Don't clear interrupt flags by accident */
90 ctrl |= JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF;
91
92 if (set)
93 ctrl |= mask;
94 else
95 ctrl &= ~mask;
96
97 ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);
98
99 spin_unlock_irqrestore(&rtc->lock, flags);
100
101 return ret;
102}
103
104static int jz4740_rtc_read_time(struct device *dev, struct rtc_time *time)
105{
106 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
107 uint32_t secs, secs2;
108 int timeout = 5;
109
110 /* If the seconds register is read while it is updated, it can contain a
111 * bogus value. This can be avoided by making sure that two consecutive
112 * reads have the same value.
113 */
114 secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
115 secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
116
117 while (secs != secs2 && --timeout) {
118 secs = secs2;
119 secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
120 }
121
122 if (timeout == 0)
123 return -EIO;
124
125 rtc_time_to_tm(secs, time);
126
127 return rtc_valid_tm(time);
128}
129
130static int jz4740_rtc_set_mmss(struct device *dev, unsigned long secs)
131{
132 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
133
134 return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, secs);
135}
136
137static int jz4740_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
138{
139 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
140 uint32_t secs;
141 uint32_t ctrl;
142
143 secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
144
145 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
146
147 alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
148 alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);
149
150 rtc_time_to_tm(secs, &alrm->time);
151
152 return rtc_valid_tm(&alrm->time);
153}
154
155static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
156{
157 int ret;
158 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
159 unsigned long secs;
160
161 rtc_tm_to_time(&alrm->time, &secs);
162
163 ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, secs);
164 if (!ret)
165 ret = jz4740_rtc_ctrl_set_bits(rtc,
166 JZ_RTC_CTRL_AE | JZ_RTC_CTRL_AF_IRQ, alrm->enabled);
167
168 return ret;
169}
170
171static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
172{
173 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
174 return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);
175}
176
177static struct rtc_class_ops jz4740_rtc_ops = {
178 .read_time = jz4740_rtc_read_time,
179 .set_mmss = jz4740_rtc_set_mmss,
180 .read_alarm = jz4740_rtc_read_alarm,
181 .set_alarm = jz4740_rtc_set_alarm,
182 .alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
183};
184
185static irqreturn_t jz4740_rtc_irq(int irq, void *data)
186{
187 struct jz4740_rtc *rtc = data;
188 uint32_t ctrl;
189 unsigned long events = 0;
190
191 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
192
193 if (ctrl & JZ_RTC_CTRL_1HZ)
194 events |= (RTC_UF | RTC_IRQF);
195
196 if (ctrl & JZ_RTC_CTRL_AF)
197 events |= (RTC_AF | RTC_IRQF);
198
199 rtc_update_irq(rtc->rtc, 1, events);
200
201 jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF, false);
202
203 return IRQ_HANDLED;
204}
205
206void jz4740_rtc_poweroff(struct device *dev)
207{
208 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
209 jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);
210}
211EXPORT_SYMBOL_GPL(jz4740_rtc_poweroff);
212
213static int __devinit jz4740_rtc_probe(struct platform_device *pdev)
214{
215 int ret;
216 struct jz4740_rtc *rtc;
217 uint32_t scratchpad;
218
219 rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
220 if (!rtc)
221 return -ENOMEM;
222
223 rtc->irq = platform_get_irq(pdev, 0);
224 if (rtc->irq < 0) {
225 ret = -ENOENT;
226 dev_err(&pdev->dev, "Failed to get platform irq\n");
227 goto err_free;
228 }
229
230 rtc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
231 if (!rtc->mem) {
232 ret = -ENOENT;
233 dev_err(&pdev->dev, "Failed to get platform mmio memory\n");
234 goto err_free;
235 }
236
237 rtc->mem = request_mem_region(rtc->mem->start, resource_size(rtc->mem),
238 pdev->name);
239 if (!rtc->mem) {
240 ret = -EBUSY;
241 dev_err(&pdev->dev, "Failed to request mmio memory region\n");
242 goto err_free;
243 }
244
245 rtc->base = ioremap_nocache(rtc->mem->start, resource_size(rtc->mem));
246 if (!rtc->base) {
247 ret = -EBUSY;
248 dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
249 goto err_release_mem_region;
250 }
251
252 spin_lock_init(&rtc->lock);
253
254 platform_set_drvdata(pdev, rtc);
255
256 device_init_wakeup(&pdev->dev, 1);
257
258 rtc->rtc = rtc_device_register(pdev->name, &pdev->dev, &jz4740_rtc_ops,
259 THIS_MODULE);
260 if (IS_ERR(rtc->rtc)) {
261 ret = PTR_ERR(rtc->rtc);
262 dev_err(&pdev->dev, "Failed to register rtc device: %d\n", ret);
263 goto err_iounmap;
264 }
265
266 ret = request_irq(rtc->irq, jz4740_rtc_irq, 0,
267 pdev->name, rtc);
268 if (ret) {
269 dev_err(&pdev->dev, "Failed to request rtc irq: %d\n", ret);
270 goto err_unregister_rtc;
271 }
272
273 scratchpad = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD);
274 if (scratchpad != 0x12345678) {
275 ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
276 ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, 0);
277 if (ret) {
278 dev_err(&pdev->dev, "Could not write write to RTC registers\n");
279 goto err_free_irq;
280 }
281 }
282
283 return 0;
284
285err_free_irq:
286 free_irq(rtc->irq, rtc);
287err_unregister_rtc:
288 rtc_device_unregister(rtc->rtc);
289err_iounmap:
290 platform_set_drvdata(pdev, NULL);
291 iounmap(rtc->base);
292err_release_mem_region:
293 release_mem_region(rtc->mem->start, resource_size(rtc->mem));
294err_free:
295 kfree(rtc);
296
297 return ret;
298}
299
300static int __devexit jz4740_rtc_remove(struct platform_device *pdev)
301{
302 struct jz4740_rtc *rtc = platform_get_drvdata(pdev);
303
304 free_irq(rtc->irq, rtc);
305
306 rtc_device_unregister(rtc->rtc);
307
308 iounmap(rtc->base);
309 release_mem_region(rtc->mem->start, resource_size(rtc->mem));
310
311 kfree(rtc);
312
313 platform_set_drvdata(pdev, NULL);
314
315 return 0;
316}
317
318
319#ifdef CONFIG_PM
320static int jz4740_rtc_suspend(struct device *dev)
321{
322 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
323
324 if (device_may_wakeup(dev))
325 enable_irq_wake(rtc->irq);
326 return 0;
327}
328
329static int jz4740_rtc_resume(struct device *dev)
330{
331 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
332
333 if (device_may_wakeup(dev))
334 disable_irq_wake(rtc->irq);
335 return 0;
336}
337
338static const struct dev_pm_ops jz4740_pm_ops = {
339 .suspend = jz4740_rtc_suspend,
340 .resume = jz4740_rtc_resume,
341};
342#define JZ4740_RTC_PM_OPS (&jz4740_pm_ops)
343
344#else
345#define JZ4740_RTC_PM_OPS NULL
346#endif /* CONFIG_PM */
347
348static struct platform_driver jz4740_rtc_driver = {
349 .probe = jz4740_rtc_probe,
350 .remove = __devexit_p(jz4740_rtc_remove),
351 .driver = {
352 .name = "jz4740-rtc",
353 .owner = THIS_MODULE,
354 .pm = JZ4740_RTC_PM_OPS,
355 },
356};
357
358module_platform_driver(jz4740_rtc_driver);
359
360MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
361MODULE_LICENSE("GPL");
362MODULE_DESCRIPTION("RTC driver for the JZ4740 SoC\n");
363MODULE_ALIAS("platform:jz4740-rtc");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
4 * Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
5 * JZ4740 SoC RTC driver
6 */
7
8#include <linux/clk.h>
9#include <linux/io.h>
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/of_device.h>
13#include <linux/platform_device.h>
14#include <linux/pm_wakeirq.h>
15#include <linux/reboot.h>
16#include <linux/rtc.h>
17#include <linux/slab.h>
18#include <linux/spinlock.h>
19
20#define JZ_REG_RTC_CTRL 0x00
21#define JZ_REG_RTC_SEC 0x04
22#define JZ_REG_RTC_SEC_ALARM 0x08
23#define JZ_REG_RTC_REGULATOR 0x0C
24#define JZ_REG_RTC_HIBERNATE 0x20
25#define JZ_REG_RTC_WAKEUP_FILTER 0x24
26#define JZ_REG_RTC_RESET_COUNTER 0x28
27#define JZ_REG_RTC_SCRATCHPAD 0x34
28
29/* The following are present on the jz4780 */
30#define JZ_REG_RTC_WENR 0x3C
31#define JZ_RTC_WENR_WEN BIT(31)
32
33#define JZ_RTC_CTRL_WRDY BIT(7)
34#define JZ_RTC_CTRL_1HZ BIT(6)
35#define JZ_RTC_CTRL_1HZ_IRQ BIT(5)
36#define JZ_RTC_CTRL_AF BIT(4)
37#define JZ_RTC_CTRL_AF_IRQ BIT(3)
38#define JZ_RTC_CTRL_AE BIT(2)
39#define JZ_RTC_CTRL_ENABLE BIT(0)
40
41/* Magic value to enable writes on jz4780 */
42#define JZ_RTC_WENR_MAGIC 0xA55A
43
44#define JZ_RTC_WAKEUP_FILTER_MASK 0x0000FFE0
45#define JZ_RTC_RESET_COUNTER_MASK 0x00000FE0
46
47enum jz4740_rtc_type {
48 ID_JZ4740,
49 ID_JZ4780,
50};
51
52struct jz4740_rtc {
53 void __iomem *base;
54 enum jz4740_rtc_type type;
55
56 struct rtc_device *rtc;
57 struct clk *clk;
58
59 int irq;
60
61 spinlock_t lock;
62
63 unsigned int min_wakeup_pin_assert_time;
64 unsigned int reset_pin_assert_time;
65};
66
67static struct device *dev_for_power_off;
68
69static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
70{
71 return readl(rtc->base + reg);
72}
73
74static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
75{
76 uint32_t ctrl;
77 int timeout = 10000;
78
79 do {
80 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
81 } while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout);
82
83 return timeout ? 0 : -EIO;
84}
85
86static inline int jz4780_rtc_enable_write(struct jz4740_rtc *rtc)
87{
88 uint32_t ctrl;
89 int ret, timeout = 10000;
90
91 ret = jz4740_rtc_wait_write_ready(rtc);
92 if (ret != 0)
93 return ret;
94
95 writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR);
96
97 do {
98 ctrl = readl(rtc->base + JZ_REG_RTC_WENR);
99 } while (!(ctrl & JZ_RTC_WENR_WEN) && --timeout);
100
101 return timeout ? 0 : -EIO;
102}
103
104static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
105 uint32_t val)
106{
107 int ret = 0;
108
109 if (rtc->type >= ID_JZ4780)
110 ret = jz4780_rtc_enable_write(rtc);
111 if (ret == 0)
112 ret = jz4740_rtc_wait_write_ready(rtc);
113 if (ret == 0)
114 writel(val, rtc->base + reg);
115
116 return ret;
117}
118
119static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
120 bool set)
121{
122 int ret;
123 unsigned long flags;
124 uint32_t ctrl;
125
126 spin_lock_irqsave(&rtc->lock, flags);
127
128 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
129
130 /* Don't clear interrupt flags by accident */
131 ctrl |= JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF;
132
133 if (set)
134 ctrl |= mask;
135 else
136 ctrl &= ~mask;
137
138 ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);
139
140 spin_unlock_irqrestore(&rtc->lock, flags);
141
142 return ret;
143}
144
145static int jz4740_rtc_read_time(struct device *dev, struct rtc_time *time)
146{
147 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
148 uint32_t secs, secs2;
149 int timeout = 5;
150
151 if (jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD) != 0x12345678)
152 return -EINVAL;
153
154 /* If the seconds register is read while it is updated, it can contain a
155 * bogus value. This can be avoided by making sure that two consecutive
156 * reads have the same value.
157 */
158 secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
159 secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
160
161 while (secs != secs2 && --timeout) {
162 secs = secs2;
163 secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
164 }
165
166 if (timeout == 0)
167 return -EIO;
168
169 rtc_time64_to_tm(secs, time);
170
171 return 0;
172}
173
174static int jz4740_rtc_set_time(struct device *dev, struct rtc_time *time)
175{
176 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
177 int ret;
178
179 ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, rtc_tm_to_time64(time));
180 if (ret)
181 return ret;
182
183 return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
184}
185
186static int jz4740_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
187{
188 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
189 uint32_t secs;
190 uint32_t ctrl;
191
192 secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
193
194 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
195
196 alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
197 alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);
198
199 rtc_time64_to_tm(secs, &alrm->time);
200
201 return 0;
202}
203
204static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
205{
206 int ret;
207 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
208 uint32_t secs = lower_32_bits(rtc_tm_to_time64(&alrm->time));
209
210 ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, secs);
211 if (!ret)
212 ret = jz4740_rtc_ctrl_set_bits(rtc,
213 JZ_RTC_CTRL_AE | JZ_RTC_CTRL_AF_IRQ, alrm->enabled);
214
215 return ret;
216}
217
218static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
219{
220 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
221 return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);
222}
223
224static const struct rtc_class_ops jz4740_rtc_ops = {
225 .read_time = jz4740_rtc_read_time,
226 .set_time = jz4740_rtc_set_time,
227 .read_alarm = jz4740_rtc_read_alarm,
228 .set_alarm = jz4740_rtc_set_alarm,
229 .alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
230};
231
232static irqreturn_t jz4740_rtc_irq(int irq, void *data)
233{
234 struct jz4740_rtc *rtc = data;
235 uint32_t ctrl;
236 unsigned long events = 0;
237
238 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
239
240 if (ctrl & JZ_RTC_CTRL_1HZ)
241 events |= (RTC_UF | RTC_IRQF);
242
243 if (ctrl & JZ_RTC_CTRL_AF)
244 events |= (RTC_AF | RTC_IRQF);
245
246 rtc_update_irq(rtc->rtc, 1, events);
247
248 jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF, false);
249
250 return IRQ_HANDLED;
251}
252
253static void jz4740_rtc_poweroff(struct device *dev)
254{
255 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
256 jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);
257}
258
259static void jz4740_rtc_power_off(void)
260{
261 struct jz4740_rtc *rtc = dev_get_drvdata(dev_for_power_off);
262 unsigned long rtc_rate;
263 unsigned long wakeup_filter_ticks;
264 unsigned long reset_counter_ticks;
265
266 clk_prepare_enable(rtc->clk);
267
268 rtc_rate = clk_get_rate(rtc->clk);
269
270 /*
271 * Set minimum wakeup pin assertion time: 100 ms.
272 * Range is 0 to 2 sec if RTC is clocked at 32 kHz.
273 */
274 wakeup_filter_ticks =
275 (rtc->min_wakeup_pin_assert_time * rtc_rate) / 1000;
276 if (wakeup_filter_ticks < JZ_RTC_WAKEUP_FILTER_MASK)
277 wakeup_filter_ticks &= JZ_RTC_WAKEUP_FILTER_MASK;
278 else
279 wakeup_filter_ticks = JZ_RTC_WAKEUP_FILTER_MASK;
280 jz4740_rtc_reg_write(rtc,
281 JZ_REG_RTC_WAKEUP_FILTER, wakeup_filter_ticks);
282
283 /*
284 * Set reset pin low-level assertion time after wakeup: 60 ms.
285 * Range is 0 to 125 ms if RTC is clocked at 32 kHz.
286 */
287 reset_counter_ticks = (rtc->reset_pin_assert_time * rtc_rate) / 1000;
288 if (reset_counter_ticks < JZ_RTC_RESET_COUNTER_MASK)
289 reset_counter_ticks &= JZ_RTC_RESET_COUNTER_MASK;
290 else
291 reset_counter_ticks = JZ_RTC_RESET_COUNTER_MASK;
292 jz4740_rtc_reg_write(rtc,
293 JZ_REG_RTC_RESET_COUNTER, reset_counter_ticks);
294
295 jz4740_rtc_poweroff(dev_for_power_off);
296 kernel_halt();
297}
298
299static const struct of_device_id jz4740_rtc_of_match[] = {
300 { .compatible = "ingenic,jz4740-rtc", .data = (void *)ID_JZ4740 },
301 { .compatible = "ingenic,jz4780-rtc", .data = (void *)ID_JZ4780 },
302 {},
303};
304MODULE_DEVICE_TABLE(of, jz4740_rtc_of_match);
305
306static int jz4740_rtc_probe(struct platform_device *pdev)
307{
308 int ret;
309 struct jz4740_rtc *rtc;
310 struct resource *mem;
311 const struct platform_device_id *id = platform_get_device_id(pdev);
312 const struct of_device_id *of_id = of_match_device(
313 jz4740_rtc_of_match, &pdev->dev);
314 struct device_node *np = pdev->dev.of_node;
315
316 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
317 if (!rtc)
318 return -ENOMEM;
319
320 if (of_id)
321 rtc->type = (enum jz4740_rtc_type)of_id->data;
322 else
323 rtc->type = id->driver_data;
324
325 rtc->irq = platform_get_irq(pdev, 0);
326 if (rtc->irq < 0)
327 return -ENOENT;
328
329 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
330 rtc->base = devm_ioremap_resource(&pdev->dev, mem);
331 if (IS_ERR(rtc->base))
332 return PTR_ERR(rtc->base);
333
334 rtc->clk = devm_clk_get(&pdev->dev, "rtc");
335 if (IS_ERR(rtc->clk)) {
336 dev_err(&pdev->dev, "Failed to get RTC clock\n");
337 return PTR_ERR(rtc->clk);
338 }
339
340 spin_lock_init(&rtc->lock);
341
342 platform_set_drvdata(pdev, rtc);
343
344 device_init_wakeup(&pdev->dev, 1);
345
346 ret = dev_pm_set_wake_irq(&pdev->dev, rtc->irq);
347 if (ret) {
348 dev_err(&pdev->dev, "Failed to set wake irq: %d\n", ret);
349 return ret;
350 }
351
352 rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
353 if (IS_ERR(rtc->rtc)) {
354 ret = PTR_ERR(rtc->rtc);
355 dev_err(&pdev->dev, "Failed to allocate rtc device: %d\n", ret);
356 return ret;
357 }
358
359 rtc->rtc->ops = &jz4740_rtc_ops;
360 rtc->rtc->range_max = U32_MAX;
361
362 ret = rtc_register_device(rtc->rtc);
363 if (ret)
364 return ret;
365
366 ret = devm_request_irq(&pdev->dev, rtc->irq, jz4740_rtc_irq, 0,
367 pdev->name, rtc);
368 if (ret) {
369 dev_err(&pdev->dev, "Failed to request rtc irq: %d\n", ret);
370 return ret;
371 }
372
373 if (np && of_device_is_system_power_controller(np)) {
374 if (!pm_power_off) {
375 /* Default: 60ms */
376 rtc->reset_pin_assert_time = 60;
377 of_property_read_u32(np, "reset-pin-assert-time-ms",
378 &rtc->reset_pin_assert_time);
379
380 /* Default: 100ms */
381 rtc->min_wakeup_pin_assert_time = 100;
382 of_property_read_u32(np,
383 "min-wakeup-pin-assert-time-ms",
384 &rtc->min_wakeup_pin_assert_time);
385
386 dev_for_power_off = &pdev->dev;
387 pm_power_off = jz4740_rtc_power_off;
388 } else {
389 dev_warn(&pdev->dev,
390 "Poweroff handler already present!\n");
391 }
392 }
393
394 return 0;
395}
396
397static const struct platform_device_id jz4740_rtc_ids[] = {
398 { "jz4740-rtc", ID_JZ4740 },
399 { "jz4780-rtc", ID_JZ4780 },
400 {}
401};
402MODULE_DEVICE_TABLE(platform, jz4740_rtc_ids);
403
404static struct platform_driver jz4740_rtc_driver = {
405 .probe = jz4740_rtc_probe,
406 .driver = {
407 .name = "jz4740-rtc",
408 .of_match_table = of_match_ptr(jz4740_rtc_of_match),
409 },
410 .id_table = jz4740_rtc_ids,
411};
412
413module_platform_driver(jz4740_rtc_driver);
414
415MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
416MODULE_LICENSE("GPL");
417MODULE_DESCRIPTION("RTC driver for the JZ4740 SoC\n");
418MODULE_ALIAS("platform:jz4740-rtc");