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1/*
2 * PCI Express Hot Plug Controller Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
27 *
28 */
29#ifndef _PCIEHP_H
30#define _PCIEHP_H
31
32#include <linux/types.h>
33#include <linux/pci.h>
34#include <linux/pci_hotplug.h>
35#include <linux/delay.h>
36#include <linux/sched.h> /* signal_pending() */
37#include <linux/pcieport_if.h>
38#include <linux/mutex.h>
39#include <linux/workqueue.h>
40
41#define MY_NAME "pciehp"
42
43extern bool pciehp_poll_mode;
44extern int pciehp_poll_time;
45extern bool pciehp_debug;
46extern bool pciehp_force;
47extern struct workqueue_struct *pciehp_wq;
48
49#define dbg(format, arg...) \
50do { \
51 if (pciehp_debug) \
52 printk(KERN_DEBUG "%s: " format, MY_NAME , ## arg); \
53} while (0)
54#define err(format, arg...) \
55 printk(KERN_ERR "%s: " format, MY_NAME , ## arg)
56#define info(format, arg...) \
57 printk(KERN_INFO "%s: " format, MY_NAME , ## arg)
58#define warn(format, arg...) \
59 printk(KERN_WARNING "%s: " format, MY_NAME , ## arg)
60
61#define ctrl_dbg(ctrl, format, arg...) \
62 do { \
63 if (pciehp_debug) \
64 dev_printk(KERN_DEBUG, &ctrl->pcie->device, \
65 format, ## arg); \
66 } while (0)
67#define ctrl_err(ctrl, format, arg...) \
68 dev_err(&ctrl->pcie->device, format, ## arg)
69#define ctrl_info(ctrl, format, arg...) \
70 dev_info(&ctrl->pcie->device, format, ## arg)
71#define ctrl_warn(ctrl, format, arg...) \
72 dev_warn(&ctrl->pcie->device, format, ## arg)
73
74#define SLOT_NAME_SIZE 10
75struct slot {
76 u8 state;
77 struct controller *ctrl;
78 struct hotplug_slot *hotplug_slot;
79 struct delayed_work work; /* work for button event */
80 struct mutex lock;
81};
82
83struct event_info {
84 u32 event_type;
85 struct slot *p_slot;
86 struct work_struct work;
87};
88
89struct controller {
90 struct mutex ctrl_lock; /* controller lock */
91 struct pcie_device *pcie; /* PCI Express port service */
92 struct slot *slot;
93 wait_queue_head_t queue; /* sleep & wake process */
94 u32 slot_cap;
95 struct timer_list poll_timer;
96 unsigned int cmd_busy:1;
97 unsigned int no_cmd_complete:1;
98 unsigned int link_active_reporting:1;
99 unsigned int notification_enabled:1;
100 unsigned int power_fault_detected;
101};
102
103#define INT_BUTTON_IGNORE 0
104#define INT_PRESENCE_ON 1
105#define INT_PRESENCE_OFF 2
106#define INT_SWITCH_CLOSE 3
107#define INT_SWITCH_OPEN 4
108#define INT_POWER_FAULT 5
109#define INT_POWER_FAULT_CLEAR 6
110#define INT_BUTTON_PRESS 7
111#define INT_BUTTON_RELEASE 8
112#define INT_BUTTON_CANCEL 9
113
114#define STATIC_STATE 0
115#define BLINKINGON_STATE 1
116#define BLINKINGOFF_STATE 2
117#define POWERON_STATE 3
118#define POWEROFF_STATE 4
119
120#define ATTN_BUTTN(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_ABP)
121#define POWER_CTRL(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_PCP)
122#define MRL_SENS(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_MRLSP)
123#define ATTN_LED(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_AIP)
124#define PWR_LED(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_PIP)
125#define HP_SUPR_RM(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_HPS)
126#define EMI(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_EIP)
127#define NO_CMD_CMPL(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_NCCS)
128#define PSN(ctrl) ((ctrl)->slot_cap >> 19)
129
130extern int pciehp_sysfs_enable_slot(struct slot *slot);
131extern int pciehp_sysfs_disable_slot(struct slot *slot);
132extern u8 pciehp_handle_attention_button(struct slot *p_slot);
133extern u8 pciehp_handle_switch_change(struct slot *p_slot);
134extern u8 pciehp_handle_presence_change(struct slot *p_slot);
135extern u8 pciehp_handle_power_fault(struct slot *p_slot);
136extern int pciehp_configure_device(struct slot *p_slot);
137extern int pciehp_unconfigure_device(struct slot *p_slot);
138extern void pciehp_queue_pushbutton_work(struct work_struct *work);
139struct controller *pcie_init(struct pcie_device *dev);
140int pcie_init_notification(struct controller *ctrl);
141int pciehp_enable_slot(struct slot *p_slot);
142int pciehp_disable_slot(struct slot *p_slot);
143int pcie_enable_notification(struct controller *ctrl);
144int pciehp_power_on_slot(struct slot *slot);
145int pciehp_power_off_slot(struct slot *slot);
146int pciehp_get_power_status(struct slot *slot, u8 *status);
147int pciehp_get_attention_status(struct slot *slot, u8 *status);
148
149int pciehp_set_attention_status(struct slot *slot, u8 status);
150int pciehp_get_latch_status(struct slot *slot, u8 *status);
151int pciehp_get_adapter_status(struct slot *slot, u8 *status);
152int pciehp_get_max_link_speed(struct slot *slot, enum pci_bus_speed *speed);
153int pciehp_get_max_link_width(struct slot *slot, enum pcie_link_width *val);
154int pciehp_get_cur_link_speed(struct slot *slot, enum pci_bus_speed *speed);
155int pciehp_get_cur_link_width(struct slot *slot, enum pcie_link_width *val);
156int pciehp_query_power_fault(struct slot *slot);
157void pciehp_green_led_on(struct slot *slot);
158void pciehp_green_led_off(struct slot *slot);
159void pciehp_green_led_blink(struct slot *slot);
160int pciehp_check_link_status(struct controller *ctrl);
161void pciehp_release_ctrl(struct controller *ctrl);
162
163static inline const char *slot_name(struct slot *slot)
164{
165 return hotplug_slot_name(slot->hotplug_slot);
166}
167
168#ifdef CONFIG_ACPI
169#include <acpi/acpi.h>
170#include <acpi/acpi_bus.h>
171#include <linux/pci-acpi.h>
172
173extern void __init pciehp_acpi_slot_detection_init(void);
174extern int pciehp_acpi_slot_detection_check(struct pci_dev *dev);
175
176static inline void pciehp_firmware_init(void)
177{
178 pciehp_acpi_slot_detection_init();
179}
180#else
181#define pciehp_firmware_init() do {} while (0)
182static inline int pciehp_acpi_slot_detection_check(struct pci_dev *dev)
183{
184 return 0;
185}
186#endif /* CONFIG_ACPI */
187#endif /* _PCIEHP_H */
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * PCI Express Hot Plug Controller Driver
4 *
5 * Copyright (C) 1995,2001 Compaq Computer Corporation
6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
7 * Copyright (C) 2001 IBM Corp.
8 * Copyright (C) 2003-2004 Intel Corporation
9 *
10 * All rights reserved.
11 *
12 * Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
13 *
14 */
15#ifndef _PCIEHP_H
16#define _PCIEHP_H
17
18#include <linux/types.h>
19#include <linux/pci.h>
20#include <linux/pci_hotplug.h>
21#include <linux/delay.h>
22#include <linux/mutex.h>
23#include <linux/rwsem.h>
24#include <linux/workqueue.h>
25
26#include "../pcie/portdrv.h"
27
28extern bool pciehp_poll_mode;
29extern int pciehp_poll_time;
30
31/*
32 * Set CONFIG_DYNAMIC_DEBUG=y and boot with 'dyndbg="file pciehp* +p"' to
33 * enable debug messages.
34 */
35#define ctrl_dbg(ctrl, format, arg...) \
36 pci_dbg(ctrl->pcie->port, format, ## arg)
37#define ctrl_err(ctrl, format, arg...) \
38 pci_err(ctrl->pcie->port, format, ## arg)
39#define ctrl_info(ctrl, format, arg...) \
40 pci_info(ctrl->pcie->port, format, ## arg)
41#define ctrl_warn(ctrl, format, arg...) \
42 pci_warn(ctrl->pcie->port, format, ## arg)
43
44#define SLOT_NAME_SIZE 10
45
46/**
47 * struct controller - PCIe hotplug controller
48 * @pcie: pointer to the controller's PCIe port service device
49 * @slot_cap: cached copy of the Slot Capabilities register
50 * @slot_ctrl: cached copy of the Slot Control register
51 * @ctrl_lock: serializes writes to the Slot Control register
52 * @cmd_started: jiffies when the Slot Control register was last written;
53 * the next write is allowed 1 second later, absent a Command Completed
54 * interrupt (PCIe r4.0, sec 6.7.3.2)
55 * @cmd_busy: flag set on Slot Control register write, cleared by IRQ handler
56 * on reception of a Command Completed event
57 * @queue: wait queue to wake up on reception of a Command Completed event,
58 * used for synchronous writes to the Slot Control register
59 * @pending_events: used by the IRQ handler to save events retrieved from the
60 * Slot Status register for later consumption by the IRQ thread
61 * @notification_enabled: whether the IRQ was requested successfully
62 * @power_fault_detected: whether a power fault was detected by the hardware
63 * that has not yet been cleared by the user
64 * @poll_thread: thread to poll for slot events if no IRQ is available,
65 * enabled with pciehp_poll_mode module parameter
66 * @state: current state machine position
67 * @state_lock: protects reads and writes of @state;
68 * protects scheduling, execution and cancellation of @button_work
69 * @button_work: work item to turn the slot on or off after 5 seconds
70 * in response to an Attention Button press
71 * @hotplug_slot: structure registered with the PCI hotplug core
72 * @reset_lock: prevents access to the Data Link Layer Link Active bit in the
73 * Link Status register and to the Presence Detect State bit in the Slot
74 * Status register during a slot reset which may cause them to flap
75 * @request_result: result of last user request submitted to the IRQ thread
76 * @requester: wait queue to wake up on completion of user request,
77 * used for synchronous slot enable/disable request via sysfs
78 *
79 * PCIe hotplug has a 1:1 relationship between controller and slot, hence
80 * unlike other drivers, the two aren't represented by separate structures.
81 */
82struct controller {
83 struct pcie_device *pcie;
84
85 u32 slot_cap; /* capabilities and quirks */
86
87 u16 slot_ctrl; /* control register access */
88 struct mutex ctrl_lock;
89 unsigned long cmd_started;
90 unsigned int cmd_busy:1;
91 wait_queue_head_t queue;
92
93 atomic_t pending_events; /* event handling */
94 unsigned int notification_enabled:1;
95 unsigned int power_fault_detected;
96 struct task_struct *poll_thread;
97
98 u8 state; /* state machine */
99 struct mutex state_lock;
100 struct delayed_work button_work;
101
102 struct hotplug_slot hotplug_slot; /* hotplug core interface */
103 struct rw_semaphore reset_lock;
104 int request_result;
105 wait_queue_head_t requester;
106};
107
108/**
109 * DOC: Slot state
110 *
111 * @OFF_STATE: slot is powered off, no subordinate devices are enumerated
112 * @BLINKINGON_STATE: slot will be powered on after the 5 second delay,
113 * Power Indicator is blinking
114 * @BLINKINGOFF_STATE: slot will be powered off after the 5 second delay,
115 * Power Indicator is blinking
116 * @POWERON_STATE: slot is currently powering on
117 * @POWEROFF_STATE: slot is currently powering off
118 * @ON_STATE: slot is powered on, subordinate devices have been enumerated
119 */
120#define OFF_STATE 0
121#define BLINKINGON_STATE 1
122#define BLINKINGOFF_STATE 2
123#define POWERON_STATE 3
124#define POWEROFF_STATE 4
125#define ON_STATE 5
126
127/**
128 * DOC: Flags to request an action from the IRQ thread
129 *
130 * These are stored together with events read from the Slot Status register,
131 * hence must be greater than its 16-bit width.
132 *
133 * %DISABLE_SLOT: Disable the slot in response to a user request via sysfs or
134 * an Attention Button press after the 5 second delay
135 * %RERUN_ISR: Used by the IRQ handler to inform the IRQ thread that the
136 * hotplug port was inaccessible when the interrupt occurred, requiring
137 * that the IRQ handler is rerun by the IRQ thread after it has made the
138 * hotplug port accessible by runtime resuming its parents to D0
139 */
140#define DISABLE_SLOT (1 << 16)
141#define RERUN_ISR (1 << 17)
142
143#define ATTN_BUTTN(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_ABP)
144#define POWER_CTRL(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_PCP)
145#define MRL_SENS(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_MRLSP)
146#define ATTN_LED(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_AIP)
147#define PWR_LED(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_PIP)
148#define HP_SUPR_RM(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_HPS)
149#define EMI(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_EIP)
150#define NO_CMD_CMPL(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_NCCS)
151#define PSN(ctrl) (((ctrl)->slot_cap & PCI_EXP_SLTCAP_PSN) >> 19)
152
153void pciehp_request(struct controller *ctrl, int action);
154void pciehp_handle_button_press(struct controller *ctrl);
155void pciehp_handle_disable_request(struct controller *ctrl);
156void pciehp_handle_presence_or_link_change(struct controller *ctrl, u32 events);
157int pciehp_configure_device(struct controller *ctrl);
158void pciehp_unconfigure_device(struct controller *ctrl, bool presence);
159void pciehp_queue_pushbutton_work(struct work_struct *work);
160struct controller *pcie_init(struct pcie_device *dev);
161int pcie_init_notification(struct controller *ctrl);
162void pcie_shutdown_notification(struct controller *ctrl);
163void pcie_clear_hotplug_events(struct controller *ctrl);
164void pcie_enable_interrupt(struct controller *ctrl);
165void pcie_disable_interrupt(struct controller *ctrl);
166int pciehp_power_on_slot(struct controller *ctrl);
167void pciehp_power_off_slot(struct controller *ctrl);
168void pciehp_get_power_status(struct controller *ctrl, u8 *status);
169
170#define INDICATOR_NOOP -1 /* Leave indicator unchanged */
171void pciehp_set_indicators(struct controller *ctrl, int pwr, int attn);
172
173void pciehp_get_latch_status(struct controller *ctrl, u8 *status);
174int pciehp_query_power_fault(struct controller *ctrl);
175bool pciehp_card_present(struct controller *ctrl);
176bool pciehp_card_present_or_link_active(struct controller *ctrl);
177int pciehp_check_link_status(struct controller *ctrl);
178bool pciehp_check_link_active(struct controller *ctrl);
179void pciehp_release_ctrl(struct controller *ctrl);
180
181int pciehp_sysfs_enable_slot(struct hotplug_slot *hotplug_slot);
182int pciehp_sysfs_disable_slot(struct hotplug_slot *hotplug_slot);
183int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, int probe);
184int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status);
185int pciehp_set_raw_indicator_status(struct hotplug_slot *h_slot, u8 status);
186int pciehp_get_raw_indicator_status(struct hotplug_slot *h_slot, u8 *status);
187
188static inline const char *slot_name(struct controller *ctrl)
189{
190 return hotplug_slot_name(&ctrl->hotplug_slot);
191}
192
193static inline struct controller *to_ctrl(struct hotplug_slot *hotplug_slot)
194{
195 return container_of(hotplug_slot, struct controller, hotplug_slot);
196}
197
198#endif /* _PCIEHP_H */