1/*
   2 * Atmel MultiMedia Card Interface driver
   3 *
   4 * Copyright (C) 2004-2008 Atmel Corporation
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation.
   9 */
  10#include <linux/blkdev.h>
  11#include <linux/clk.h>
  12#include <linux/debugfs.h>
  13#include <linux/device.h>
  14#include <linux/dmaengine.h>
  15#include <linux/dma-mapping.h>
  16#include <linux/err.h>
  17#include <linux/gpio.h>
  18#include <linux/init.h>
  19#include <linux/interrupt.h>
 
  20#include <linux/ioport.h>
  21#include <linux/module.h>
 
 
 
  22#include <linux/platform_device.h>
  23#include <linux/scatterlist.h>
  24#include <linux/seq_file.h>
  25#include <linux/slab.h>
  26#include <linux/stat.h>
  27#include <linux/types.h>
  28
  29#include <linux/mmc/host.h>
  30#include <linux/mmc/sdio.h>
  31
  32#include <mach/atmel-mci.h>
  33#include <linux/atmel-mci.h>
  34#include <linux/atmel_pdc.h>
 
 
 
  35
 
  36#include <asm/io.h>
  37#include <asm/unaligned.h>
  38
  39#include <mach/cpu.h>
  40#include <mach/board.h>
 
 
  41
  42#include "atmel-mci-regs.h"
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  43
  44#define ATMCI_DATA_ERROR_FLAGS	(ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
  45#define ATMCI_DMA_THRESHOLD	16
  46
  47enum {
  48	EVENT_CMD_RDY = 0,
  49	EVENT_XFER_COMPLETE,
  50	EVENT_NOTBUSY,
  51	EVENT_DATA_ERROR,
  52};
  53
  54enum atmel_mci_state {
  55	STATE_IDLE = 0,
  56	STATE_SENDING_CMD,
  57	STATE_DATA_XFER,
  58	STATE_WAITING_NOTBUSY,
  59	STATE_SENDING_STOP,
  60	STATE_END_REQUEST,
  61};
  62
  63enum atmci_xfer_dir {
  64	XFER_RECEIVE = 0,
  65	XFER_TRANSMIT,
  66};
  67
  68enum atmci_pdc_buf {
  69	PDC_FIRST_BUF = 0,
  70	PDC_SECOND_BUF,
  71};
  72
  73struct atmel_mci_caps {
  74	bool    has_dma;
  75	bool    has_pdc;
  76	bool    has_cfg_reg;
  77	bool    has_cstor_reg;
  78	bool    has_highspeed;
  79	bool    has_rwproof;
  80	bool	has_odd_clk_div;
  81	bool	has_bad_data_ordering;
  82	bool	need_reset_after_xfer;
  83	bool	need_blksz_mul_4;
  84	bool	need_notbusy_for_read_ops;
  85};
  86
  87struct atmel_mci_dma {
  88	struct dma_chan			*chan;
  89	struct dma_async_tx_descriptor	*data_desc;
  90};
  91
  92/**
  93 * struct atmel_mci - MMC controller state shared between all slots
  94 * @lock: Spinlock protecting the queue and associated data.
  95 * @regs: Pointer to MMIO registers.
  96 * @sg: Scatterlist entry currently being processed by PIO or PDC code.
  97 * @pio_offset: Offset into the current scatterlist entry.
  98 * @buffer: Buffer used if we don't have the r/w proof capability. We
  99 *      don't have the time to switch pdc buffers so we have to use only
 100 *      one buffer for the full transaction.
 101 * @buf_size: size of the buffer.
 102 * @phys_buf_addr: buffer address needed for pdc.
 103 * @cur_slot: The slot which is currently using the controller.
 104 * @mrq: The request currently being processed on @cur_slot,
 105 *	or NULL if the controller is idle.
 106 * @cmd: The command currently being sent to the card, or NULL.
 107 * @data: The data currently being transferred, or NULL if no data
 108 *	transfer is in progress.
 109 * @data_size: just data->blocks * data->blksz.
 110 * @dma: DMA client state.
 111 * @data_chan: DMA channel being used for the current data transfer.
 112 * @cmd_status: Snapshot of SR taken upon completion of the current
 113 *	command. Only valid when EVENT_CMD_COMPLETE is pending.
 114 * @data_status: Snapshot of SR taken upon completion of the current
 115 *	data transfer. Only valid when EVENT_DATA_COMPLETE or
 116 *	EVENT_DATA_ERROR is pending.
 117 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
 118 *	to be sent.
 119 * @tasklet: Tasklet running the request state machine.
 120 * @pending_events: Bitmask of events flagged by the interrupt handler
 121 *	to be processed by the tasklet.
 122 * @completed_events: Bitmask of events which the state machine has
 123 *	processed.
 124 * @state: Tasklet state.
 125 * @queue: List of slots waiting for access to the controller.
 126 * @need_clock_update: Update the clock rate before the next request.
 127 * @need_reset: Reset controller before next request.
 128 * @timer: Timer to balance the data timeout error flag which cannot rise.
 129 * @mode_reg: Value of the MR register.
 130 * @cfg_reg: Value of the CFG register.
 131 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
 132 *	rate and timeout calculations.
 133 * @mapbase: Physical address of the MMIO registers.
 134 * @mck: The peripheral bus clock hooked up to the MMC controller.
 135 * @pdev: Platform device associated with the MMC controller.
 136 * @slot: Slots sharing this MMC controller.
 137 * @caps: MCI capabilities depending on MCI version.
 138 * @prepare_data: function to setup MCI before data transfer which
 139 * depends on MCI capabilities.
 140 * @submit_data: function to start data transfer which depends on MCI
 141 * capabilities.
 142 * @stop_transfer: function to stop data transfer which depends on MCI
 143 * capabilities.
 144 *
 145 * Locking
 146 * =======
 147 *
 148 * @lock is a softirq-safe spinlock protecting @queue as well as
 149 * @cur_slot, @mrq and @state. These must always be updated
 150 * at the same time while holding @lock.
 151 *
 152 * @lock also protects mode_reg and need_clock_update since these are
 153 * used to synchronize mode register updates with the queue
 154 * processing.
 155 *
 156 * The @mrq field of struct atmel_mci_slot is also protected by @lock,
 157 * and must always be written at the same time as the slot is added to
 158 * @queue.
 159 *
 160 * @pending_events and @completed_events are accessed using atomic bit
 161 * operations, so they don't need any locking.
 162 *
 163 * None of the fields touched by the interrupt handler need any
 164 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
 165 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
 166 * interrupts must be disabled and @data_status updated with a
 167 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
 168 * CMDRDY interrupt must be disabled and @cmd_status updated with a
 169 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
 170 * bytes_xfered field of @data must be written. This is ensured by
 171 * using barriers.
 172 */
 173struct atmel_mci {
 174	spinlock_t		lock;
 175	void __iomem		*regs;
 176
 177	struct scatterlist	*sg;
 
 178	unsigned int		pio_offset;
 179	unsigned int		*buffer;
 180	unsigned int		buf_size;
 181	dma_addr_t		buf_phys_addr;
 182
 183	struct atmel_mci_slot	*cur_slot;
 184	struct mmc_request	*mrq;
 185	struct mmc_command	*cmd;
 186	struct mmc_data		*data;
 187	unsigned int		data_size;
 188
 189	struct atmel_mci_dma	dma;
 190	struct dma_chan		*data_chan;
 191	struct dma_slave_config	dma_conf;
 192
 193	u32			cmd_status;
 194	u32			data_status;
 195	u32			stop_cmdr;
 196
 197	struct tasklet_struct	tasklet;
 198	unsigned long		pending_events;
 199	unsigned long		completed_events;
 200	enum atmel_mci_state	state;
 201	struct list_head	queue;
 202
 203	bool			need_clock_update;
 204	bool			need_reset;
 205	struct timer_list	timer;
 206	u32			mode_reg;
 207	u32			cfg_reg;
 208	unsigned long		bus_hz;
 209	unsigned long		mapbase;
 210	struct clk		*mck;
 211	struct platform_device	*pdev;
 212
 213	struct atmel_mci_slot	*slot[ATMCI_MAX_NR_SLOTS];
 214
 215	struct atmel_mci_caps   caps;
 216
 217	u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
 218	void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
 219	void (*stop_transfer)(struct atmel_mci *host);
 220};
 221
 222/**
 223 * struct atmel_mci_slot - MMC slot state
 224 * @mmc: The mmc_host representing this slot.
 225 * @host: The MMC controller this slot is using.
 226 * @sdc_reg: Value of SDCR to be written before using this slot.
 227 * @sdio_irq: SDIO irq mask for this slot.
 228 * @mrq: mmc_request currently being processed or waiting to be
 229 *	processed, or NULL when the slot is idle.
 230 * @queue_node: List node for placing this node in the @queue list of
 231 *	&struct atmel_mci.
 232 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
 233 * @flags: Random state bits associated with the slot.
 234 * @detect_pin: GPIO pin used for card detection, or negative if not
 235 *	available.
 236 * @wp_pin: GPIO pin used for card write protect sending, or negative
 237 *	if not available.
 238 * @detect_is_active_high: The state of the detect pin when it is active.
 239 * @detect_timer: Timer used for debouncing @detect_pin interrupts.
 240 */
 241struct atmel_mci_slot {
 242	struct mmc_host		*mmc;
 243	struct atmel_mci	*host;
 244
 245	u32			sdc_reg;
 246	u32			sdio_irq;
 247
 248	struct mmc_request	*mrq;
 249	struct list_head	queue_node;
 250
 251	unsigned int		clock;
 252	unsigned long		flags;
 253#define ATMCI_CARD_PRESENT	0
 254#define ATMCI_CARD_NEED_INIT	1
 255#define ATMCI_SHUTDOWN		2
 256#define ATMCI_SUSPENDED		3
 257
 258	int			detect_pin;
 259	int			wp_pin;
 260	bool			detect_is_active_high;
 261
 262	struct timer_list	detect_timer;
 263};
 264
 265#define atmci_test_and_clear_pending(host, event)		\
 266	test_and_clear_bit(event, &host->pending_events)
 267#define atmci_set_completed(host, event)			\
 268	set_bit(event, &host->completed_events)
 269#define atmci_set_pending(host, event)				\
 270	set_bit(event, &host->pending_events)
 271
 272/*
 273 * The debugfs stuff below is mostly optimized away when
 274 * CONFIG_DEBUG_FS is not set.
 275 */
 276static int atmci_req_show(struct seq_file *s, void *v)
 277{
 278	struct atmel_mci_slot	*slot = s->private;
 279	struct mmc_request	*mrq;
 280	struct mmc_command	*cmd;
 281	struct mmc_command	*stop;
 282	struct mmc_data		*data;
 283
 284	/* Make sure we get a consistent snapshot */
 285	spin_lock_bh(&slot->host->lock);
 286	mrq = slot->mrq;
 287
 288	if (mrq) {
 289		cmd = mrq->cmd;
 290		data = mrq->data;
 291		stop = mrq->stop;
 292
 293		if (cmd)
 294			seq_printf(s,
 295				"CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 296				cmd->opcode, cmd->arg, cmd->flags,
 297				cmd->resp[0], cmd->resp[1], cmd->resp[2],
 298				cmd->resp[3], cmd->error);
 299		if (data)
 300			seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 301				data->bytes_xfered, data->blocks,
 302				data->blksz, data->flags, data->error);
 303		if (stop)
 304			seq_printf(s,
 305				"CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 306				stop->opcode, stop->arg, stop->flags,
 307				stop->resp[0], stop->resp[1], stop->resp[2],
 308				stop->resp[3], stop->error);
 309	}
 310
 311	spin_unlock_bh(&slot->host->lock);
 312
 313	return 0;
 314}
 315
 316static int atmci_req_open(struct inode *inode, struct file *file)
 317{
 318	return single_open(file, atmci_req_show, inode->i_private);
 319}
 320
 321static const struct file_operations atmci_req_fops = {
 322	.owner		= THIS_MODULE,
 323	.open		= atmci_req_open,
 324	.read		= seq_read,
 325	.llseek		= seq_lseek,
 326	.release	= single_release,
 327};
 328
 329static void atmci_show_status_reg(struct seq_file *s,
 330		const char *regname, u32 value)
 331{
 332	static const char	*sr_bit[] = {
 333		[0]	= "CMDRDY",
 334		[1]	= "RXRDY",
 335		[2]	= "TXRDY",
 336		[3]	= "BLKE",
 337		[4]	= "DTIP",
 338		[5]	= "NOTBUSY",
 339		[6]	= "ENDRX",
 340		[7]	= "ENDTX",
 341		[8]	= "SDIOIRQA",
 342		[9]	= "SDIOIRQB",
 343		[12]	= "SDIOWAIT",
 344		[14]	= "RXBUFF",
 345		[15]	= "TXBUFE",
 346		[16]	= "RINDE",
 347		[17]	= "RDIRE",
 348		[18]	= "RCRCE",
 349		[19]	= "RENDE",
 350		[20]	= "RTOE",
 351		[21]	= "DCRCE",
 352		[22]	= "DTOE",
 353		[23]	= "CSTOE",
 354		[24]	= "BLKOVRE",
 355		[25]	= "DMADONE",
 356		[26]	= "FIFOEMPTY",
 357		[27]	= "XFRDONE",
 358		[30]	= "OVRE",
 359		[31]	= "UNRE",
 360	};
 361	unsigned int		i;
 362
 363	seq_printf(s, "%s:\t0x%08x", regname, value);
 364	for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
 365		if (value & (1 << i)) {
 366			if (sr_bit[i])
 367				seq_printf(s, " %s", sr_bit[i]);
 368			else
 369				seq_puts(s, " UNKNOWN");
 370		}
 371	}
 372	seq_putc(s, '\n');
 373}
 374
 375static int atmci_regs_show(struct seq_file *s, void *v)
 376{
 377	struct atmel_mci	*host = s->private;
 378	u32			*buf;
 
 
 379
 380	buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
 381	if (!buf)
 382		return -ENOMEM;
 383
 
 
 384	/*
 385	 * Grab a more or less consistent snapshot. Note that we're
 386	 * not disabling interrupts, so IMR and SR may not be
 387	 * consistent.
 388	 */
 389	spin_lock_bh(&host->lock);
 390	clk_enable(host->mck);
 391	memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
 392	clk_disable(host->mck);
 393	spin_unlock_bh(&host->lock);
 394
 395	seq_printf(s, "MR:\t0x%08x%s%s CLKDIV=%u\n",
 
 
 
 396			buf[ATMCI_MR / 4],
 397			buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
 398			buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "",
 399			buf[ATMCI_MR / 4] & 0xff);
 
 
 
 
 
 
 400	seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
 401	seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
 402	seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
 403	seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
 404			buf[ATMCI_BLKR / 4],
 405			buf[ATMCI_BLKR / 4] & 0xffff,
 406			(buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
 407	if (host->caps.has_cstor_reg)
 408		seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
 409
 410	/* Don't read RSPR and RDR; it will consume the data there */
 411
 412	atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
 413	atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
 414
 415	if (host->caps.has_dma) {
 416		u32 val;
 417
 418		val = buf[ATMCI_DMA / 4];
 419		seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
 420				val, val & 3,
 421				((val >> 4) & 3) ?
 422					1 << (((val >> 4) & 3) + 1) : 1,
 423				val & ATMCI_DMAEN ? " DMAEN" : "");
 424	}
 425	if (host->caps.has_cfg_reg) {
 426		u32 val;
 427
 428		val = buf[ATMCI_CFG / 4];
 429		seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
 430				val,
 431				val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
 432				val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
 433				val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
 434				val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
 435	}
 436
 437	kfree(buf);
 438
 439	return 0;
 440}
 441
 442static int atmci_regs_open(struct inode *inode, struct file *file)
 443{
 444	return single_open(file, atmci_regs_show, inode->i_private);
 445}
 446
 447static const struct file_operations atmci_regs_fops = {
 448	.owner		= THIS_MODULE,
 449	.open		= atmci_regs_open,
 450	.read		= seq_read,
 451	.llseek		= seq_lseek,
 452	.release	= single_release,
 453};
 454
 455static void atmci_init_debugfs(struct atmel_mci_slot *slot)
 456{
 457	struct mmc_host		*mmc = slot->mmc;
 458	struct atmel_mci	*host = slot->host;
 459	struct dentry		*root;
 460	struct dentry		*node;
 461
 462	root = mmc->debugfs_root;
 463	if (!root)
 464		return;
 465
 466	node = debugfs_create_file("regs", S_IRUSR, root, host,
 467			&atmci_regs_fops);
 468	if (IS_ERR(node))
 469		return;
 470	if (!node)
 471		goto err;
 
 
 472
 473	node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
 474	if (!node)
 475		goto err;
 476
 477	node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 478	if (!node)
 479		goto err;
 480
 481	node = debugfs_create_x32("pending_events", S_IRUSR, root,
 482				     (u32 *)&host->pending_events);
 483	if (!node)
 484		goto err;
 485
 486	node = debugfs_create_x32("completed_events", S_IRUSR, root,
 487				     (u32 *)&host->completed_events);
 488	if (!node)
 489		goto err;
 490
 491	return;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 492
 493err:
 494	dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 
 
 
 
 
 495}
 
 496
 497static inline unsigned int atmci_get_version(struct atmel_mci *host)
 498{
 499	return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
 500}
 501
 502static void atmci_timeout_timer(unsigned long data)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 503{
 504	struct atmel_mci *host;
 505
 506	host = (struct atmel_mci *)data;
 507
 508	dev_dbg(&host->pdev->dev, "software timeout\n");
 509
 510	if (host->mrq->cmd->data) {
 511		host->mrq->cmd->data->error = -ETIMEDOUT;
 512		host->data = NULL;
 
 
 
 
 
 
 
 513	} else {
 514		host->mrq->cmd->error = -ETIMEDOUT;
 515		host->cmd = NULL;
 516	}
 517	host->need_reset = 1;
 518	host->state = STATE_END_REQUEST;
 519	smp_wmb();
 520	tasklet_schedule(&host->tasklet);
 521}
 522
 523static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
 524					unsigned int ns)
 525{
 526	/*
 527	 * It is easier here to use us instead of ns for the timeout,
 528	 * it prevents from overflows during calculation.
 529	 */
 530	unsigned int us = DIV_ROUND_UP(ns, 1000);
 531
 532	/* Maximum clock frequency is host->bus_hz/2 */
 533	return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
 534}
 535
 536static void atmci_set_timeout(struct atmel_mci *host,
 537		struct atmel_mci_slot *slot, struct mmc_data *data)
 538{
 539	static unsigned	dtomul_to_shift[] = {
 540		0, 4, 7, 8, 10, 12, 16, 20
 541	};
 542	unsigned	timeout;
 543	unsigned	dtocyc;
 544	unsigned	dtomul;
 545
 546	timeout = atmci_ns_to_clocks(host, data->timeout_ns)
 547		+ data->timeout_clks;
 548
 549	for (dtomul = 0; dtomul < 8; dtomul++) {
 550		unsigned shift = dtomul_to_shift[dtomul];
 551		dtocyc = (timeout + (1 << shift) - 1) >> shift;
 552		if (dtocyc < 15)
 553			break;
 554	}
 555
 556	if (dtomul >= 8) {
 557		dtomul = 7;
 558		dtocyc = 15;
 559	}
 560
 561	dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
 562			dtocyc << dtomul_to_shift[dtomul]);
 563	atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
 564}
 565
 566/*
 567 * Return mask with command flags to be enabled for this command.
 568 */
 569static u32 atmci_prepare_command(struct mmc_host *mmc,
 570				 struct mmc_command *cmd)
 571{
 572	struct mmc_data	*data;
 573	u32		cmdr;
 574
 575	cmd->error = -EINPROGRESS;
 576
 577	cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
 578
 579	if (cmd->flags & MMC_RSP_PRESENT) {
 580		if (cmd->flags & MMC_RSP_136)
 581			cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
 582		else
 583			cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
 584	}
 585
 586	/*
 587	 * This should really be MAXLAT_5 for CMD2 and ACMD41, but
 588	 * it's too difficult to determine whether this is an ACMD or
 589	 * not. Better make it 64.
 590	 */
 591	cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
 592
 593	if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
 594		cmdr |= ATMCI_CMDR_OPDCMD;
 595
 596	data = cmd->data;
 597	if (data) {
 598		cmdr |= ATMCI_CMDR_START_XFER;
 599
 600		if (cmd->opcode == SD_IO_RW_EXTENDED) {
 601			cmdr |= ATMCI_CMDR_SDIO_BLOCK;
 602		} else {
 603			if (data->flags & MMC_DATA_STREAM)
 604				cmdr |= ATMCI_CMDR_STREAM;
 605			else if (data->blocks > 1)
 606				cmdr |= ATMCI_CMDR_MULTI_BLOCK;
 607			else
 608				cmdr |= ATMCI_CMDR_BLOCK;
 609		}
 610
 611		if (data->flags & MMC_DATA_READ)
 612			cmdr |= ATMCI_CMDR_TRDIR_READ;
 613	}
 614
 615	return cmdr;
 616}
 617
 618static void atmci_send_command(struct atmel_mci *host,
 619		struct mmc_command *cmd, u32 cmd_flags)
 620{
 621	WARN_ON(host->cmd);
 622	host->cmd = cmd;
 623
 624	dev_vdbg(&host->pdev->dev,
 625			"start command: ARGR=0x%08x CMDR=0x%08x\n",
 626			cmd->arg, cmd_flags);
 627
 628	atmci_writel(host, ATMCI_ARGR, cmd->arg);
 629	atmci_writel(host, ATMCI_CMDR, cmd_flags);
 630}
 631
 632static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
 633{
 634	dev_dbg(&host->pdev->dev, "send stop command\n");
 635	atmci_send_command(host, data->stop, host->stop_cmdr);
 636	atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
 637}
 638
 639/*
 640 * Configure given PDC buffer taking care of alignement issues.
 641 * Update host->data_size and host->sg.
 642 */
 643static void atmci_pdc_set_single_buf(struct atmel_mci *host,
 644	enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
 645{
 646	u32 pointer_reg, counter_reg;
 647	unsigned int buf_size;
 648
 649	if (dir == XFER_RECEIVE) {
 650		pointer_reg = ATMEL_PDC_RPR;
 651		counter_reg = ATMEL_PDC_RCR;
 652	} else {
 653		pointer_reg = ATMEL_PDC_TPR;
 654		counter_reg = ATMEL_PDC_TCR;
 655	}
 656
 657	if (buf_nb == PDC_SECOND_BUF) {
 658		pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
 659		counter_reg += ATMEL_PDC_SCND_BUF_OFF;
 660	}
 661
 662	if (!host->caps.has_rwproof) {
 663		buf_size = host->buf_size;
 664		atmci_writel(host, pointer_reg, host->buf_phys_addr);
 665	} else {
 666		buf_size = sg_dma_len(host->sg);
 667		atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
 668	}
 669
 670	if (host->data_size <= buf_size) {
 671		if (host->data_size & 0x3) {
 672			/* If size is different from modulo 4, transfer bytes */
 673			atmci_writel(host, counter_reg, host->data_size);
 674			atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
 675		} else {
 676			/* Else transfer 32-bits words */
 677			atmci_writel(host, counter_reg, host->data_size / 4);
 678		}
 679		host->data_size = 0;
 680	} else {
 681		/* We assume the size of a page is 32-bits aligned */
 682		atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
 683		host->data_size -= sg_dma_len(host->sg);
 684		if (host->data_size)
 685			host->sg = sg_next(host->sg);
 686	}
 687}
 688
 689/*
 690 * Configure PDC buffer according to the data size ie configuring one or two
 691 * buffers. Don't use this function if you want to configure only the second
 692 * buffer. In this case, use atmci_pdc_set_single_buf.
 693 */
 694static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
 695{
 696	atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
 697	if (host->data_size)
 698		atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
 699}
 700
 701/*
 702 * Unmap sg lists, called when transfer is finished.
 703 */
 704static void atmci_pdc_cleanup(struct atmel_mci *host)
 705{
 706	struct mmc_data         *data = host->data;
 707
 708	if (data)
 709		dma_unmap_sg(&host->pdev->dev,
 710				data->sg, data->sg_len,
 711				((data->flags & MMC_DATA_WRITE)
 712				 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
 713}
 714
 715/*
 716 * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
 717 * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
 718 * interrupt needed for both transfer directions.
 719 */
 720static void atmci_pdc_complete(struct atmel_mci *host)
 721{
 722	int transfer_size = host->data->blocks * host->data->blksz;
 723	int i;
 724
 725	atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
 726
 727	if ((!host->caps.has_rwproof)
 728	    && (host->data->flags & MMC_DATA_READ)) {
 729		if (host->caps.has_bad_data_ordering)
 730			for (i = 0; i < transfer_size; i++)
 731				host->buffer[i] = swab32(host->buffer[i]);
 732		sg_copy_from_buffer(host->data->sg, host->data->sg_len,
 733		                    host->buffer, transfer_size);
 734	}
 735
 736	atmci_pdc_cleanup(host);
 737
 738	/*
 739	 * If the card was removed, data will be NULL. No point trying
 740	 * to send the stop command or waiting for NBUSY in this case.
 741	 */
 742	if (host->data) {
 743		dev_dbg(&host->pdev->dev,
 744		        "(%s) set pending xfer complete\n", __func__);
 745		atmci_set_pending(host, EVENT_XFER_COMPLETE);
 746		tasklet_schedule(&host->tasklet);
 747	}
 748}
 749
 750static void atmci_dma_cleanup(struct atmel_mci *host)
 751{
 752	struct mmc_data                 *data = host->data;
 753
 754	if (data)
 755		dma_unmap_sg(host->dma.chan->device->dev,
 756				data->sg, data->sg_len,
 757				((data->flags & MMC_DATA_WRITE)
 758				 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
 759}
 760
 761/*
 762 * This function is called by the DMA driver from tasklet context.
 763 */
 764static void atmci_dma_complete(void *arg)
 765{
 766	struct atmel_mci	*host = arg;
 767	struct mmc_data		*data = host->data;
 768
 769	dev_vdbg(&host->pdev->dev, "DMA complete\n");
 770
 771	if (host->caps.has_dma)
 772		/* Disable DMA hardware handshaking on MCI */
 773		atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
 774
 775	atmci_dma_cleanup(host);
 776
 777	/*
 778	 * If the card was removed, data will be NULL. No point trying
 779	 * to send the stop command or waiting for NBUSY in this case.
 780	 */
 781	if (data) {
 782		dev_dbg(&host->pdev->dev,
 783		        "(%s) set pending xfer complete\n", __func__);
 784		atmci_set_pending(host, EVENT_XFER_COMPLETE);
 785		tasklet_schedule(&host->tasklet);
 786
 787		/*
 788		 * Regardless of what the documentation says, we have
 789		 * to wait for NOTBUSY even after block read
 790		 * operations.
 791		 *
 792		 * When the DMA transfer is complete, the controller
 793		 * may still be reading the CRC from the card, i.e.
 794		 * the data transfer is still in progress and we
 795		 * haven't seen all the potential error bits yet.
 796		 *
 797		 * The interrupt handler will schedule a different
 798		 * tasklet to finish things up when the data transfer
 799		 * is completely done.
 800		 *
 801		 * We may not complete the mmc request here anyway
 802		 * because the mmc layer may call back and cause us to
 803		 * violate the "don't submit new operations from the
 804		 * completion callback" rule of the dma engine
 805		 * framework.
 806		 */
 807		atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
 808	}
 809}
 810
 811/*
 812 * Returns a mask of interrupt flags to be enabled after the whole
 813 * request has been prepared.
 814 */
 815static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
 816{
 817	u32 iflags;
 818
 819	data->error = -EINPROGRESS;
 820
 821	host->sg = data->sg;
 
 822	host->data = data;
 823	host->data_chan = NULL;
 824
 825	iflags = ATMCI_DATA_ERROR_FLAGS;
 826
 827	/*
 828	 * Errata: MMC data write operation with less than 12
 829	 * bytes is impossible.
 830	 *
 831	 * Errata: MCI Transmit Data Register (TDR) FIFO
 832	 * corruption when length is not multiple of 4.
 833	 */
 834	if (data->blocks * data->blksz < 12
 835			|| (data->blocks * data->blksz) & 3)
 836		host->need_reset = true;
 837
 838	host->pio_offset = 0;
 839	if (data->flags & MMC_DATA_READ)
 840		iflags |= ATMCI_RXRDY;
 841	else
 842		iflags |= ATMCI_TXRDY;
 843
 844	return iflags;
 845}
 846
 847/*
 848 * Set interrupt flags and set block length into the MCI mode register even
 849 * if this value is also accessible in the MCI block register. It seems to be
 850 * necessary before the High Speed MCI version. It also map sg and configure
 851 * PDC registers.
 852 */
 853static u32
 854atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
 855{
 856	u32 iflags, tmp;
 857	unsigned int sg_len;
 858	enum dma_data_direction dir;
 859	int i;
 860
 861	data->error = -EINPROGRESS;
 862
 863	host->data = data;
 864	host->sg = data->sg;
 865	iflags = ATMCI_DATA_ERROR_FLAGS;
 866
 867	/* Enable pdc mode */
 868	atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
 869
 870	if (data->flags & MMC_DATA_READ) {
 871		dir = DMA_FROM_DEVICE;
 872		iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
 873	} else {
 874		dir = DMA_TO_DEVICE;
 875		iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE;
 876	}
 877
 878	/* Set BLKLEN */
 879	tmp = atmci_readl(host, ATMCI_MR);
 880	tmp &= 0x0000ffff;
 881	tmp |= ATMCI_BLKLEN(data->blksz);
 882	atmci_writel(host, ATMCI_MR, tmp);
 883
 884	/* Configure PDC */
 885	host->data_size = data->blocks * data->blksz;
 886	sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, dir);
 
 887
 888	if ((!host->caps.has_rwproof)
 889	    && (host->data->flags & MMC_DATA_WRITE)) {
 890		sg_copy_to_buffer(host->data->sg, host->data->sg_len,
 891		                  host->buffer, host->data_size);
 892		if (host->caps.has_bad_data_ordering)
 893			for (i = 0; i < host->data_size; i++)
 894				host->buffer[i] = swab32(host->buffer[i]);
 895	}
 896
 897	if (host->data_size)
 898		atmci_pdc_set_both_buf(host,
 899			((dir == DMA_FROM_DEVICE) ? XFER_RECEIVE : XFER_TRANSMIT));
 900
 901	return iflags;
 902}
 903
 904static u32
 905atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
 906{
 907	struct dma_chan			*chan;
 908	struct dma_async_tx_descriptor	*desc;
 909	struct scatterlist		*sg;
 910	unsigned int			i;
 911	enum dma_data_direction		direction;
 912	enum dma_transfer_direction	slave_dirn;
 913	unsigned int			sglen;
 914	u32				maxburst;
 915	u32 iflags;
 916
 917	data->error = -EINPROGRESS;
 918
 919	WARN_ON(host->data);
 920	host->sg = NULL;
 921	host->data = data;
 922
 923	iflags = ATMCI_DATA_ERROR_FLAGS;
 924
 925	/*
 926	 * We don't do DMA on "complex" transfers, i.e. with
 927	 * non-word-aligned buffers or lengths. Also, we don't bother
 928	 * with all the DMA setup overhead for short transfers.
 929	 */
 930	if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
 931		return atmci_prepare_data(host, data);
 932	if (data->blksz & 3)
 933		return atmci_prepare_data(host, data);
 934
 935	for_each_sg(data->sg, sg, data->sg_len, i) {
 936		if (sg->offset & 3 || sg->length & 3)
 937			return atmci_prepare_data(host, data);
 938	}
 939
 940	/* If we don't have a channel, we can't do DMA */
 941	chan = host->dma.chan;
 942	if (chan)
 943		host->data_chan = chan;
 944
 945	if (!chan)
 946		return -ENODEV;
 947
 948	if (data->flags & MMC_DATA_READ) {
 949		direction = DMA_FROM_DEVICE;
 950		host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
 951		maxburst = atmci_convert_chksize(host->dma_conf.src_maxburst);
 
 952	} else {
 953		direction = DMA_TO_DEVICE;
 954		host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
 955		maxburst = atmci_convert_chksize(host->dma_conf.dst_maxburst);
 
 956	}
 957
 958	atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) | ATMCI_DMAEN);
 
 
 959
 960	sglen = dma_map_sg(chan->device->dev, data->sg,
 961			data->sg_len, direction);
 962
 963	dmaengine_slave_config(chan, &host->dma_conf);
 964	desc = dmaengine_prep_slave_sg(chan,
 965			data->sg, sglen, slave_dirn,
 966			DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 967	if (!desc)
 968		goto unmap_exit;
 969
 970	host->dma.data_desc = desc;
 971	desc->callback = atmci_dma_complete;
 972	desc->callback_param = host;
 973
 974	return iflags;
 975unmap_exit:
 976	dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, direction);
 
 977	return -ENOMEM;
 978}
 979
 980static void
 981atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
 982{
 983	return;
 984}
 985
 986/*
 987 * Start PDC according to transfer direction.
 988 */
 989static void
 990atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
 991{
 992	if (data->flags & MMC_DATA_READ)
 993		atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
 994	else
 995		atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
 996}
 997
 998static void
 999atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
1000{
1001	struct dma_chan			*chan = host->data_chan;
1002	struct dma_async_tx_descriptor	*desc = host->dma.data_desc;
1003
1004	if (chan) {
1005		dmaengine_submit(desc);
1006		dma_async_issue_pending(chan);
1007	}
1008}
1009
1010static void atmci_stop_transfer(struct atmel_mci *host)
1011{
1012	dev_dbg(&host->pdev->dev,
1013	        "(%s) set pending xfer complete\n", __func__);
1014	atmci_set_pending(host, EVENT_XFER_COMPLETE);
1015	atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1016}
1017
1018/*
1019 * Stop data transfer because error(s) occured.
1020 */
1021static void atmci_stop_transfer_pdc(struct atmel_mci *host)
1022{
1023	atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
1024}
1025
1026static void atmci_stop_transfer_dma(struct atmel_mci *host)
1027{
1028	struct dma_chan *chan = host->data_chan;
1029
1030	if (chan) {
1031		dmaengine_terminate_all(chan);
1032		atmci_dma_cleanup(host);
1033	} else {
1034		/* Data transfer was stopped by the interrupt handler */
1035		dev_dbg(&host->pdev->dev,
1036		        "(%s) set pending xfer complete\n", __func__);
1037		atmci_set_pending(host, EVENT_XFER_COMPLETE);
1038		atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1039	}
1040}
1041
1042/*
1043 * Start a request: prepare data if needed, prepare the command and activate
1044 * interrupts.
1045 */
1046static void atmci_start_request(struct atmel_mci *host,
1047		struct atmel_mci_slot *slot)
1048{
1049	struct mmc_request	*mrq;
1050	struct mmc_command	*cmd;
1051	struct mmc_data		*data;
1052	u32			iflags;
1053	u32			cmdflags;
1054
1055	mrq = slot->mrq;
1056	host->cur_slot = slot;
1057	host->mrq = mrq;
1058
1059	host->pending_events = 0;
1060	host->completed_events = 0;
1061	host->cmd_status = 0;
1062	host->data_status = 0;
1063
1064	dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode);
1065
1066	if (host->need_reset || host->caps.need_reset_after_xfer) {
1067		iflags = atmci_readl(host, ATMCI_IMR);
1068		iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
1069		atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1070		atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1071		atmci_writel(host, ATMCI_MR, host->mode_reg);
1072		if (host->caps.has_cfg_reg)
1073			atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1074		atmci_writel(host, ATMCI_IER, iflags);
1075		host->need_reset = false;
1076	}
1077	atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
1078
1079	iflags = atmci_readl(host, ATMCI_IMR);
1080	if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
1081		dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
1082				iflags);
1083
1084	if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
1085		/* Send init sequence (74 clock cycles) */
1086		atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
1087		while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
1088			cpu_relax();
1089	}
1090	iflags = 0;
1091	data = mrq->data;
1092	if (data) {
1093		atmci_set_timeout(host, slot, data);
1094
1095		/* Must set block count/size before sending command */
1096		atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
1097				| ATMCI_BLKLEN(data->blksz));
1098		dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
1099			ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
1100
1101		iflags |= host->prepare_data(host, data);
1102	}
1103
1104	iflags |= ATMCI_CMDRDY;
1105	cmd = mrq->cmd;
1106	cmdflags = atmci_prepare_command(slot->mmc, cmd);
1107	atmci_send_command(host, cmd, cmdflags);
 
 
 
 
 
 
 
 
1108
1109	if (data)
1110		host->submit_data(host, data);
1111
 
 
 
1112	if (mrq->stop) {
1113		host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
1114		host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
1115		if (!(data->flags & MMC_DATA_WRITE))
1116			host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
1117		if (data->flags & MMC_DATA_STREAM)
1118			host->stop_cmdr |= ATMCI_CMDR_STREAM;
1119		else
1120			host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
1121	}
1122
1123	/*
1124	 * We could have enabled interrupts earlier, but I suspect
1125	 * that would open up a nice can of interesting race
1126	 * conditions (e.g. command and data complete, but stop not
1127	 * prepared yet.)
1128	 */
1129	atmci_writel(host, ATMCI_IER, iflags);
1130
1131	mod_timer(&host->timer, jiffies +  msecs_to_jiffies(2000));
1132}
1133
1134static void atmci_queue_request(struct atmel_mci *host,
1135		struct atmel_mci_slot *slot, struct mmc_request *mrq)
1136{
1137	dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1138			host->state);
1139
1140	spin_lock_bh(&host->lock);
1141	slot->mrq = mrq;
1142	if (host->state == STATE_IDLE) {
1143		host->state = STATE_SENDING_CMD;
1144		atmci_start_request(host, slot);
1145	} else {
1146		dev_dbg(&host->pdev->dev, "queue request\n");
1147		list_add_tail(&slot->queue_node, &host->queue);
1148	}
1149	spin_unlock_bh(&host->lock);
1150}
1151
1152static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1153{
1154	struct atmel_mci_slot	*slot = mmc_priv(mmc);
1155	struct atmel_mci	*host = slot->host;
1156	struct mmc_data		*data;
1157
1158	WARN_ON(slot->mrq);
1159	dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode);
1160
1161	/*
1162	 * We may "know" the card is gone even though there's still an
1163	 * electrical connection. If so, we really need to communicate
1164	 * this to the MMC core since there won't be any more
1165	 * interrupts as the card is completely removed. Otherwise,
1166	 * the MMC core might believe the card is still there even
1167	 * though the card was just removed very slowly.
1168	 */
1169	if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
1170		mrq->cmd->error = -ENOMEDIUM;
1171		mmc_request_done(mmc, mrq);
1172		return;
1173	}
1174
1175	/* We don't support multiple blocks of weird lengths. */
1176	data = mrq->data;
1177	if (data && data->blocks > 1 && data->blksz & 3) {
1178		mrq->cmd->error = -EINVAL;
1179		mmc_request_done(mmc, mrq);
1180	}
1181
1182	atmci_queue_request(host, slot, mrq);
1183}
1184
1185static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1186{
1187	struct atmel_mci_slot	*slot = mmc_priv(mmc);
1188	struct atmel_mci	*host = slot->host;
1189	unsigned int		i;
1190
1191	slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
1192	switch (ios->bus_width) {
1193	case MMC_BUS_WIDTH_1:
1194		slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
1195		break;
1196	case MMC_BUS_WIDTH_4:
1197		slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
1198		break;
 
 
 
1199	}
1200
1201	if (ios->clock) {
1202		unsigned int clock_min = ~0U;
1203		u32 clkdiv;
1204
1205		spin_lock_bh(&host->lock);
1206		if (!host->mode_reg) {
1207			clk_enable(host->mck);
1208			atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1209			atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1210			if (host->caps.has_cfg_reg)
1211				atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1212		}
1213
1214		/*
1215		 * Use mirror of ios->clock to prevent race with mmc
1216		 * core ios update when finding the minimum.
1217		 */
1218		slot->clock = ios->clock;
1219		for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1220			if (host->slot[i] && host->slot[i]->clock
1221					&& host->slot[i]->clock < clock_min)
1222				clock_min = host->slot[i]->clock;
1223		}
1224
1225		/* Calculate clock divider */
1226		if (host->caps.has_odd_clk_div) {
1227			clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
1228			if (clkdiv > 511) {
 
 
 
 
 
1229				dev_warn(&mmc->class_dev,
1230				         "clock %u too slow; using %lu\n",
1231				         clock_min, host->bus_hz / (511 + 2));
1232				clkdiv = 511;
1233			}
1234			host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
1235			                 | ATMCI_MR_CLKODD(clkdiv & 1);
1236		} else {
1237			clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
1238			if (clkdiv > 255) {
1239				dev_warn(&mmc->class_dev,
1240				         "clock %u too slow; using %lu\n",
1241				         clock_min, host->bus_hz / (2 * 256));
1242				clkdiv = 255;
1243			}
1244			host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
1245		}
1246
1247		/*
1248		 * WRPROOF and RDPROOF prevent overruns/underruns by
1249		 * stopping the clock when the FIFO is full/empty.
1250		 * This state is not expected to last for long.
1251		 */
1252		if (host->caps.has_rwproof)
1253			host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
1254
1255		if (host->caps.has_cfg_reg) {
1256			/* setup High Speed mode in relation with card capacity */
1257			if (ios->timing == MMC_TIMING_SD_HS)
1258				host->cfg_reg |= ATMCI_CFG_HSMODE;
1259			else
1260				host->cfg_reg &= ~ATMCI_CFG_HSMODE;
1261		}
1262
1263		if (list_empty(&host->queue)) {
1264			atmci_writel(host, ATMCI_MR, host->mode_reg);
1265			if (host->caps.has_cfg_reg)
1266				atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1267		} else {
1268			host->need_clock_update = true;
1269		}
1270
1271		spin_unlock_bh(&host->lock);
1272	} else {
1273		bool any_slot_active = false;
1274
1275		spin_lock_bh(&host->lock);
1276		slot->clock = 0;
1277		for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1278			if (host->slot[i] && host->slot[i]->clock) {
1279				any_slot_active = true;
1280				break;
1281			}
1282		}
1283		if (!any_slot_active) {
1284			atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
1285			if (host->mode_reg) {
1286				atmci_readl(host, ATMCI_MR);
1287				clk_disable(host->mck);
1288			}
1289			host->mode_reg = 0;
1290		}
1291		spin_unlock_bh(&host->lock);
1292	}
1293
1294	switch (ios->power_mode) {
 
 
 
 
1295	case MMC_POWER_UP:
1296		set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
 
 
1297		break;
1298	default:
1299		/*
1300		 * TODO: None of the currently available AVR32-based
1301		 * boards allow MMC power to be turned off. Implement
1302		 * power control when this can be tested properly.
1303		 *
1304		 * We also need to hook this into the clock management
1305		 * somehow so that newly inserted cards aren't
1306		 * subjected to a fast clock before we have a chance
1307		 * to figure out what the maximum rate is. Currently,
1308		 * there's no way to avoid this, and there never will
1309		 * be for boards that don't support power control.
1310		 */
1311		break;
1312	}
1313}
1314
1315static int atmci_get_ro(struct mmc_host *mmc)
1316{
1317	int			read_only = -ENOSYS;
1318	struct atmel_mci_slot	*slot = mmc_priv(mmc);
1319
1320	if (gpio_is_valid(slot->wp_pin)) {
1321		read_only = gpio_get_value(slot->wp_pin);
1322		dev_dbg(&mmc->class_dev, "card is %s\n",
1323				read_only ? "read-only" : "read-write");
1324	}
1325
1326	return read_only;
1327}
1328
1329static int atmci_get_cd(struct mmc_host *mmc)
1330{
1331	int			present = -ENOSYS;
1332	struct atmel_mci_slot	*slot = mmc_priv(mmc);
1333
1334	if (gpio_is_valid(slot->detect_pin)) {
1335		present = !(gpio_get_value(slot->detect_pin) ^
1336			    slot->detect_is_active_high);
1337		dev_dbg(&mmc->class_dev, "card is %spresent\n",
1338				present ? "" : "not ");
1339	}
1340
1341	return present;
1342}
1343
1344static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1345{
1346	struct atmel_mci_slot	*slot = mmc_priv(mmc);
1347	struct atmel_mci	*host = slot->host;
1348
1349	if (enable)
1350		atmci_writel(host, ATMCI_IER, slot->sdio_irq);
1351	else
1352		atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
1353}
1354
1355static const struct mmc_host_ops atmci_ops = {
1356	.request	= atmci_request,
1357	.set_ios	= atmci_set_ios,
1358	.get_ro		= atmci_get_ro,
1359	.get_cd		= atmci_get_cd,
1360	.enable_sdio_irq = atmci_enable_sdio_irq,
1361};
1362
1363/* Called with host->lock held */
1364static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1365	__releases(&host->lock)
1366	__acquires(&host->lock)
1367{
1368	struct atmel_mci_slot	*slot = NULL;
1369	struct mmc_host		*prev_mmc = host->cur_slot->mmc;
1370
1371	WARN_ON(host->cmd || host->data);
1372
1373	/*
1374	 * Update the MMC clock rate if necessary. This may be
1375	 * necessary if set_ios() is called when a different slot is
1376	 * busy transferring data.
1377	 */
1378	if (host->need_clock_update) {
1379		atmci_writel(host, ATMCI_MR, host->mode_reg);
1380		if (host->caps.has_cfg_reg)
1381			atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1382	}
1383
1384	host->cur_slot->mrq = NULL;
1385	host->mrq = NULL;
1386	if (!list_empty(&host->queue)) {
1387		slot = list_entry(host->queue.next,
1388				struct atmel_mci_slot, queue_node);
1389		list_del(&slot->queue_node);
1390		dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1391				mmc_hostname(slot->mmc));
1392		host->state = STATE_SENDING_CMD;
1393		atmci_start_request(host, slot);
1394	} else {
1395		dev_vdbg(&host->pdev->dev, "list empty\n");
1396		host->state = STATE_IDLE;
1397	}
1398
1399	del_timer(&host->timer);
1400
1401	spin_unlock(&host->lock);
1402	mmc_request_done(prev_mmc, mrq);
1403	spin_lock(&host->lock);
1404}
1405
1406static void atmci_command_complete(struct atmel_mci *host,
1407			struct mmc_command *cmd)
1408{
1409	u32		status = host->cmd_status;
1410
1411	/* Read the response from the card (up to 16 bytes) */
1412	cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
1413	cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
1414	cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
1415	cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
1416
1417	if (status & ATMCI_RTOE)
1418		cmd->error = -ETIMEDOUT;
1419	else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
1420		cmd->error = -EILSEQ;
1421	else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
1422		cmd->error = -EIO;
1423	else if (host->mrq->data && (host->mrq->data->blksz & 3)) {
1424		if (host->caps.need_blksz_mul_4) {
1425			cmd->error = -EINVAL;
1426			host->need_reset = 1;
1427		}
1428	} else
1429		cmd->error = 0;
1430}
1431
1432static void atmci_detect_change(unsigned long data)
1433{
1434	struct atmel_mci_slot	*slot = (struct atmel_mci_slot *)data;
1435	bool			present;
1436	bool			present_old;
1437
1438	/*
1439	 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1440	 * freeing the interrupt. We must not re-enable the interrupt
1441	 * if it has been freed, and if we're shutting down, it
1442	 * doesn't really matter whether the card is present or not.
1443	 */
1444	smp_rmb();
1445	if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
1446		return;
1447
1448	enable_irq(gpio_to_irq(slot->detect_pin));
1449	present = !(gpio_get_value(slot->detect_pin) ^
1450		    slot->detect_is_active_high);
1451	present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
1452
1453	dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1454			present, present_old);
1455
1456	if (present != present_old) {
1457		struct atmel_mci	*host = slot->host;
1458		struct mmc_request	*mrq;
1459
1460		dev_dbg(&slot->mmc->class_dev, "card %s\n",
1461			present ? "inserted" : "removed");
1462
1463		spin_lock(&host->lock);
1464
1465		if (!present)
1466			clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1467		else
1468			set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1469
1470		/* Clean up queue if present */
1471		mrq = slot->mrq;
1472		if (mrq) {
1473			if (mrq == host->mrq) {
1474				/*
1475				 * Reset controller to terminate any ongoing
1476				 * commands or data transfers.
1477				 */
1478				atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1479				atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1480				atmci_writel(host, ATMCI_MR, host->mode_reg);
1481				if (host->caps.has_cfg_reg)
1482					atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1483
1484				host->data = NULL;
1485				host->cmd = NULL;
1486
1487				switch (host->state) {
1488				case STATE_IDLE:
1489					break;
1490				case STATE_SENDING_CMD:
1491					mrq->cmd->error = -ENOMEDIUM;
1492					if (mrq->data)
1493						host->stop_transfer(host);
1494					break;
1495				case STATE_DATA_XFER:
1496					mrq->data->error = -ENOMEDIUM;
1497					host->stop_transfer(host);
1498					break;
1499				case STATE_WAITING_NOTBUSY:
1500					mrq->data->error = -ENOMEDIUM;
1501					break;
1502				case STATE_SENDING_STOP:
1503					mrq->stop->error = -ENOMEDIUM;
1504					break;
1505				case STATE_END_REQUEST:
1506					break;
1507				}
1508
1509				atmci_request_end(host, mrq);
1510			} else {
1511				list_del(&slot->queue_node);
1512				mrq->cmd->error = -ENOMEDIUM;
1513				if (mrq->data)
1514					mrq->data->error = -ENOMEDIUM;
1515				if (mrq->stop)
1516					mrq->stop->error = -ENOMEDIUM;
1517
1518				spin_unlock(&host->lock);
1519				mmc_request_done(slot->mmc, mrq);
1520				spin_lock(&host->lock);
1521			}
1522		}
1523		spin_unlock(&host->lock);
1524
1525		mmc_detect_change(slot->mmc, 0);
1526	}
1527}
1528
1529static void atmci_tasklet_func(unsigned long priv)
1530{
1531	struct atmel_mci	*host = (struct atmel_mci *)priv;
1532	struct mmc_request	*mrq = host->mrq;
1533	struct mmc_data		*data = host->data;
1534	enum atmel_mci_state	state = host->state;
1535	enum atmel_mci_state	prev_state;
1536	u32			status;
1537
1538	spin_lock(&host->lock);
1539
1540	state = host->state;
1541
1542	dev_vdbg(&host->pdev->dev,
1543		"tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1544		state, host->pending_events, host->completed_events,
1545		atmci_readl(host, ATMCI_IMR));
1546
1547	do {
1548		prev_state = state;
1549		dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state);
1550
1551		switch (state) {
1552		case STATE_IDLE:
1553			break;
1554
1555		case STATE_SENDING_CMD:
1556			/*
1557			 * Command has been sent, we are waiting for command
1558			 * ready. Then we have three next states possible:
1559			 * END_REQUEST by default, WAITING_NOTBUSY if it's a
1560			 * command needing it or DATA_XFER if there is data.
1561			 */
1562			dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1563			if (!atmci_test_and_clear_pending(host,
1564						EVENT_CMD_RDY))
1565				break;
1566
1567			dev_dbg(&host->pdev->dev, "set completed cmd ready\n");
1568			host->cmd = NULL;
1569			atmci_set_completed(host, EVENT_CMD_RDY);
1570			atmci_command_complete(host, mrq->cmd);
1571			if (mrq->data) {
1572				dev_dbg(&host->pdev->dev,
1573				        "command with data transfer");
1574				/*
1575				 * If there is a command error don't start
1576				 * data transfer.
1577				 */
1578				if (mrq->cmd->error) {
1579					host->stop_transfer(host);
1580					host->data = NULL;
1581					atmci_writel(host, ATMCI_IDR,
1582					             ATMCI_TXRDY | ATMCI_RXRDY
1583					             | ATMCI_DATA_ERROR_FLAGS);
1584					state = STATE_END_REQUEST;
1585				} else
1586					state = STATE_DATA_XFER;
1587			} else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) {
1588				dev_dbg(&host->pdev->dev,
1589				        "command response need waiting notbusy");
1590				atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1591				state = STATE_WAITING_NOTBUSY;
1592			} else
1593				state = STATE_END_REQUEST;
1594
1595			break;
1596
1597		case STATE_DATA_XFER:
1598			if (atmci_test_and_clear_pending(host,
1599						EVENT_DATA_ERROR)) {
1600				dev_dbg(&host->pdev->dev, "set completed data error\n");
1601				atmci_set_completed(host, EVENT_DATA_ERROR);
1602				state = STATE_END_REQUEST;
1603				break;
1604			}
1605
1606			/*
1607			 * A data transfer is in progress. The event expected
1608			 * to move to the next state depends of data transfer
1609			 * type (PDC or DMA). Once transfer done we can move
1610			 * to the next step which is WAITING_NOTBUSY in write
1611			 * case and directly SENDING_STOP in read case.
1612			 */
1613			dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n");
1614			if (!atmci_test_and_clear_pending(host,
1615						EVENT_XFER_COMPLETE))
1616				break;
1617
1618			dev_dbg(&host->pdev->dev,
1619			        "(%s) set completed xfer complete\n",
1620				__func__);
1621			atmci_set_completed(host, EVENT_XFER_COMPLETE);
1622
1623			if (host->caps.need_notbusy_for_read_ops ||
1624			   (host->data->flags & MMC_DATA_WRITE)) {
1625				atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1626				state = STATE_WAITING_NOTBUSY;
1627			} else if (host->mrq->stop) {
1628				atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
1629				atmci_send_stop_cmd(host, data);
1630				state = STATE_SENDING_STOP;
1631			} else {
1632				host->data = NULL;
1633				data->bytes_xfered = data->blocks * data->blksz;
1634				data->error = 0;
1635				state = STATE_END_REQUEST;
1636			}
1637			break;
1638
1639		case STATE_WAITING_NOTBUSY:
1640			/*
1641			 * We can be in the state for two reasons: a command
1642			 * requiring waiting not busy signal (stop command
1643			 * included) or a write operation. In the latest case,
1644			 * we need to send a stop command.
1645			 */
1646			dev_dbg(&host->pdev->dev, "FSM: not busy?\n");
1647			if (!atmci_test_and_clear_pending(host,
1648						EVENT_NOTBUSY))
1649				break;
1650
1651			dev_dbg(&host->pdev->dev, "set completed not busy\n");
1652			atmci_set_completed(host, EVENT_NOTBUSY);
1653
1654			if (host->data) {
1655				/*
1656				 * For some commands such as CMD53, even if
1657				 * there is data transfer, there is no stop
1658				 * command to send.
1659				 */
1660				if (host->mrq->stop) {
1661					atmci_writel(host, ATMCI_IER,
1662					             ATMCI_CMDRDY);
1663					atmci_send_stop_cmd(host, data);
1664					state = STATE_SENDING_STOP;
1665				} else {
1666					host->data = NULL;
1667					data->bytes_xfered = data->blocks
1668					                     * data->blksz;
1669					data->error = 0;
1670					state = STATE_END_REQUEST;
1671				}
1672			} else
1673				state = STATE_END_REQUEST;
1674			break;
1675
1676		case STATE_SENDING_STOP:
1677			/*
1678			 * In this state, it is important to set host->data to
1679			 * NULL (which is tested in the waiting notbusy state)
1680			 * in order to go to the end request state instead of
1681			 * sending stop again.
1682			 */
1683			dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1684			if (!atmci_test_and_clear_pending(host,
1685						EVENT_CMD_RDY))
1686				break;
1687
1688			dev_dbg(&host->pdev->dev, "FSM: cmd ready\n");
1689			host->cmd = NULL;
1690			host->data = NULL;
1691			data->bytes_xfered = data->blocks * data->blksz;
1692			data->error = 0;
1693			atmci_command_complete(host, mrq->stop);
1694			if (mrq->stop->error) {
1695				host->stop_transfer(host);
1696				atmci_writel(host, ATMCI_IDR,
1697				             ATMCI_TXRDY | ATMCI_RXRDY
1698				             | ATMCI_DATA_ERROR_FLAGS);
1699				state = STATE_END_REQUEST;
1700			} else {
1701				atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1702				state = STATE_WAITING_NOTBUSY;
1703			}
 
1704			break;
1705
1706		case STATE_END_REQUEST:
1707			atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY
1708			                   | ATMCI_DATA_ERROR_FLAGS);
1709			status = host->data_status;
1710			if (unlikely(status)) {
1711				host->stop_transfer(host);
1712				host->data = NULL;
1713				if (status & ATMCI_DTOE) {
1714					data->error = -ETIMEDOUT;
1715				} else if (status & ATMCI_DCRCE) {
1716					data->error = -EILSEQ;
1717				} else {
1718					data->error = -EIO;
 
 
1719				}
1720			}
1721
1722			atmci_request_end(host, host->mrq);
1723			state = STATE_IDLE;
1724			break;
1725		}
1726	} while (state != prev_state);
1727
1728	host->state = state;
1729
 
1730	spin_unlock(&host->lock);
1731}
1732
1733static void atmci_read_data_pio(struct atmel_mci *host)
1734{
1735	struct scatterlist	*sg = host->sg;
1736	void			*buf = sg_virt(sg);
1737	unsigned int		offset = host->pio_offset;
1738	struct mmc_data		*data = host->data;
1739	u32			value;
1740	u32			status;
1741	unsigned int		nbytes = 0;
1742
1743	do {
1744		value = atmci_readl(host, ATMCI_RDR);
1745		if (likely(offset + 4 <= sg->length)) {
1746			put_unaligned(value, (u32 *)(buf + offset));
1747
1748			offset += 4;
1749			nbytes += 4;
1750
1751			if (offset == sg->length) {
1752				flush_dcache_page(sg_page(sg));
1753				host->sg = sg = sg_next(sg);
1754				if (!sg)
 
1755					goto done;
1756
1757				offset = 0;
1758				buf = sg_virt(sg);
1759			}
1760		} else {
1761			unsigned int remaining = sg->length - offset;
1762			memcpy(buf + offset, &value, remaining);
 
1763			nbytes += remaining;
1764
1765			flush_dcache_page(sg_page(sg));
1766			host->sg = sg = sg_next(sg);
1767			if (!sg)
 
1768				goto done;
1769
1770			offset = 4 - remaining;
1771			buf = sg_virt(sg);
1772			memcpy(buf, (u8 *)&value + remaining, offset);
1773			nbytes += offset;
1774		}
1775
1776		status = atmci_readl(host, ATMCI_SR);
1777		if (status & ATMCI_DATA_ERROR_FLAGS) {
1778			atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
1779						| ATMCI_DATA_ERROR_FLAGS));
1780			host->data_status = status;
1781			data->bytes_xfered += nbytes;
1782			return;
1783		}
1784	} while (status & ATMCI_RXRDY);
1785
1786	host->pio_offset = offset;
1787	data->bytes_xfered += nbytes;
1788
1789	return;
1790
1791done:
1792	atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
1793	atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1794	data->bytes_xfered += nbytes;
1795	smp_wmb();
1796	atmci_set_pending(host, EVENT_XFER_COMPLETE);
1797}
1798
1799static void atmci_write_data_pio(struct atmel_mci *host)
1800{
1801	struct scatterlist	*sg = host->sg;
1802	void			*buf = sg_virt(sg);
1803	unsigned int		offset = host->pio_offset;
1804	struct mmc_data		*data = host->data;
1805	u32			value;
1806	u32			status;
1807	unsigned int		nbytes = 0;
1808
1809	do {
1810		if (likely(offset + 4 <= sg->length)) {
1811			value = get_unaligned((u32 *)(buf + offset));
1812			atmci_writel(host, ATMCI_TDR, value);
1813
1814			offset += 4;
1815			nbytes += 4;
1816			if (offset == sg->length) {
1817				host->sg = sg = sg_next(sg);
1818				if (!sg)
 
1819					goto done;
1820
1821				offset = 0;
1822				buf = sg_virt(sg);
1823			}
1824		} else {
1825			unsigned int remaining = sg->length - offset;
1826
1827			value = 0;
1828			memcpy(&value, buf + offset, remaining);
1829			nbytes += remaining;
1830
1831			host->sg = sg = sg_next(sg);
1832			if (!sg) {
 
1833				atmci_writel(host, ATMCI_TDR, value);
1834				goto done;
1835			}
1836
1837			offset = 4 - remaining;
1838			buf = sg_virt(sg);
1839			memcpy((u8 *)&value + remaining, buf, offset);
1840			atmci_writel(host, ATMCI_TDR, value);
1841			nbytes += offset;
1842		}
1843
1844		status = atmci_readl(host, ATMCI_SR);
1845		if (status & ATMCI_DATA_ERROR_FLAGS) {
1846			atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
1847						| ATMCI_DATA_ERROR_FLAGS));
1848			host->data_status = status;
1849			data->bytes_xfered += nbytes;
1850			return;
1851		}
1852	} while (status & ATMCI_TXRDY);
1853
1854	host->pio_offset = offset;
1855	data->bytes_xfered += nbytes;
1856
1857	return;
1858
1859done:
1860	atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
1861	atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1862	data->bytes_xfered += nbytes;
1863	smp_wmb();
1864	atmci_set_pending(host, EVENT_XFER_COMPLETE);
1865}
1866
1867static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
1868{
1869	int	i;
1870
1871	for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1872		struct atmel_mci_slot *slot = host->slot[i];
1873		if (slot && (status & slot->sdio_irq)) {
1874			mmc_signal_sdio_irq(slot->mmc);
1875		}
1876	}
1877}
1878
1879
1880static irqreturn_t atmci_interrupt(int irq, void *dev_id)
1881{
1882	struct atmel_mci	*host = dev_id;
1883	u32			status, mask, pending;
1884	unsigned int		pass_count = 0;
1885
1886	do {
1887		status = atmci_readl(host, ATMCI_SR);
1888		mask = atmci_readl(host, ATMCI_IMR);
1889		pending = status & mask;
1890		if (!pending)
1891			break;
1892
1893		if (pending & ATMCI_DATA_ERROR_FLAGS) {
1894			dev_dbg(&host->pdev->dev, "IRQ: data error\n");
1895			atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
1896					| ATMCI_RXRDY | ATMCI_TXRDY
1897					| ATMCI_ENDRX | ATMCI_ENDTX
1898					| ATMCI_RXBUFF | ATMCI_TXBUFE);
1899
1900			host->data_status = status;
1901			dev_dbg(&host->pdev->dev, "set pending data error\n");
1902			smp_wmb();
1903			atmci_set_pending(host, EVENT_DATA_ERROR);
1904			tasklet_schedule(&host->tasklet);
1905		}
1906
1907		if (pending & ATMCI_TXBUFE) {
1908			dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n");
1909			atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
1910			atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
1911			/*
1912			 * We can receive this interruption before having configured
1913			 * the second pdc buffer, so we need to reconfigure first and
1914			 * second buffers again
1915			 */
1916			if (host->data_size) {
1917				atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
1918				atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
1919				atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
1920			} else {
1921				atmci_pdc_complete(host);
1922			}
1923		} else if (pending & ATMCI_ENDTX) {
1924			dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n");
1925			atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
1926
1927			if (host->data_size) {
1928				atmci_pdc_set_single_buf(host,
1929						XFER_TRANSMIT, PDC_SECOND_BUF);
1930				atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
1931			}
1932		}
1933
1934		if (pending & ATMCI_RXBUFF) {
1935			dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n");
1936			atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
1937			atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
1938			/*
1939			 * We can receive this interruption before having configured
1940			 * the second pdc buffer, so we need to reconfigure first and
1941			 * second buffers again
1942			 */
1943			if (host->data_size) {
1944				atmci_pdc_set_both_buf(host, XFER_RECEIVE);
1945				atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
1946				atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
1947			} else {
1948				atmci_pdc_complete(host);
1949			}
1950		} else if (pending & ATMCI_ENDRX) {
1951			dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n");
1952			atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
1953
1954			if (host->data_size) {
1955				atmci_pdc_set_single_buf(host,
1956						XFER_RECEIVE, PDC_SECOND_BUF);
1957				atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
1958			}
1959		}
1960
1961		/*
1962		 * First mci IPs, so mainly the ones having pdc, have some
1963		 * issues with the notbusy signal. You can't get it after
1964		 * data transmission if you have not sent a stop command.
1965		 * The appropriate workaround is to use the BLKE signal.
1966		 */
1967		if (pending & ATMCI_BLKE) {
1968			dev_dbg(&host->pdev->dev, "IRQ: blke\n");
1969			atmci_writel(host, ATMCI_IDR, ATMCI_BLKE);
1970			smp_wmb();
1971			dev_dbg(&host->pdev->dev, "set pending notbusy\n");
1972			atmci_set_pending(host, EVENT_NOTBUSY);
1973			tasklet_schedule(&host->tasklet);
1974		}
1975
1976		if (pending & ATMCI_NOTBUSY) {
1977			dev_dbg(&host->pdev->dev, "IRQ: not_busy\n");
1978			atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY);
1979			smp_wmb();
1980			dev_dbg(&host->pdev->dev, "set pending notbusy\n");
1981			atmci_set_pending(host, EVENT_NOTBUSY);
1982			tasklet_schedule(&host->tasklet);
1983		}
1984
1985		if (pending & ATMCI_RXRDY)
1986			atmci_read_data_pio(host);
1987		if (pending & ATMCI_TXRDY)
1988			atmci_write_data_pio(host);
1989
1990		if (pending & ATMCI_CMDRDY) {
1991			dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n");
1992			atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
1993			host->cmd_status = status;
1994			smp_wmb();
1995			dev_dbg(&host->pdev->dev, "set pending cmd rdy\n");
1996			atmci_set_pending(host, EVENT_CMD_RDY);
1997			tasklet_schedule(&host->tasklet);
1998		}
1999
2000		if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
2001			atmci_sdio_interrupt(host, status);
2002
2003	} while (pass_count++ < 5);
2004
2005	return pass_count ? IRQ_HANDLED : IRQ_NONE;
2006}
2007
2008static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
2009{
2010	struct atmel_mci_slot	*slot = dev_id;
2011
2012	/*
2013	 * Disable interrupts until the pin has stabilized and check
2014	 * the state then. Use mod_timer() since we may be in the
2015	 * middle of the timer routine when this interrupt triggers.
2016	 */
2017	disable_irq_nosync(irq);
2018	mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
2019
2020	return IRQ_HANDLED;
2021}
2022
2023static int __init atmci_init_slot(struct atmel_mci *host,
2024		struct mci_slot_pdata *slot_data, unsigned int id,
2025		u32 sdc_reg, u32 sdio_irq)
2026{
2027	struct mmc_host			*mmc;
2028	struct atmel_mci_slot		*slot;
2029
2030	mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
2031	if (!mmc)
2032		return -ENOMEM;
2033
2034	slot = mmc_priv(mmc);
2035	slot->mmc = mmc;
2036	slot->host = host;
2037	slot->detect_pin = slot_data->detect_pin;
2038	slot->wp_pin = slot_data->wp_pin;
2039	slot->detect_is_active_high = slot_data->detect_is_active_high;
2040	slot->sdc_reg = sdc_reg;
2041	slot->sdio_irq = sdio_irq;
2042
 
 
 
 
 
 
 
2043	mmc->ops = &atmci_ops;
2044	mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
2045	mmc->f_max = host->bus_hz / 2;
2046	mmc->ocr_avail	= MMC_VDD_32_33 | MMC_VDD_33_34;
2047	if (sdio_irq)
2048		mmc->caps |= MMC_CAP_SDIO_IRQ;
2049	if (host->caps.has_highspeed)
2050		mmc->caps |= MMC_CAP_SD_HIGHSPEED;
2051	/*
2052	 * Without the read/write proof capability, it is strongly suggested to
2053	 * use only one bit for data to prevent fifo underruns and overruns
2054	 * which will corrupt data.
2055	 */
2056	if ((slot_data->bus_width >= 4) && host->caps.has_rwproof)
2057		mmc->caps |= MMC_CAP_4_BIT_DATA;
 
 
 
2058
2059	if (atmci_get_version(host) < 0x200) {
2060		mmc->max_segs = 256;
2061		mmc->max_blk_size = 4095;
2062		mmc->max_blk_count = 256;
2063		mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2064		mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs;
2065	} else {
2066		mmc->max_segs = 64;
2067		mmc->max_req_size = 32768 * 512;
2068		mmc->max_blk_size = 32768;
2069		mmc->max_blk_count = 512;
2070	}
2071
2072	/* Assume card is present initially */
2073	set_bit(ATMCI_CARD_PRESENT, &slot->flags);
2074	if (gpio_is_valid(slot->detect_pin)) {
2075		if (gpio_request(slot->detect_pin, "mmc_detect")) {
 
2076			dev_dbg(&mmc->class_dev, "no detect pin available\n");
2077			slot->detect_pin = -EBUSY;
2078		} else if (gpio_get_value(slot->detect_pin) ^
2079				slot->detect_is_active_high) {
2080			clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
2081		}
2082	}
2083
2084	if (!gpio_is_valid(slot->detect_pin))
2085		mmc->caps |= MMC_CAP_NEEDS_POLL;
 
 
 
 
2086
2087	if (gpio_is_valid(slot->wp_pin)) {
2088		if (gpio_request(slot->wp_pin, "mmc_wp")) {
 
2089			dev_dbg(&mmc->class_dev, "no WP pin available\n");
2090			slot->wp_pin = -EBUSY;
2091		}
2092	}
2093
2094	host->slot[id] = slot;
 
2095	mmc_add_host(mmc);
2096
2097	if (gpio_is_valid(slot->detect_pin)) {
2098		int ret;
2099
2100		setup_timer(&slot->detect_timer, atmci_detect_change,
2101				(unsigned long)slot);
2102
2103		ret = request_irq(gpio_to_irq(slot->detect_pin),
2104				atmci_detect_interrupt,
2105				IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2106				"mmc-detect", slot);
2107		if (ret) {
2108			dev_dbg(&mmc->class_dev,
2109				"could not request IRQ %d for detect pin\n",
2110				gpio_to_irq(slot->detect_pin));
2111			gpio_free(slot->detect_pin);
2112			slot->detect_pin = -EBUSY;
2113		}
2114	}
2115
2116	atmci_init_debugfs(slot);
2117
2118	return 0;
2119}
2120
2121static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot,
2122		unsigned int id)
2123{
2124	/* Debugfs stuff is cleaned up by mmc core */
2125
2126	set_bit(ATMCI_SHUTDOWN, &slot->flags);
2127	smp_wmb();
2128
2129	mmc_remove_host(slot->mmc);
2130
2131	if (gpio_is_valid(slot->detect_pin)) {
2132		int pin = slot->detect_pin;
2133
2134		free_irq(gpio_to_irq(pin), slot);
2135		del_timer_sync(&slot->detect_timer);
2136		gpio_free(pin);
2137	}
2138	if (gpio_is_valid(slot->wp_pin))
2139		gpio_free(slot->wp_pin);
2140
2141	slot->host->slot[id] = NULL;
2142	mmc_free_host(slot->mmc);
2143}
2144
2145static bool atmci_filter(struct dma_chan *chan, void *slave)
2146{
2147	struct mci_dma_data	*sl = slave;
2148
2149	if (sl && find_slave_dev(sl) == chan->device->dev) {
2150		chan->private = slave_data_ptr(sl);
2151		return true;
2152	} else {
2153		return false;
2154	}
2155}
2156
2157static bool atmci_configure_dma(struct atmel_mci *host)
2158{
2159	struct mci_platform_data	*pdata;
2160
2161	if (host == NULL)
2162		return false;
2163
2164	pdata = host->pdev->dev.platform_data;
2165
2166	if (pdata && find_slave_dev(pdata->dma_slave)) {
2167		dma_cap_mask_t mask;
2168
2169		/* Try to grab a DMA channel */
 
 
2170		dma_cap_zero(mask);
2171		dma_cap_set(DMA_SLAVE, mask);
2172		host->dma.chan =
2173			dma_request_channel(mask, atmci_filter, pdata->dma_slave);
2174	}
2175	if (!host->dma.chan) {
2176		dev_warn(&host->pdev->dev, "no DMA channel available\n");
2177		return false;
2178	} else {
2179		dev_info(&host->pdev->dev,
2180					"using %s for DMA transfers\n",
2181					dma_chan_name(host->dma.chan));
2182
2183		host->dma_conf.src_addr = host->mapbase + ATMCI_RDR;
2184		host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2185		host->dma_conf.src_maxburst = 1;
2186		host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR;
2187		host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2188		host->dma_conf.dst_maxburst = 1;
2189		host->dma_conf.device_fc = false;
2190		return true;
2191	}
 
 
2192}
2193
2194/*
2195 * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
2196 * HSMCI provides DMA support and a new config register but no more supports
2197 * PDC.
2198 */
2199static void __init atmci_get_cap(struct atmel_mci *host)
2200{
2201	unsigned int version;
2202
2203	version = atmci_get_version(host);
2204	dev_info(&host->pdev->dev,
2205			"version: 0x%x\n", version);
2206
2207	host->caps.has_dma = 0;
2208	host->caps.has_pdc = 1;
2209	host->caps.has_cfg_reg = 0;
2210	host->caps.has_cstor_reg = 0;
2211	host->caps.has_highspeed = 0;
2212	host->caps.has_rwproof = 0;
2213	host->caps.has_odd_clk_div = 0;
2214	host->caps.has_bad_data_ordering = 1;
2215	host->caps.need_reset_after_xfer = 1;
2216	host->caps.need_blksz_mul_4 = 1;
2217	host->caps.need_notbusy_for_read_ops = 0;
2218
2219	/* keep only major version number */
2220	switch (version & 0xf00) {
 
2221	case 0x500:
2222		host->caps.has_odd_clk_div = 1;
 
2223	case 0x400:
2224	case 0x300:
2225#ifdef CONFIG_AT_HDMAC
2226		host->caps.has_dma = 1;
2227#else
2228		dev_info(&host->pdev->dev,
2229			"has dma capability but dma engine is not selected, then use pio\n");
2230#endif
2231		host->caps.has_pdc = 0;
2232		host->caps.has_cfg_reg = 1;
2233		host->caps.has_cstor_reg = 1;
2234		host->caps.has_highspeed = 1;
 
2235	case 0x200:
2236		host->caps.has_rwproof = 1;
2237		host->caps.need_blksz_mul_4 = 0;
2238		host->caps.need_notbusy_for_read_ops = 1;
 
2239	case 0x100:
2240		host->caps.has_bad_data_ordering = 0;
2241		host->caps.need_reset_after_xfer = 0;
 
2242	case 0x0:
2243		break;
2244	default:
2245		host->caps.has_pdc = 0;
2246		dev_warn(&host->pdev->dev,
2247				"Unmanaged mci version, set minimum capabilities\n");
2248		break;
2249	}
2250}
2251
2252static int __init atmci_probe(struct platform_device *pdev)
2253{
2254	struct mci_platform_data	*pdata;
2255	struct atmel_mci		*host;
2256	struct resource			*regs;
2257	unsigned int			nr_slots;
2258	int				irq;
2259	int				ret;
2260
2261	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2262	if (!regs)
2263		return -ENXIO;
2264	pdata = pdev->dev.platform_data;
2265	if (!pdata)
2266		return -ENXIO;
 
 
 
 
 
 
2267	irq = platform_get_irq(pdev, 0);
2268	if (irq < 0)
2269		return irq;
2270
2271	host = kzalloc(sizeof(struct atmel_mci), GFP_KERNEL);
2272	if (!host)
2273		return -ENOMEM;
2274
2275	host->pdev = pdev;
2276	spin_lock_init(&host->lock);
2277	INIT_LIST_HEAD(&host->queue);
2278
2279	host->mck = clk_get(&pdev->dev, "mci_clk");
2280	if (IS_ERR(host->mck)) {
2281		ret = PTR_ERR(host->mck);
2282		goto err_clk_get;
2283	}
2284
2285	ret = -ENOMEM;
2286	host->regs = ioremap(regs->start, resource_size(regs));
2287	if (!host->regs)
2288		goto err_ioremap;
 
 
 
 
2289
2290	clk_enable(host->mck);
2291	atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
2292	host->bus_hz = clk_get_rate(host->mck);
2293	clk_disable(host->mck);
2294
2295	host->mapbase = regs->start;
2296
2297	tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
2298
2299	ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
2300	if (ret)
2301		goto err_request_irq;
 
 
2302
2303	/* Get MCI capabilities and set operations according to it */
2304	atmci_get_cap(host);
2305	if (host->caps.has_dma && atmci_configure_dma(host)) {
 
 
 
2306		host->prepare_data = &atmci_prepare_data_dma;
2307		host->submit_data = &atmci_submit_data_dma;
2308		host->stop_transfer = &atmci_stop_transfer_dma;
2309	} else if (host->caps.has_pdc) {
2310		dev_info(&pdev->dev, "using PDC\n");
2311		host->prepare_data = &atmci_prepare_data_pdc;
2312		host->submit_data = &atmci_submit_data_pdc;
2313		host->stop_transfer = &atmci_stop_transfer_pdc;
2314	} else {
2315		dev_info(&pdev->dev, "using PIO\n");
2316		host->prepare_data = &atmci_prepare_data;
2317		host->submit_data = &atmci_submit_data;
2318		host->stop_transfer = &atmci_stop_transfer;
2319	}
2320
2321	platform_set_drvdata(pdev, host);
2322
2323	setup_timer(&host->timer, atmci_timeout_timer, (unsigned long)host);
 
 
 
 
 
 
2324
2325	/* We need at least one slot to succeed */
2326	nr_slots = 0;
2327	ret = -ENODEV;
2328	if (pdata->slot[0].bus_width) {
2329		ret = atmci_init_slot(host, &pdata->slot[0],
2330				0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
2331		if (!ret) {
2332			nr_slots++;
2333			host->buf_size = host->slot[0]->mmc->max_req_size;
2334		}
2335	}
2336	if (pdata->slot[1].bus_width) {
2337		ret = atmci_init_slot(host, &pdata->slot[1],
2338				1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
2339		if (!ret) {
2340			nr_slots++;
2341			if (host->slot[1]->mmc->max_req_size > host->buf_size)
2342				host->buf_size =
2343					host->slot[1]->mmc->max_req_size;
2344		}
2345	}
2346
2347	if (!nr_slots) {
2348		dev_err(&pdev->dev, "init failed: no slot defined\n");
2349		goto err_init_slot;
2350	}
2351
2352	if (!host->caps.has_rwproof) {
2353		host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size,
2354		                                  &host->buf_phys_addr,
2355						  GFP_KERNEL);
2356		if (!host->buffer) {
2357			ret = -ENOMEM;
2358			dev_err(&pdev->dev, "buffer allocation failed\n");
2359			goto err_init_slot;
2360		}
2361	}
2362
2363	dev_info(&pdev->dev,
2364			"Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2365			host->mapbase, irq, nr_slots);
2366
 
 
 
2367	return 0;
2368
 
 
 
 
 
2369err_init_slot:
2370	if (host->dma.chan)
 
 
 
 
 
 
2371		dma_release_channel(host->dma.chan);
 
2372	free_irq(irq, host);
2373err_request_irq:
2374	iounmap(host->regs);
2375err_ioremap:
2376	clk_put(host->mck);
2377err_clk_get:
2378	kfree(host);
2379	return ret;
2380}
2381
2382static int __exit atmci_remove(struct platform_device *pdev)
2383{
2384	struct atmel_mci	*host = platform_get_drvdata(pdev);
2385	unsigned int		i;
2386
2387	platform_set_drvdata(pdev, NULL);
2388
2389	if (host->buffer)
2390		dma_free_coherent(&pdev->dev, host->buf_size,
2391		                  host->buffer, host->buf_phys_addr);
2392
2393	for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2394		if (host->slot[i])
2395			atmci_cleanup_slot(host->slot[i], i);
2396	}
2397
2398	clk_enable(host->mck);
2399	atmci_writel(host, ATMCI_IDR, ~0UL);
2400	atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
2401	atmci_readl(host, ATMCI_SR);
2402	clk_disable(host->mck);
2403
2404#ifdef CONFIG_MMC_ATMELMCI_DMA
2405	if (host->dma.chan)
2406		dma_release_channel(host->dma.chan);
2407#endif
2408
2409	free_irq(platform_get_irq(pdev, 0), host);
2410	iounmap(host->regs);
2411
2412	clk_put(host->mck);
2413	kfree(host);
 
 
2414
2415	return 0;
2416}
2417
2418#ifdef CONFIG_PM
2419static int atmci_suspend(struct device *dev)
2420{
2421	struct atmel_mci *host = dev_get_drvdata(dev);
2422	int i;
2423
2424	 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2425		struct atmel_mci_slot *slot = host->slot[i];
2426		int ret;
2427
2428		if (!slot)
2429			continue;
2430		ret = mmc_suspend_host(slot->mmc);
2431		if (ret < 0) {
2432			while (--i >= 0) {
2433				slot = host->slot[i];
2434				if (slot
2435				&& test_bit(ATMCI_SUSPENDED, &slot->flags)) {
2436					mmc_resume_host(host->slot[i]->mmc);
2437					clear_bit(ATMCI_SUSPENDED, &slot->flags);
2438				}
2439			}
2440			return ret;
2441		} else {
2442			set_bit(ATMCI_SUSPENDED, &slot->flags);
2443		}
2444	}
2445
2446	return 0;
2447}
2448
2449static int atmci_resume(struct device *dev)
2450{
2451	struct atmel_mci *host = dev_get_drvdata(dev);
2452	int i;
2453	int ret = 0;
2454
2455	for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2456		struct atmel_mci_slot *slot = host->slot[i];
2457		int err;
2458
2459		slot = host->slot[i];
2460		if (!slot)
2461			continue;
2462		if (!test_bit(ATMCI_SUSPENDED, &slot->flags))
2463			continue;
2464		err = mmc_resume_host(slot->mmc);
2465		if (err < 0)
2466			ret = err;
2467		else
2468			clear_bit(ATMCI_SUSPENDED, &slot->flags);
2469	}
2470
2471	return ret;
2472}
2473static SIMPLE_DEV_PM_OPS(atmci_pm, atmci_suspend, atmci_resume);
2474#define ATMCI_PM_OPS	(&atmci_pm)
2475#else
2476#define ATMCI_PM_OPS	NULL
2477#endif
2478
 
 
 
 
 
 
2479static struct platform_driver atmci_driver = {
2480	.remove		= __exit_p(atmci_remove),
 
2481	.driver		= {
2482		.name		= "atmel_mci",
2483		.pm		= ATMCI_PM_OPS,
 
2484	},
2485};
2486
2487static int __init atmci_init(void)
2488{
2489	return platform_driver_probe(&atmci_driver, atmci_probe);
2490}
2491
2492static void __exit atmci_exit(void)
2493{
2494	platform_driver_unregister(&atmci_driver);
2495}
2496
2497late_initcall(atmci_init); /* try to load after dma driver when built-in */
2498module_exit(atmci_exit);
2499
2500MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
2501MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2502MODULE_LICENSE("GPL v2");