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1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License, version 2
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
6 */
7
8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/platform_device.h>
11#include <linux/slab.h>
12#include <linux/gpio.h>
13#include <linux/irq.h>
14#include <linux/interrupt.h>
15#include <linux/mfd/stmpe.h>
16
17/*
18 * These registers are modified under the irq bus lock and cached to avoid
19 * unnecessary writes in bus_sync_unlock.
20 */
21enum { REG_RE, REG_FE, REG_IE };
22
23#define CACHE_NR_REGS 3
24#define CACHE_NR_BANKS (STMPE_NR_GPIOS / 8)
25
26struct stmpe_gpio {
27 struct gpio_chip chip;
28 struct stmpe *stmpe;
29 struct device *dev;
30 struct mutex irq_lock;
31
32 int irq_base;
33 unsigned norequest_mask;
34
35 /* Caches of interrupt control registers for bus_lock */
36 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
37 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
38};
39
40static inline struct stmpe_gpio *to_stmpe_gpio(struct gpio_chip *chip)
41{
42 return container_of(chip, struct stmpe_gpio, chip);
43}
44
45static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
46{
47 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
48 struct stmpe *stmpe = stmpe_gpio->stmpe;
49 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
50 u8 mask = 1 << (offset % 8);
51 int ret;
52
53 ret = stmpe_reg_read(stmpe, reg);
54 if (ret < 0)
55 return ret;
56
57 return !!(ret & mask);
58}
59
60static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
61{
62 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
63 struct stmpe *stmpe = stmpe_gpio->stmpe;
64 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
65 u8 reg = stmpe->regs[which] - (offset / 8);
66 u8 mask = 1 << (offset % 8);
67
68 /*
69 * Some variants have single register for gpio set/clear functionality.
70 * For them we need to write 0 to clear and 1 to set.
71 */
72 if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
73 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
74 else
75 stmpe_reg_write(stmpe, reg, mask);
76}
77
78static int stmpe_gpio_direction_output(struct gpio_chip *chip,
79 unsigned offset, int val)
80{
81 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
82 struct stmpe *stmpe = stmpe_gpio->stmpe;
83 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
84 u8 mask = 1 << (offset % 8);
85
86 stmpe_gpio_set(chip, offset, val);
87
88 return stmpe_set_bits(stmpe, reg, mask, mask);
89}
90
91static int stmpe_gpio_direction_input(struct gpio_chip *chip,
92 unsigned offset)
93{
94 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
95 struct stmpe *stmpe = stmpe_gpio->stmpe;
96 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
97 u8 mask = 1 << (offset % 8);
98
99 return stmpe_set_bits(stmpe, reg, mask, 0);
100}
101
102static int stmpe_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
103{
104 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
105
106 return stmpe_gpio->irq_base + offset;
107}
108
109static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
110{
111 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
112 struct stmpe *stmpe = stmpe_gpio->stmpe;
113
114 if (stmpe_gpio->norequest_mask & (1 << offset))
115 return -EINVAL;
116
117 return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
118}
119
120static struct gpio_chip template_chip = {
121 .label = "stmpe",
122 .owner = THIS_MODULE,
123 .direction_input = stmpe_gpio_direction_input,
124 .get = stmpe_gpio_get,
125 .direction_output = stmpe_gpio_direction_output,
126 .set = stmpe_gpio_set,
127 .to_irq = stmpe_gpio_to_irq,
128 .request = stmpe_gpio_request,
129 .can_sleep = 1,
130};
131
132static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
133{
134 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
135 int offset = d->irq - stmpe_gpio->irq_base;
136 int regoffset = offset / 8;
137 int mask = 1 << (offset % 8);
138
139 if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
140 return -EINVAL;
141
142 /* STMPE801 doesn't have RE and FE registers */
143 if (stmpe_gpio->stmpe->partnum == STMPE801)
144 return 0;
145
146 if (type == IRQ_TYPE_EDGE_RISING)
147 stmpe_gpio->regs[REG_RE][regoffset] |= mask;
148 else
149 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
150
151 if (type == IRQ_TYPE_EDGE_FALLING)
152 stmpe_gpio->regs[REG_FE][regoffset] |= mask;
153 else
154 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
155
156 return 0;
157}
158
159static void stmpe_gpio_irq_lock(struct irq_data *d)
160{
161 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
162
163 mutex_lock(&stmpe_gpio->irq_lock);
164}
165
166static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
167{
168 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
169 struct stmpe *stmpe = stmpe_gpio->stmpe;
170 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
171 static const u8 regmap[] = {
172 [REG_RE] = STMPE_IDX_GPRER_LSB,
173 [REG_FE] = STMPE_IDX_GPFER_LSB,
174 [REG_IE] = STMPE_IDX_IEGPIOR_LSB,
175 };
176 int i, j;
177
178 for (i = 0; i < CACHE_NR_REGS; i++) {
179 /* STMPE801 doesn't have RE and FE registers */
180 if ((stmpe->partnum == STMPE801) &&
181 (i != REG_IE))
182 continue;
183
184 for (j = 0; j < num_banks; j++) {
185 u8 old = stmpe_gpio->oldregs[i][j];
186 u8 new = stmpe_gpio->regs[i][j];
187
188 if (new == old)
189 continue;
190
191 stmpe_gpio->oldregs[i][j] = new;
192 stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new);
193 }
194 }
195
196 mutex_unlock(&stmpe_gpio->irq_lock);
197}
198
199static void stmpe_gpio_irq_mask(struct irq_data *d)
200{
201 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
202 int offset = d->irq - stmpe_gpio->irq_base;
203 int regoffset = offset / 8;
204 int mask = 1 << (offset % 8);
205
206 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
207}
208
209static void stmpe_gpio_irq_unmask(struct irq_data *d)
210{
211 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
212 int offset = d->irq - stmpe_gpio->irq_base;
213 int regoffset = offset / 8;
214 int mask = 1 << (offset % 8);
215
216 stmpe_gpio->regs[REG_IE][regoffset] |= mask;
217}
218
219static struct irq_chip stmpe_gpio_irq_chip = {
220 .name = "stmpe-gpio",
221 .irq_bus_lock = stmpe_gpio_irq_lock,
222 .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
223 .irq_mask = stmpe_gpio_irq_mask,
224 .irq_unmask = stmpe_gpio_irq_unmask,
225 .irq_set_type = stmpe_gpio_irq_set_type,
226};
227
228static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
229{
230 struct stmpe_gpio *stmpe_gpio = dev;
231 struct stmpe *stmpe = stmpe_gpio->stmpe;
232 u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
233 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
234 u8 status[num_banks];
235 int ret;
236 int i;
237
238 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
239 if (ret < 0)
240 return IRQ_NONE;
241
242 for (i = 0; i < num_banks; i++) {
243 int bank = num_banks - i - 1;
244 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
245 unsigned int stat = status[i];
246
247 stat &= enabled;
248 if (!stat)
249 continue;
250
251 while (stat) {
252 int bit = __ffs(stat);
253 int line = bank * 8 + bit;
254
255 handle_nested_irq(stmpe_gpio->irq_base + line);
256 stat &= ~(1 << bit);
257 }
258
259 stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
260
261 /* Edge detect register is not present on 801 */
262 if (stmpe->partnum != STMPE801)
263 stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB]
264 + i, status[i]);
265 }
266
267 return IRQ_HANDLED;
268}
269
270static int __devinit stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio)
271{
272 int base = stmpe_gpio->irq_base;
273 int irq;
274
275 for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
276 irq_set_chip_data(irq, stmpe_gpio);
277 irq_set_chip_and_handler(irq, &stmpe_gpio_irq_chip,
278 handle_simple_irq);
279 irq_set_nested_thread(irq, 1);
280#ifdef CONFIG_ARM
281 set_irq_flags(irq, IRQF_VALID);
282#else
283 irq_set_noprobe(irq);
284#endif
285 }
286
287 return 0;
288}
289
290static void stmpe_gpio_irq_remove(struct stmpe_gpio *stmpe_gpio)
291{
292 int base = stmpe_gpio->irq_base;
293 int irq;
294
295 for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
296#ifdef CONFIG_ARM
297 set_irq_flags(irq, 0);
298#endif
299 irq_set_chip_and_handler(irq, NULL, NULL);
300 irq_set_chip_data(irq, NULL);
301 }
302}
303
304static int __devinit stmpe_gpio_probe(struct platform_device *pdev)
305{
306 struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
307 struct stmpe_gpio_platform_data *pdata;
308 struct stmpe_gpio *stmpe_gpio;
309 int ret;
310 int irq = 0;
311
312 pdata = stmpe->pdata->gpio;
313
314 irq = platform_get_irq(pdev, 0);
315
316 stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
317 if (!stmpe_gpio)
318 return -ENOMEM;
319
320 mutex_init(&stmpe_gpio->irq_lock);
321
322 stmpe_gpio->dev = &pdev->dev;
323 stmpe_gpio->stmpe = stmpe;
324 stmpe_gpio->norequest_mask = pdata ? pdata->norequest_mask : 0;
325
326 stmpe_gpio->chip = template_chip;
327 stmpe_gpio->chip.ngpio = stmpe->num_gpios;
328 stmpe_gpio->chip.dev = &pdev->dev;
329 stmpe_gpio->chip.base = pdata ? pdata->gpio_base : -1;
330
331 if (irq >= 0)
332 stmpe_gpio->irq_base = stmpe->irq_base + STMPE_INT_GPIO(0);
333 else
334 dev_info(&pdev->dev,
335 "device configured in no-irq mode; "
336 "irqs are not available\n");
337
338 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
339 if (ret)
340 goto out_free;
341
342 if (irq >= 0) {
343 ret = stmpe_gpio_irq_init(stmpe_gpio);
344 if (ret)
345 goto out_disable;
346
347 ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq,
348 IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio);
349 if (ret) {
350 dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
351 goto out_removeirq;
352 }
353 }
354
355 ret = gpiochip_add(&stmpe_gpio->chip);
356 if (ret) {
357 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
358 goto out_freeirq;
359 }
360
361 if (pdata && pdata->setup)
362 pdata->setup(stmpe, stmpe_gpio->chip.base);
363
364 platform_set_drvdata(pdev, stmpe_gpio);
365
366 return 0;
367
368out_freeirq:
369 if (irq >= 0)
370 free_irq(irq, stmpe_gpio);
371out_removeirq:
372 if (irq >= 0)
373 stmpe_gpio_irq_remove(stmpe_gpio);
374out_disable:
375 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
376out_free:
377 kfree(stmpe_gpio);
378 return ret;
379}
380
381static int __devexit stmpe_gpio_remove(struct platform_device *pdev)
382{
383 struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
384 struct stmpe *stmpe = stmpe_gpio->stmpe;
385 struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio;
386 int irq = platform_get_irq(pdev, 0);
387 int ret;
388
389 if (pdata && pdata->remove)
390 pdata->remove(stmpe, stmpe_gpio->chip.base);
391
392 ret = gpiochip_remove(&stmpe_gpio->chip);
393 if (ret < 0) {
394 dev_err(stmpe_gpio->dev,
395 "unable to remove gpiochip: %d\n", ret);
396 return ret;
397 }
398
399 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
400
401 if (irq >= 0) {
402 free_irq(irq, stmpe_gpio);
403 stmpe_gpio_irq_remove(stmpe_gpio);
404 }
405 platform_set_drvdata(pdev, NULL);
406 kfree(stmpe_gpio);
407
408 return 0;
409}
410
411static struct platform_driver stmpe_gpio_driver = {
412 .driver.name = "stmpe-gpio",
413 .driver.owner = THIS_MODULE,
414 .probe = stmpe_gpio_probe,
415 .remove = __devexit_p(stmpe_gpio_remove),
416};
417
418static int __init stmpe_gpio_init(void)
419{
420 return platform_driver_register(&stmpe_gpio_driver);
421}
422subsys_initcall(stmpe_gpio_init);
423
424static void __exit stmpe_gpio_exit(void)
425{
426 platform_driver_unregister(&stmpe_gpio_driver);
427}
428module_exit(stmpe_gpio_exit);
429
430MODULE_LICENSE("GPL v2");
431MODULE_DESCRIPTION("STMPExxxx GPIO driver");
432MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
6 */
7
8#include <linux/init.h>
9#include <linux/platform_device.h>
10#include <linux/slab.h>
11#include <linux/gpio/driver.h>
12#include <linux/interrupt.h>
13#include <linux/of.h>
14#include <linux/mfd/stmpe.h>
15#include <linux/seq_file.h>
16#include <linux/bitops.h>
17
18/*
19 * These registers are modified under the irq bus lock and cached to avoid
20 * unnecessary writes in bus_sync_unlock.
21 */
22enum { REG_RE, REG_FE, REG_IE };
23
24enum { LSB, CSB, MSB };
25
26#define CACHE_NR_REGS 3
27/* No variant has more than 24 GPIOs */
28#define CACHE_NR_BANKS (24 / 8)
29
30struct stmpe_gpio {
31 struct gpio_chip chip;
32 struct stmpe *stmpe;
33 struct device *dev;
34 struct mutex irq_lock;
35 u32 norequest_mask;
36 /* Caches of interrupt control registers for bus_lock */
37 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
38 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
39};
40
41static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
42{
43 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
44 struct stmpe *stmpe = stmpe_gpio->stmpe;
45 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];
46 u8 mask = BIT(offset % 8);
47 int ret;
48
49 ret = stmpe_reg_read(stmpe, reg);
50 if (ret < 0)
51 return ret;
52
53 return !!(ret & mask);
54}
55
56static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
57{
58 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
59 struct stmpe *stmpe = stmpe_gpio->stmpe;
60 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
61 u8 reg = stmpe->regs[which + (offset / 8)];
62 u8 mask = BIT(offset % 8);
63
64 /*
65 * Some variants have single register for gpio set/clear functionality.
66 * For them we need to write 0 to clear and 1 to set.
67 */
68 if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
69 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
70 else
71 stmpe_reg_write(stmpe, reg, mask);
72}
73
74static int stmpe_gpio_get_direction(struct gpio_chip *chip,
75 unsigned offset)
76{
77 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
78 struct stmpe *stmpe = stmpe_gpio->stmpe;
79 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
80 u8 mask = BIT(offset % 8);
81 int ret;
82
83 ret = stmpe_reg_read(stmpe, reg);
84 if (ret < 0)
85 return ret;
86
87 return !(ret & mask);
88}
89
90static int stmpe_gpio_direction_output(struct gpio_chip *chip,
91 unsigned offset, int val)
92{
93 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
94 struct stmpe *stmpe = stmpe_gpio->stmpe;
95 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
96 u8 mask = BIT(offset % 8);
97
98 stmpe_gpio_set(chip, offset, val);
99
100 return stmpe_set_bits(stmpe, reg, mask, mask);
101}
102
103static int stmpe_gpio_direction_input(struct gpio_chip *chip,
104 unsigned offset)
105{
106 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
107 struct stmpe *stmpe = stmpe_gpio->stmpe;
108 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
109 u8 mask = BIT(offset % 8);
110
111 return stmpe_set_bits(stmpe, reg, mask, 0);
112}
113
114static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
115{
116 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
117 struct stmpe *stmpe = stmpe_gpio->stmpe;
118
119 if (stmpe_gpio->norequest_mask & BIT(offset))
120 return -EINVAL;
121
122 return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO);
123}
124
125static const struct gpio_chip template_chip = {
126 .label = "stmpe",
127 .owner = THIS_MODULE,
128 .get_direction = stmpe_gpio_get_direction,
129 .direction_input = stmpe_gpio_direction_input,
130 .get = stmpe_gpio_get,
131 .direction_output = stmpe_gpio_direction_output,
132 .set = stmpe_gpio_set,
133 .request = stmpe_gpio_request,
134 .can_sleep = true,
135};
136
137static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
138{
139 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
140 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
141 int offset = d->hwirq;
142 int regoffset = offset / 8;
143 int mask = BIT(offset % 8);
144
145 if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)
146 return -EINVAL;
147
148 /* STMPE801 and STMPE 1600 don't have RE and FE registers */
149 if (stmpe_gpio->stmpe->partnum == STMPE801 ||
150 stmpe_gpio->stmpe->partnum == STMPE1600)
151 return 0;
152
153 if (type & IRQ_TYPE_EDGE_RISING)
154 stmpe_gpio->regs[REG_RE][regoffset] |= mask;
155 else
156 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
157
158 if (type & IRQ_TYPE_EDGE_FALLING)
159 stmpe_gpio->regs[REG_FE][regoffset] |= mask;
160 else
161 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
162
163 return 0;
164}
165
166static void stmpe_gpio_irq_lock(struct irq_data *d)
167{
168 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
169 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
170
171 mutex_lock(&stmpe_gpio->irq_lock);
172}
173
174static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
175{
176 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
177 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
178 struct stmpe *stmpe = stmpe_gpio->stmpe;
179 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
180 static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {
181 [REG_RE][LSB] = STMPE_IDX_GPRER_LSB,
182 [REG_RE][CSB] = STMPE_IDX_GPRER_CSB,
183 [REG_RE][MSB] = STMPE_IDX_GPRER_MSB,
184 [REG_FE][LSB] = STMPE_IDX_GPFER_LSB,
185 [REG_FE][CSB] = STMPE_IDX_GPFER_CSB,
186 [REG_FE][MSB] = STMPE_IDX_GPFER_MSB,
187 [REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,
188 [REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,
189 [REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,
190 };
191 int i, j;
192
193 /*
194 * STMPE1600: to be able to get IRQ from pins,
195 * a read must be done on GPMR register, or a write in
196 * GPSR or GPCR registers
197 */
198 if (stmpe->partnum == STMPE1600) {
199 stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);
200 stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);
201 }
202
203 for (i = 0; i < CACHE_NR_REGS; i++) {
204 /* STMPE801 and STMPE1600 don't have RE and FE registers */
205 if ((stmpe->partnum == STMPE801 ||
206 stmpe->partnum == STMPE1600) &&
207 (i != REG_IE))
208 continue;
209
210 for (j = 0; j < num_banks; j++) {
211 u8 old = stmpe_gpio->oldregs[i][j];
212 u8 new = stmpe_gpio->regs[i][j];
213
214 if (new == old)
215 continue;
216
217 stmpe_gpio->oldregs[i][j] = new;
218 stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);
219 }
220 }
221
222 mutex_unlock(&stmpe_gpio->irq_lock);
223}
224
225static void stmpe_gpio_irq_mask(struct irq_data *d)
226{
227 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
228 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
229 int offset = d->hwirq;
230 int regoffset = offset / 8;
231 int mask = BIT(offset % 8);
232
233 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
234}
235
236static void stmpe_gpio_irq_unmask(struct irq_data *d)
237{
238 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
239 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
240 int offset = d->hwirq;
241 int regoffset = offset / 8;
242 int mask = BIT(offset % 8);
243
244 stmpe_gpio->regs[REG_IE][regoffset] |= mask;
245}
246
247static void stmpe_dbg_show_one(struct seq_file *s,
248 struct gpio_chip *gc,
249 unsigned offset, unsigned gpio)
250{
251 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
252 struct stmpe *stmpe = stmpe_gpio->stmpe;
253 const char *label = gpiochip_is_requested(gc, offset);
254 bool val = !!stmpe_gpio_get(gc, offset);
255 u8 bank = offset / 8;
256 u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
257 u8 mask = BIT(offset % 8);
258 int ret;
259 u8 dir;
260
261 ret = stmpe_reg_read(stmpe, dir_reg);
262 if (ret < 0)
263 return;
264 dir = !!(ret & mask);
265
266 if (dir) {
267 seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
268 gpio, label ?: "(none)",
269 val ? "hi" : "lo");
270 } else {
271 u8 edge_det_reg;
272 u8 rise_reg;
273 u8 fall_reg;
274 u8 irqen_reg;
275
276 static const char * const edge_det_values[] = {
277 "edge-inactive",
278 "edge-asserted",
279 "not-supported"
280 };
281 static const char * const rise_values[] = {
282 "no-rising-edge-detection",
283 "rising-edge-detection",
284 "not-supported"
285 };
286 static const char * const fall_values[] = {
287 "no-falling-edge-detection",
288 "falling-edge-detection",
289 "not-supported"
290 };
291 #define NOT_SUPPORTED_IDX 2
292 u8 edge_det = NOT_SUPPORTED_IDX;
293 u8 rise = NOT_SUPPORTED_IDX;
294 u8 fall = NOT_SUPPORTED_IDX;
295 bool irqen;
296
297 switch (stmpe->partnum) {
298 case STMPE610:
299 case STMPE811:
300 case STMPE1601:
301 case STMPE2401:
302 case STMPE2403:
303 edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
304 ret = stmpe_reg_read(stmpe, edge_det_reg);
305 if (ret < 0)
306 return;
307 edge_det = !!(ret & mask);
308 /* fall through */
309 case STMPE1801:
310 rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
311 fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];
312
313 ret = stmpe_reg_read(stmpe, rise_reg);
314 if (ret < 0)
315 return;
316 rise = !!(ret & mask);
317 ret = stmpe_reg_read(stmpe, fall_reg);
318 if (ret < 0)
319 return;
320 fall = !!(ret & mask);
321 /* fall through */
322 case STMPE801:
323 case STMPE1600:
324 irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
325 break;
326
327 default:
328 return;
329 }
330
331 ret = stmpe_reg_read(stmpe, irqen_reg);
332 if (ret < 0)
333 return;
334 irqen = !!(ret & mask);
335
336 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s",
337 gpio, label ?: "(none)",
338 val ? "hi" : "lo",
339 edge_det_values[edge_det],
340 irqen ? "IRQ-enabled" : "IRQ-disabled",
341 rise_values[rise],
342 fall_values[fall]);
343 }
344}
345
346static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc)
347{
348 unsigned i;
349 unsigned gpio = gc->base;
350
351 for (i = 0; i < gc->ngpio; i++, gpio++) {
352 stmpe_dbg_show_one(s, gc, i, gpio);
353 seq_putc(s, '\n');
354 }
355}
356
357static struct irq_chip stmpe_gpio_irq_chip = {
358 .name = "stmpe-gpio",
359 .irq_bus_lock = stmpe_gpio_irq_lock,
360 .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
361 .irq_mask = stmpe_gpio_irq_mask,
362 .irq_unmask = stmpe_gpio_irq_unmask,
363 .irq_set_type = stmpe_gpio_irq_set_type,
364};
365
366#define MAX_GPIOS 24
367
368static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
369{
370 struct stmpe_gpio *stmpe_gpio = dev;
371 struct stmpe *stmpe = stmpe_gpio->stmpe;
372 u8 statmsbreg;
373 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
374 u8 status[DIV_ROUND_UP(MAX_GPIOS, 8)];
375 int ret;
376 int i;
377
378 /*
379 * the stmpe_block_read() call below, imposes to set statmsbreg
380 * with the register located at the lowest address. As STMPE1600
381 * variant is the only one which respect registers address's order
382 * (LSB regs located at lowest address than MSB ones) whereas all
383 * the others have a registers layout with MSB located before the
384 * LSB regs.
385 */
386 if (stmpe->partnum == STMPE1600)
387 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];
388 else
389 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
390
391 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
392 if (ret < 0)
393 return IRQ_NONE;
394
395 for (i = 0; i < num_banks; i++) {
396 int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :
397 num_banks - i - 1;
398 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
399 unsigned int stat = status[i];
400
401 stat &= enabled;
402 if (!stat)
403 continue;
404
405 while (stat) {
406 int bit = __ffs(stat);
407 int line = bank * 8 + bit;
408 int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain,
409 line);
410
411 handle_nested_irq(child_irq);
412 stat &= ~BIT(bit);
413 }
414
415 /*
416 * interrupt status register write has no effect on
417 * 801/1801/1600, bits are cleared when read.
418 * Edge detect register is not present on 801/1600/1801
419 */
420 if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 &&
421 stmpe->partnum != STMPE1801) {
422 stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
423 stmpe_reg_write(stmpe,
424 stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
425 status[i]);
426 }
427 }
428
429 return IRQ_HANDLED;
430}
431
432static void stmpe_init_irq_valid_mask(struct gpio_chip *gc,
433 unsigned long *valid_mask,
434 unsigned int ngpios)
435{
436 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
437 int i;
438
439 if (!stmpe_gpio->norequest_mask)
440 return;
441
442 /* Forbid unused lines to be mapped as IRQs */
443 for (i = 0; i < sizeof(u32); i++) {
444 if (stmpe_gpio->norequest_mask & BIT(i))
445 clear_bit(i, valid_mask);
446 }
447}
448
449static int stmpe_gpio_probe(struct platform_device *pdev)
450{
451 struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
452 struct device_node *np = pdev->dev.of_node;
453 struct stmpe_gpio *stmpe_gpio;
454 int ret, irq;
455
456 if (stmpe->num_gpios > MAX_GPIOS) {
457 dev_err(&pdev->dev, "Need to increase maximum GPIO number\n");
458 return -EINVAL;
459 }
460
461 stmpe_gpio = kzalloc(sizeof(*stmpe_gpio), GFP_KERNEL);
462 if (!stmpe_gpio)
463 return -ENOMEM;
464
465 mutex_init(&stmpe_gpio->irq_lock);
466
467 stmpe_gpio->dev = &pdev->dev;
468 stmpe_gpio->stmpe = stmpe;
469 stmpe_gpio->chip = template_chip;
470 stmpe_gpio->chip.ngpio = stmpe->num_gpios;
471 stmpe_gpio->chip.parent = &pdev->dev;
472 stmpe_gpio->chip.of_node = np;
473 stmpe_gpio->chip.base = -1;
474 /*
475 * REVISIT: this makes sure the valid mask gets allocated and
476 * filled in when adding the gpio_chip, but the rest of the
477 * gpio_irqchip is still filled in using the old method
478 * in gpiochip_irqchip_add_nested() so clean this up once we
479 * get the gpio_irqchip to initialize while adding the
480 * gpio_chip also for threaded irqchips.
481 */
482 stmpe_gpio->chip.irq.init_valid_mask = stmpe_init_irq_valid_mask;
483
484 if (IS_ENABLED(CONFIG_DEBUG_FS))
485 stmpe_gpio->chip.dbg_show = stmpe_dbg_show;
486
487 of_property_read_u32(np, "st,norequest-mask",
488 &stmpe_gpio->norequest_mask);
489
490 irq = platform_get_irq(pdev, 0);
491 if (irq < 0)
492 dev_info(&pdev->dev,
493 "device configured in no-irq mode: "
494 "irqs are not available\n");
495
496 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
497 if (ret)
498 goto out_free;
499
500 ret = gpiochip_add_data(&stmpe_gpio->chip, stmpe_gpio);
501 if (ret) {
502 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
503 goto out_disable;
504 }
505
506 if (irq > 0) {
507 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
508 stmpe_gpio_irq, IRQF_ONESHOT,
509 "stmpe-gpio", stmpe_gpio);
510 if (ret) {
511 dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
512 goto out_disable;
513 }
514 ret = gpiochip_irqchip_add_nested(&stmpe_gpio->chip,
515 &stmpe_gpio_irq_chip,
516 0,
517 handle_simple_irq,
518 IRQ_TYPE_NONE);
519 if (ret) {
520 dev_err(&pdev->dev,
521 "could not connect irqchip to gpiochip\n");
522 goto out_disable;
523 }
524
525 gpiochip_set_nested_irqchip(&stmpe_gpio->chip,
526 &stmpe_gpio_irq_chip,
527 irq);
528 }
529
530 platform_set_drvdata(pdev, stmpe_gpio);
531
532 return 0;
533
534out_disable:
535 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
536 gpiochip_remove(&stmpe_gpio->chip);
537out_free:
538 kfree(stmpe_gpio);
539 return ret;
540}
541
542static struct platform_driver stmpe_gpio_driver = {
543 .driver = {
544 .suppress_bind_attrs = true,
545 .name = "stmpe-gpio",
546 },
547 .probe = stmpe_gpio_probe,
548};
549
550static int __init stmpe_gpio_init(void)
551{
552 return platform_driver_register(&stmpe_gpio_driver);
553}
554subsys_initcall(stmpe_gpio_init);