1/*
  2 * ICS backend for OPAL managed interrupts.
  3 *
  4 * Copyright 2011 IBM Corp.
  5 *
  6 * This program is free software; you can redistribute it and/or
  7 * modify it under the terms of the GNU General Public License
  8 * as published by the Free Software Foundation; either version
  9 * 2 of the License, or (at your option) any later version.
 10 */
 11
 12#undef DEBUG
 13
 14#include <linux/types.h>
 15#include <linux/kernel.h>
 16#include <linux/irq.h>
 17#include <linux/smp.h>
 18#include <linux/interrupt.h>
 19#include <linux/init.h>
 20#include <linux/cpu.h>
 21#include <linux/of.h>
 22#include <linux/spinlock.h>
 23#include <linux/msi.h>
 24
 25#include <asm/prom.h>
 26#include <asm/smp.h>
 27#include <asm/machdep.h>
 28#include <asm/irq.h>
 29#include <asm/errno.h>
 30#include <asm/xics.h>
 31#include <asm/opal.h>
 32#include <asm/firmware.h>
 33
 34static int ics_opal_mangle_server(int server)
 35{
 36	/* No link for now */
 37	return server << 2;
 38}
 39
 40static int ics_opal_unmangle_server(int server)
 41{
 42	/* No link for now */
 43	return server >> 2;
 44}
 45
 46static void ics_opal_unmask_irq(struct irq_data *d)
 47{
 48	unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
 49	int64_t rc;
 50	int server;
 51
 52	pr_devel("ics-hal: unmask virq %d [hw 0x%x]\n", d->irq, hw_irq);
 53
 54	if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
 55		return;
 56
 57	server = xics_get_irq_server(d->irq, d->affinity, 0);
 58	server = ics_opal_mangle_server(server);
 59
 60	rc = opal_set_xive(hw_irq, server, DEFAULT_PRIORITY);
 61	if (rc != OPAL_SUCCESS)
 62		pr_err("%s: opal_set_xive(irq=%d [hw 0x%x] server=%x)"
 63		       " error %lld\n",
 64		       __func__, d->irq, hw_irq, server, rc);
 65}
 66
 67static unsigned int ics_opal_startup(struct irq_data *d)
 68{
 69#ifdef CONFIG_PCI_MSI
 70	/*
 71	 * The generic MSI code returns with the interrupt disabled on the
 72	 * card, using the MSI mask bits. Firmware doesn't appear to unmask
 73	 * at that level, so we do it here by hand.
 74	 */
 75	if (d->msi_desc)
 76		unmask_msi_irq(d);
 77#endif
 78
 79	/* unmask it */
 80	ics_opal_unmask_irq(d);
 81	return 0;
 82}
 83
 84static void ics_opal_mask_real_irq(unsigned int hw_irq)
 85{
 86	int server = ics_opal_mangle_server(xics_default_server);
 87	int64_t rc;
 88
 89	if (hw_irq == XICS_IPI)
 90		return;
 91
 92	/* Have to set XIVE to 0xff to be able to remove a slot */
 93	rc = opal_set_xive(hw_irq, server, 0xff);
 94	if (rc != OPAL_SUCCESS)
 95		pr_err("%s: opal_set_xive(0xff) irq=%u returned %lld\n",
 96		       __func__, hw_irq, rc);
 97}
 98
 99static void ics_opal_mask_irq(struct irq_data *d)
100{
101	unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
102
103	pr_devel("ics-hal: mask virq %d [hw 0x%x]\n", d->irq, hw_irq);
104
105	if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
106		return;
107	ics_opal_mask_real_irq(hw_irq);
108}
109
110static int ics_opal_set_affinity(struct irq_data *d,
111				 const struct cpumask *cpumask,
112				 bool force)
113{
114	unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
 
115	int16_t server;
116	int8_t priority;
117	int64_t rc;
118	int wanted_server;
119
120	if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
121		return -1;
122
123	rc = opal_get_xive(hw_irq, &server, &priority);
124	if (rc != OPAL_SUCCESS) {
125		pr_err("%s: opal_set_xive(irq=%d [hw 0x%x] server=%x)"
126		       " error %lld\n",
127		       __func__, d->irq, hw_irq, server, rc);
128		return -1;
129	}
 
130
131	wanted_server = xics_get_irq_server(d->irq, cpumask, 1);
132	if (wanted_server < 0) {
133		char cpulist[128];
134		cpumask_scnprintf(cpulist, sizeof(cpulist), cpumask);
135		pr_warning("%s: No online cpus in the mask %s for irq %d\n",
136			   __func__, cpulist, d->irq);
137		return -1;
138	}
139	server = ics_opal_mangle_server(wanted_server);
140
141	pr_devel("ics-hal: set-affinity irq %d [hw 0x%x] server: 0x%x/0x%x\n",
142		 d->irq, hw_irq, wanted_server, server);
143
144	rc = opal_set_xive(hw_irq, server, priority);
145	if (rc != OPAL_SUCCESS) {
146		pr_err("%s: opal_set_xive(irq=%d [hw 0x%x] server=%x)"
147		       " error %lld\n",
148		       __func__, d->irq, hw_irq, server, rc);
149		return -1;
150	}
151	return 0;
152}
153
154static struct irq_chip ics_opal_irq_chip = {
155	.name = "OPAL ICS",
156	.irq_startup = ics_opal_startup,
157	.irq_mask = ics_opal_mask_irq,
158	.irq_unmask = ics_opal_unmask_irq,
159	.irq_eoi = NULL, /* Patched at init time */
160	.irq_set_affinity = ics_opal_set_affinity
 
 
161};
162
163static int ics_opal_map(struct ics *ics, unsigned int virq);
164static void ics_opal_mask_unknown(struct ics *ics, unsigned long vec);
165static long ics_opal_get_server(struct ics *ics, unsigned long vec);
166
167static int ics_opal_host_match(struct ics *ics, struct device_node *node)
168{
169	return 1;
170}
171
172/* Only one global & state struct ics */
173static struct ics ics_hal = {
174	.map		= ics_opal_map,
175	.mask_unknown	= ics_opal_mask_unknown,
176	.get_server	= ics_opal_get_server,
177	.host_match	= ics_opal_host_match,
178};
179
180static int ics_opal_map(struct ics *ics, unsigned int virq)
181{
182	unsigned int hw_irq = (unsigned int)virq_to_hw(virq);
183	int64_t rc;
184	int16_t server;
185	int8_t priority;
186
187	if (WARN_ON(hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS))
188		return -EINVAL;
189
190	/* Check if HAL knows about this interrupt */
191	rc = opal_get_xive(hw_irq, &server, &priority);
192	if (rc != OPAL_SUCCESS)
193		return -ENXIO;
194
195	irq_set_chip_and_handler(virq, &ics_opal_irq_chip, handle_fasteoi_irq);
196	irq_set_chip_data(virq, &ics_hal);
197
198	return 0;
199}
200
201static void ics_opal_mask_unknown(struct ics *ics, unsigned long vec)
202{
203	int64_t rc;
204	int16_t server;
205	int8_t priority;
206
207	/* Check if HAL knows about this interrupt */
208	rc = opal_get_xive(vec, &server, &priority);
209	if (rc != OPAL_SUCCESS)
210		return;
211
212	ics_opal_mask_real_irq(vec);
213}
214
215static long ics_opal_get_server(struct ics *ics, unsigned long vec)
216{
217	int64_t rc;
218	int16_t server;
219	int8_t priority;
220
221	/* Check if HAL knows about this interrupt */
222	rc = opal_get_xive(vec, &server, &priority);
223	if (rc != OPAL_SUCCESS)
224		return -1;
225	return ics_opal_unmangle_server(server);
226}
227
228int __init ics_opal_init(void)
229{
230	if (!firmware_has_feature(FW_FEATURE_OPAL))
231		return -ENODEV;
232
233	/* We need to patch our irq chip's EOI to point to the
234	 * right ICP
235	 */
236	ics_opal_irq_chip.irq_eoi = icp_ops->eoi;
237
238	/* Register ourselves */
239	xics_register_ics(&ics_hal);
240
241	pr_info("ICS OPAL backend registered\n");
242
243	return 0;
244}

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * ICS backend for OPAL managed interrupts.
  4 *
  5 * Copyright 2011 IBM Corp.
 
 
 
 
 
  6 */
  7
  8#undef DEBUG
  9
 10#include <linux/types.h>
 11#include <linux/kernel.h>
 12#include <linux/irq.h>
 13#include <linux/smp.h>
 14#include <linux/interrupt.h>
 15#include <linux/init.h>
 16#include <linux/cpu.h>
 17#include <linux/of.h>
 18#include <linux/spinlock.h>
 19#include <linux/msi.h>
 20
 21#include <asm/prom.h>
 22#include <asm/smp.h>
 23#include <asm/machdep.h>
 24#include <asm/irq.h>
 25#include <asm/errno.h>
 26#include <asm/xics.h>
 27#include <asm/opal.h>
 28#include <asm/firmware.h>
 29
 30static int ics_opal_mangle_server(int server)
 31{
 32	/* No link for now */
 33	return server << 2;
 34}
 35
 36static int ics_opal_unmangle_server(int server)
 37{
 38	/* No link for now */
 39	return server >> 2;
 40}
 41
 42static void ics_opal_unmask_irq(struct irq_data *d)
 43{
 44	unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
 45	int64_t rc;
 46	int server;
 47
 48	pr_devel("ics-hal: unmask virq %d [hw 0x%x]\n", d->irq, hw_irq);
 49
 50	if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
 51		return;
 52
 53	server = xics_get_irq_server(d->irq, irq_data_get_affinity_mask(d), 0);
 54	server = ics_opal_mangle_server(server);
 55
 56	rc = opal_set_xive(hw_irq, server, DEFAULT_PRIORITY);
 57	if (rc != OPAL_SUCCESS)
 58		pr_err("%s: opal_set_xive(irq=%d [hw 0x%x] server=%x)"
 59		       " error %lld\n",
 60		       __func__, d->irq, hw_irq, server, rc);
 61}
 62
 63static unsigned int ics_opal_startup(struct irq_data *d)
 64{
 65#ifdef CONFIG_PCI_MSI
 66	/*
 67	 * The generic MSI code returns with the interrupt disabled on the
 68	 * card, using the MSI mask bits. Firmware doesn't appear to unmask
 69	 * at that level, so we do it here by hand.
 70	 */
 71	if (irq_data_get_msi_desc(d))
 72		pci_msi_unmask_irq(d);
 73#endif
 74
 75	/* unmask it */
 76	ics_opal_unmask_irq(d);
 77	return 0;
 78}
 79
 80static void ics_opal_mask_real_irq(unsigned int hw_irq)
 81{
 82	int server = ics_opal_mangle_server(xics_default_server);
 83	int64_t rc;
 84
 85	if (hw_irq == XICS_IPI)
 86		return;
 87
 88	/* Have to set XIVE to 0xff to be able to remove a slot */
 89	rc = opal_set_xive(hw_irq, server, 0xff);
 90	if (rc != OPAL_SUCCESS)
 91		pr_err("%s: opal_set_xive(0xff) irq=%u returned %lld\n",
 92		       __func__, hw_irq, rc);
 93}
 94
 95static void ics_opal_mask_irq(struct irq_data *d)
 96{
 97	unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
 98
 99	pr_devel("ics-hal: mask virq %d [hw 0x%x]\n", d->irq, hw_irq);
100
101	if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
102		return;
103	ics_opal_mask_real_irq(hw_irq);
104}
105
106static int ics_opal_set_affinity(struct irq_data *d,
107				 const struct cpumask *cpumask,
108				 bool force)
109{
110	unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
111	__be16 oserver;
112	int16_t server;
113	int8_t priority;
114	int64_t rc;
115	int wanted_server;
116
117	if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
118		return -1;
119
120	rc = opal_get_xive(hw_irq, &oserver, &priority);
121	if (rc != OPAL_SUCCESS) {
122		pr_err("%s: opal_get_xive(irq=%d [hw 0x%x]) error %lld\n",
123		       __func__, d->irq, hw_irq, rc);
 
124		return -1;
125	}
126	server = be16_to_cpu(oserver);
127
128	wanted_server = xics_get_irq_server(d->irq, cpumask, 1);
129	if (wanted_server < 0) {
130		pr_warn("%s: No online cpus in the mask %*pb for irq %d\n",
131			__func__, cpumask_pr_args(cpumask), d->irq);
 
 
132		return -1;
133	}
134	server = ics_opal_mangle_server(wanted_server);
135
136	pr_devel("ics-hal: set-affinity irq %d [hw 0x%x] server: 0x%x/0x%x\n",
137		 d->irq, hw_irq, wanted_server, server);
138
139	rc = opal_set_xive(hw_irq, server, priority);
140	if (rc != OPAL_SUCCESS) {
141		pr_err("%s: opal_set_xive(irq=%d [hw 0x%x] server=%x)"
142		       " error %lld\n",
143		       __func__, d->irq, hw_irq, server, rc);
144		return -1;
145	}
146	return IRQ_SET_MASK_OK;
147}
148
149static struct irq_chip ics_opal_irq_chip = {
150	.name = "OPAL ICS",
151	.irq_startup = ics_opal_startup,
152	.irq_mask = ics_opal_mask_irq,
153	.irq_unmask = ics_opal_unmask_irq,
154	.irq_eoi = NULL, /* Patched at init time */
155	.irq_set_affinity = ics_opal_set_affinity,
156	.irq_set_type = xics_set_irq_type,
157	.irq_retrigger = xics_retrigger,
158};
159
160static int ics_opal_map(struct ics *ics, unsigned int virq);
161static void ics_opal_mask_unknown(struct ics *ics, unsigned long vec);
162static long ics_opal_get_server(struct ics *ics, unsigned long vec);
163
164static int ics_opal_host_match(struct ics *ics, struct device_node *node)
165{
166	return 1;
167}
168
169/* Only one global & state struct ics */
170static struct ics ics_hal = {
171	.map		= ics_opal_map,
172	.mask_unknown	= ics_opal_mask_unknown,
173	.get_server	= ics_opal_get_server,
174	.host_match	= ics_opal_host_match,
175};
176
177static int ics_opal_map(struct ics *ics, unsigned int virq)
178{
179	unsigned int hw_irq = (unsigned int)virq_to_hw(virq);
180	int64_t rc;
181	__be16 server;
182	int8_t priority;
183
184	if (WARN_ON(hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS))
185		return -EINVAL;
186
187	/* Check if HAL knows about this interrupt */
188	rc = opal_get_xive(hw_irq, &server, &priority);
189	if (rc != OPAL_SUCCESS)
190		return -ENXIO;
191
192	irq_set_chip_and_handler(virq, &ics_opal_irq_chip, handle_fasteoi_irq);
193	irq_set_chip_data(virq, &ics_hal);
194
195	return 0;
196}
197
198static void ics_opal_mask_unknown(struct ics *ics, unsigned long vec)
199{
200	int64_t rc;
201	__be16 server;
202	int8_t priority;
203
204	/* Check if HAL knows about this interrupt */
205	rc = opal_get_xive(vec, &server, &priority);
206	if (rc != OPAL_SUCCESS)
207		return;
208
209	ics_opal_mask_real_irq(vec);
210}
211
212static long ics_opal_get_server(struct ics *ics, unsigned long vec)
213{
214	int64_t rc;
215	__be16 server;
216	int8_t priority;
217
218	/* Check if HAL knows about this interrupt */
219	rc = opal_get_xive(vec, &server, &priority);
220	if (rc != OPAL_SUCCESS)
221		return -1;
222	return ics_opal_unmangle_server(be16_to_cpu(server));
223}
224
225int __init ics_opal_init(void)
226{
227	if (!firmware_has_feature(FW_FEATURE_OPAL))
228		return -ENODEV;
229
230	/* We need to patch our irq chip's EOI to point to the
231	 * right ICP
232	 */
233	ics_opal_irq_chip.irq_eoi = icp_ops->eoi;
234
235	/* Register ourselves */
236	xics_register_ics(&ics_hal);
237
238	pr_info("ICS OPAL backend registered\n");
239
240	return 0;
241}