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1/*
2 * arch/arm/mach-omap2/control.h
3 *
4 * OMAP2/3/4 System Control Module definitions
5 *
6 * Copyright (C) 2007-2010 Texas Instruments, Inc.
7 * Copyright (C) 2007-2008, 2010 Nokia Corporation
8 *
9 * Written by Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation.
14 */
15
16#ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H
17#define __ARCH_ARM_MACH_OMAP2_CONTROL_H
18
19#include <mach/ctrl_module_core_44xx.h>
20#include <mach/ctrl_module_wkup_44xx.h>
21#include <mach/ctrl_module_pad_core_44xx.h>
22#include <mach/ctrl_module_pad_wkup_44xx.h>
23
24#ifndef __ASSEMBLY__
25#define OMAP242X_CTRL_REGADDR(reg) \
26 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
27#define OMAP243X_CTRL_REGADDR(reg) \
28 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
29#define OMAP343X_CTRL_REGADDR(reg) \
30 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
31#else
32#define OMAP242X_CTRL_REGADDR(reg) \
33 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
34#define OMAP243X_CTRL_REGADDR(reg) \
35 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
36#define OMAP343X_CTRL_REGADDR(reg) \
37 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
38#endif /* __ASSEMBLY__ */
39
40/*
41 * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
42 * OMAP24XX and OMAP34XX.
43 */
44
45/* Control submodule offsets */
46
47#define OMAP2_CONTROL_INTERFACE 0x000
48#define OMAP2_CONTROL_PADCONFS 0x030
49#define OMAP2_CONTROL_GENERAL 0x270
50#define OMAP343X_CONTROL_MEM_WKUP 0x600
51#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
52#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
53
54/* TI81XX spefic control submodules */
55#define TI81XX_CONTROL_DEVCONF 0x600
56
57/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
58
59#define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10)
60
61/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
62#define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004)
63#define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020)
64#define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024)
65#define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028)
66#define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c)
67#define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030)
68#define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034)
69#define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040)
70#define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090)
71#define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094)
72#define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098)
73#define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c)
74
75/* 242x-only CONTROL_GENERAL register offsets */
76#define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */
77#define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068)
78
79/* 243x-only CONTROL_GENERAL register offsets */
80/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
81#define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078)
82#define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c)
83#define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
84#define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
85#define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198)
86#define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230)
87
88/* 24xx-only CONTROL_GENERAL register offsets */
89#define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000)
90#define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008)
91#define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044)
92#define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048)
93#define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c)
94#define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050)
95#define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060)
96#define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064)
97#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c)
98#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070)
99#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074)
100#define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
101#define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
102#define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088)
103#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c)
104#define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0)
105#define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4)
106#define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8)
107#define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac)
108#define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0)
109#define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4)
110#define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0)
111#define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4)
112#define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8)
113#define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc)
114#define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0)
115#define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4)
116#define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8)
117#define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc)
118#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0)
119#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4)
120
121#define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
122
123/* 34xx-only CONTROL_GENERAL register offsets */
124#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000)
125#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008)
126#define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c)
127#define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068)
128#define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c)
129#define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070)
130#define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074)
131#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078)
132#define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
133#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
134#define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0)
135#define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8)
136#define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac)
137#define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0)
138#define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4)
139#define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8)
140#define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc)
141#define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0)
142#define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4)
143#define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8)
144#define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc)
145#define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0)
146#define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4)
147#define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8)
148#define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec)
149#define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0)
150#define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4)
151#define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8)
152#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
153#define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110)
154#define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114)
155#define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118)
156#define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c)
157#define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120)
158#define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124)
159#define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128)
160#define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c)
161#define OMAP343X_CONTROL_FUSE_SR (OMAP2_CONTROL_GENERAL + 0x0130)
162#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
163#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
164#define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \
165 + ((i) >> 1) * 4 + (!((i) & 1)) * 2)
166#define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4)
167#define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8)
168#define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0)
169#define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4)
170#define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8)
171#define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC)
172#define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0)
173#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4)
174#define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8)
175#define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0)
176#define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4)
177
178/* OMAP3630 only CONTROL_GENERAL register offsets */
179#define OMAP3630_CONTROL_FUSE_OPP1G_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110)
180#define OMAP3630_CONTROL_FUSE_OPP50_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114)
181#define OMAP3630_CONTROL_FUSE_OPP100_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118)
182#define OMAP3630_CONTROL_FUSE_OPP120_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120)
183#define OMAP3630_CONTROL_FUSE_OPP50_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128)
184#define OMAP3630_CONTROL_FUSE_OPP100_VDD2 (OMAP2_CONTROL_GENERAL + 0x012C)
185
186/* OMAP44xx control efuse offsets */
187#define OMAP44XX_CONTROL_FUSE_IVA_OPP50 0x22C
188#define OMAP44XX_CONTROL_FUSE_IVA_OPP100 0x22F
189#define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO 0x232
190#define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO 0x235
191#define OMAP44XX_CONTROL_FUSE_MPU_OPP50 0x240
192#define OMAP44XX_CONTROL_FUSE_MPU_OPP100 0x243
193#define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO 0x246
194#define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO 0x249
195#define OMAP44XX_CONTROL_FUSE_CORE_OPP50 0x254
196#define OMAP44XX_CONTROL_FUSE_CORE_OPP100 0x257
197
198/* AM35XX only CONTROL_GENERAL register offsets */
199#define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038)
200#define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310)
201#define AM35XX_CONTROL_DEVCONF3 (OMAP2_CONTROL_GENERAL + 0x0314)
202#define AM35XX_CONTROL_CBA_PRIORITY (OMAP2_CONTROL_GENERAL + 0x0320)
203#define AM35XX_CONTROL_LVL_INTR_CLEAR (OMAP2_CONTROL_GENERAL + 0x0324)
204#define AM35XX_CONTROL_IP_SW_RESET (OMAP2_CONTROL_GENERAL + 0x0328)
205#define AM35XX_CONTROL_IPSS_CLK_CTRL (OMAP2_CONTROL_GENERAL + 0x032C)
206
207/* 34xx PADCONF register offsets */
208#define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \
209 (i)*2)
210#define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0)
211#define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1)
212#define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2)
213#define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3)
214#define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4)
215#define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5)
216#define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6)
217#define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7)
218#define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8)
219#define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9)
220#define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10)
221#define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11)
222#define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12)
223#define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13)
224#define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14)
225#define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15)
226#define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16)
227#define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17)
228
229/* 34xx GENERAL_WKUP regist offsets */
230#define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \
231 0x008 + (i))
232#define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008)
233#define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C)
234#define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010)
235#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
236#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
237
238/* 36xx-only RTA - Retention till Access control registers and bits */
239#define OMAP36XX_CONTROL_MEM_RTA_CTRL 0x40C
240#define OMAP36XX_RTA_DISABLE 0x0
241
242/* 34xx D2D idle-related pins, handled by PM core */
243#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
244#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
245
246/* TI81XX CONTROL_DEVCONF register offsets */
247#define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000)
248
249/*
250 * REVISIT: This list of registers is not comprehensive - there are more
251 * that should be added.
252 */
253
254/*
255 * Control module register bit defines - these should eventually go into
256 * their own regbits file. Some of these will be complicated, depending
257 * on the device type (general-purpose, emulator, test, secure, bad, other)
258 * and the security mode (secure, non-secure, don't care)
259 */
260/* CONTROL_DEVCONF0 bits */
261#define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */
262#define OMAP24XX_USBSTANDBYCTRL (1 << 15)
263#define OMAP2_MCBSP2_CLKS_MASK (1 << 6)
264#define OMAP2_MCBSP1_FSR_MASK (1 << 4)
265#define OMAP2_MCBSP1_CLKR_MASK (1 << 3)
266#define OMAP2_MCBSP1_CLKS_MASK (1 << 2)
267
268/* CONTROL_DEVCONF1 bits */
269#define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31)
270#define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */
271#define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */
272#define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */
273#define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */
274
275/* CONTROL_STATUS bits */
276#define OMAP2_DEVICETYPE_MASK (0x7 << 8)
277#define OMAP2_SYSBOOT_5_MASK (1 << 5)
278#define OMAP2_SYSBOOT_4_MASK (1 << 4)
279#define OMAP2_SYSBOOT_3_MASK (1 << 3)
280#define OMAP2_SYSBOOT_2_MASK (1 << 2)
281#define OMAP2_SYSBOOT_1_MASK (1 << 1)
282#define OMAP2_SYSBOOT_0_MASK (1 << 0)
283
284/* CONTROL_PBIAS_LITE bits */
285#define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15)
286#define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11)
287#define OMAP343X_PBIASSPEEDCTRL1 (1 << 10)
288#define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9)
289#define OMAP343X_PBIASLITEVMODE1 (1 << 8)
290#define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7)
291#define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3)
292#define OMAP2_PBIASSPEEDCTRL0 (1 << 2)
293#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
294#define OMAP2_PBIASLITEVMODE0 (1 << 0)
295
296/* CONTROL_PROG_IO1 bits */
297#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20)
298
299/* CONTROL_IVA2_BOOTMOD bits */
300#define OMAP3_IVA2_BOOTMOD_SHIFT 0
301#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0)
302#define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0)
303
304/* CONTROL_PADCONF_X bits */
305#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15)
306#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14)
307
308#define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860)
309#define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910)
310#define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C
311#define OMAP343X_SCRATCHPAD_REGADDR(reg) OMAP2_L4_IO_ADDRESS(\
312 OMAP343X_SCRATCHPAD + reg)
313
314/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
315#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0
316#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1
317#define AM35XX_VPFE_VBUSP_CLK_SHIFT 2
318#define AM35XX_HECC_VBUSP_CLK_SHIFT 3
319#define AM35XX_USBOTG_FCLK_SHIFT 8
320#define AM35XX_CPGMAC_FCLK_SHIFT 9
321#define AM35XX_VPFE_FCLK_SHIFT 10
322
323/*AM35XX CONTROL_LVL_INTR_CLEAR bits*/
324#define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0)
325#define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1)
326#define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2)
327#define AM35XX_CPGMAC_C0_TX_PULSE_CLR BIT(3)
328#define AM35XX_USBOTGSS_INT_CLR BIT(4)
329#define AM35XX_VPFE_CCDC_VD0_INT_CLR BIT(5)
330#define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6)
331#define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7)
332
333/*AM35XX CONTROL_IP_SW_RESET bits*/
334#define AM35XX_USBOTGSS_SW_RST BIT(0)
335#define AM35XX_CPGMACSS_SW_RST BIT(1)
336#define AM35XX_VPFE_VBUSP_SW_RST BIT(2)
337#define AM35XX_HECC_SW_RST BIT(3)
338#define AM35XX_VPFE_PCLK_SW_RST BIT(4)
339
340/*
341 * CONTROL AM33XX STATUS register
342 */
343#define AM33XX_CONTROL_STATUS 0x040
344
345/*
346 * CONTROL OMAP STATUS register to identify OMAP3 features
347 */
348#define OMAP3_CONTROL_OMAP_STATUS 0x044c
349
350#define OMAP3_SGX_SHIFT 13
351#define OMAP3_SGX_MASK (3 << OMAP3_SGX_SHIFT)
352#define FEAT_SGX_FULL 0
353#define FEAT_SGX_HALF 1
354#define FEAT_SGX_NONE 2
355
356#define OMAP3_IVA_SHIFT 12
357#define OMAP3_IVA_MASK (1 << OMAP3_IVA_SHIFT)
358#define FEAT_IVA 0
359#define FEAT_IVA_NONE 1
360
361#define OMAP3_L2CACHE_SHIFT 10
362#define OMAP3_L2CACHE_MASK (3 << OMAP3_L2CACHE_SHIFT)
363#define FEAT_L2CACHE_NONE 0
364#define FEAT_L2CACHE_64KB 1
365#define FEAT_L2CACHE_128KB 2
366#define FEAT_L2CACHE_256KB 3
367
368#define OMAP3_ISP_SHIFT 5
369#define OMAP3_ISP_MASK (1 << OMAP3_ISP_SHIFT)
370#define FEAT_ISP 0
371#define FEAT_ISP_NONE 1
372
373#define OMAP3_NEON_SHIFT 4
374#define OMAP3_NEON_MASK (1 << OMAP3_NEON_SHIFT)
375#define FEAT_NEON 0
376#define FEAT_NEON_NONE 1
377
378
379#ifndef __ASSEMBLY__
380#ifdef CONFIG_ARCH_OMAP2PLUS
381extern void __iomem *omap_ctrl_base_get(void);
382extern u8 omap_ctrl_readb(u16 offset);
383extern u16 omap_ctrl_readw(u16 offset);
384extern u32 omap_ctrl_readl(u16 offset);
385extern u32 omap4_ctrl_pad_readl(u16 offset);
386extern void omap_ctrl_writeb(u8 val, u16 offset);
387extern void omap_ctrl_writew(u16 val, u16 offset);
388extern void omap_ctrl_writel(u32 val, u16 offset);
389extern void omap4_ctrl_pad_writel(u32 val, u16 offset);
390
391extern void omap3_save_scratchpad_contents(void);
392extern void omap3_clear_scratchpad_contents(void);
393extern void omap3_restore(void);
394extern void omap3_restore_es3(void);
395extern void omap3_restore_3630(void);
396extern u32 omap3_arm_context[128];
397extern void omap3_control_save_context(void);
398extern void omap3_control_restore_context(void);
399extern void omap3_ctrl_write_boot_mode(u8 bootmode);
400extern void omap3630_ctrl_disable_rta(void);
401extern int omap3_ctrl_save_padconf(void);
402#else
403#define omap_ctrl_base_get() 0
404#define omap_ctrl_readb(x) 0
405#define omap_ctrl_readw(x) 0
406#define omap_ctrl_readl(x) 0
407#define omap4_ctrl_pad_readl(x) 0
408#define omap_ctrl_writeb(x, y) WARN_ON(1)
409#define omap_ctrl_writew(x, y) WARN_ON(1)
410#define omap_ctrl_writel(x, y) WARN_ON(1)
411#define omap4_ctrl_pad_writel(x, y) WARN_ON(1)
412#endif
413#endif /* __ASSEMBLY__ */
414
415#endif /* __ARCH_ARM_MACH_OMAP2_CONTROL_H */
416
1/*
2 * arch/arm/mach-omap2/control.h
3 *
4 * OMAP2/3/4 System Control Module definitions
5 *
6 * Copyright (C) 2007-2010 Texas Instruments, Inc.
7 * Copyright (C) 2007-2008, 2010 Nokia Corporation
8 *
9 * Written by Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation.
14 */
15
16#ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H
17#define __ARCH_ARM_MACH_OMAP2_CONTROL_H
18
19#include "am33xx.h"
20
21#ifndef __ASSEMBLY__
22#define OMAP242X_CTRL_REGADDR(reg) \
23 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
24#define OMAP243X_CTRL_REGADDR(reg) \
25 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
26#define OMAP343X_CTRL_REGADDR(reg) \
27 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
28#define AM33XX_CTRL_REGADDR(reg) \
29 AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
30#else
31#define OMAP242X_CTRL_REGADDR(reg) \
32 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
33#define OMAP243X_CTRL_REGADDR(reg) \
34 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
35#define OMAP343X_CTRL_REGADDR(reg) \
36 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
37#define AM33XX_CTRL_REGADDR(reg) \
38 AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
39#endif /* __ASSEMBLY__ */
40
41/*
42 * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
43 * OMAP24XX and OMAP34XX.
44 */
45
46/* Control submodule offsets */
47
48#define OMAP2_CONTROL_INTERFACE 0x000
49#define OMAP2_CONTROL_PADCONFS 0x030
50#define OMAP2_CONTROL_GENERAL 0x270
51#define OMAP343X_CONTROL_MEM_WKUP 0x600
52#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
53#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
54
55/* TI81XX spefic control submodules */
56#define TI81XX_CONTROL_DEVBOOT 0x040
57#define TI81XX_CONTROL_DEVCONF 0x600
58
59/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
60
61#define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10)
62
63/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
64#define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004)
65#define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020)
66#define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024)
67#define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028)
68#define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c)
69#define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030)
70#define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034)
71#define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040)
72#define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090)
73#define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094)
74#define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098)
75#define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c)
76
77/* 242x-only CONTROL_GENERAL register offsets */
78#define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */
79#define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068)
80
81/* 243x-only CONTROL_GENERAL register offsets */
82/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
83#define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078)
84#define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c)
85#define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
86#define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
87#define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198)
88#define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230)
89
90/* 24xx-only CONTROL_GENERAL register offsets */
91#define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000)
92#define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008)
93#define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044)
94#define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048)
95#define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c)
96#define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050)
97#define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060)
98#define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064)
99#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c)
100#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070)
101#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074)
102#define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
103#define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
104#define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088)
105#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c)
106#define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0)
107#define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4)
108#define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8)
109#define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac)
110#define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0)
111#define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4)
112#define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0)
113#define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4)
114#define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8)
115#define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc)
116#define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0)
117#define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4)
118#define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8)
119#define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc)
120#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0)
121#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4)
122
123#define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
124
125/* 34xx-only CONTROL_GENERAL register offsets */
126#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000)
127#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008)
128#define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c)
129#define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068)
130#define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c)
131#define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070)
132#define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074)
133#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078)
134#define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
135#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
136#define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0)
137#define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8)
138#define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac)
139#define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0)
140#define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4)
141#define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8)
142#define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc)
143#define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0)
144#define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4)
145#define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8)
146#define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc)
147#define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0)
148#define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4)
149#define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8)
150#define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec)
151#define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0)
152#define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4)
153#define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8)
154#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
155#define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110)
156#define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114)
157#define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118)
158#define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c)
159#define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120)
160#define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124)
161#define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128)
162#define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c)
163#define OMAP343X_CONTROL_FUSE_SR (OMAP2_CONTROL_GENERAL + 0x0130)
164#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
165#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
166#define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \
167 + ((i) >> 1) * 4 + (!((i) & 1)) * 2)
168#define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4)
169#define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8)
170#define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0)
171#define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4)
172#define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8)
173#define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC)
174#define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0)
175#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4)
176#define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8)
177#define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0)
178#define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4)
179
180/* OMAP3630 only CONTROL_GENERAL register offsets */
181#define OMAP3630_CONTROL_FUSE_OPP1G_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110)
182#define OMAP3630_CONTROL_FUSE_OPP50_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114)
183#define OMAP3630_CONTROL_FUSE_OPP100_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118)
184#define OMAP3630_CONTROL_FUSE_OPP120_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120)
185#define OMAP3630_CONTROL_FUSE_OPP50_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128)
186#define OMAP3630_CONTROL_FUSE_OPP100_VDD2 (OMAP2_CONTROL_GENERAL + 0x012C)
187#define OMAP3630_CONTROL_CAMERA_PHY_CTRL (OMAP2_CONTROL_GENERAL + 0x02f0)
188
189/* OMAP44xx control efuse offsets */
190#define OMAP44XX_CONTROL_FUSE_IVA_OPP50 0x22C
191#define OMAP44XX_CONTROL_FUSE_IVA_OPP100 0x22F
192#define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO 0x232
193#define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO 0x235
194#define OMAP44XX_CONTROL_FUSE_MPU_OPP50 0x240
195#define OMAP44XX_CONTROL_FUSE_MPU_OPP100 0x243
196#define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO 0x246
197#define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO 0x249
198#define OMAP44XX_CONTROL_FUSE_CORE_OPP50 0x254
199#define OMAP44XX_CONTROL_FUSE_CORE_OPP100 0x257
200#define OMAP44XX_CONTROL_FUSE_CORE_OPP100OV 0x25A
201
202/* AM35XX only CONTROL_GENERAL register offsets */
203#define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038)
204#define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310)
205#define AM35XX_CONTROL_DEVCONF3 (OMAP2_CONTROL_GENERAL + 0x0314)
206#define AM35XX_CONTROL_CBA_PRIORITY (OMAP2_CONTROL_GENERAL + 0x0320)
207#define AM35XX_CONTROL_LVL_INTR_CLEAR (OMAP2_CONTROL_GENERAL + 0x0324)
208#define AM35XX_CONTROL_IP_SW_RESET (OMAP2_CONTROL_GENERAL + 0x0328)
209#define AM35XX_CONTROL_IPSS_CLK_CTRL (OMAP2_CONTROL_GENERAL + 0x032C)
210
211/* 34xx PADCONF register offsets */
212#define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \
213 (i)*2)
214#define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0)
215#define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1)
216#define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2)
217#define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3)
218#define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4)
219#define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5)
220#define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6)
221#define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7)
222#define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8)
223#define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9)
224#define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10)
225#define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11)
226#define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12)
227#define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13)
228#define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14)
229#define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15)
230#define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16)
231#define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17)
232
233/* 34xx GENERAL_WKUP register offsets */
234#define OMAP34XX_CONTROL_WKUP_CTRL (OMAP343X_CONTROL_GENERAL_WKUP - 0x4)
235#define OMAP36XX_GPIO_IO_PWRDNZ BIT(6)
236
237#define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \
238 0x008 + (i))
239#define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008)
240#define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C)
241#define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010)
242#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
243#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
244
245/* 36xx-only RTA - Retention till Access control registers and bits */
246#define OMAP36XX_CONTROL_MEM_RTA_CTRL 0x40C
247#define OMAP36XX_RTA_DISABLE 0x0
248
249/* 34xx D2D idle-related pins, handled by PM core */
250#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
251#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
252
253/* TI81XX CONTROL_DEVBOOT register offsets */
254#define TI81XX_CONTROL_STATUS (TI81XX_CONTROL_DEVBOOT + 0x000)
255
256/* TI81XX CONTROL_DEVCONF register offsets */
257#define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000)
258
259/* OMAP4 CONTROL MODULE */
260#define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000
261#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604
262#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4
263#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218
264#define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR 0x0304
265#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618
266#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX 0x0608
267
268/* OMAP4 CONTROL_DSIPHY */
269#define OMAP4_DSI2_LANEENABLE_SHIFT 29
270#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
271#define OMAP4_DSI1_LANEENABLE_SHIFT 24
272#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
273#define OMAP4_DSI1_PIPD_SHIFT 19
274#define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
275#define OMAP4_DSI2_PIPD_SHIFT 14
276#define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
277
278/* OMAP4 CONTROL_CAMERA_RX */
279#define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT 24
280#define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK (0x1f << 24)
281#define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT 29
282#define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK (0x3 << 29)
283#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT 21
284#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK (1 << 21)
285#define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT 19
286#define OMAP4_CAMERARX_CSI22_CAMMODE_MASK (0x3 << 19)
287#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT 18
288#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK (1 << 18)
289#define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT 16
290#define OMAP4_CAMERARX_CSI21_CAMMODE_MASK (0x3 << 16)
291
292/* OMAP54XX CONTROL STATUS register */
293#define OMAP5XXX_CONTROL_STATUS 0x134
294#define OMAP5_DEVICETYPE_MASK (0x7 << 6)
295
296/* DRA7XX CONTROL CORE BOOTSTRAP */
297#define DRA7_CTRL_CORE_BOOTSTRAP 0x6c4
298#define DRA7_SPEEDSELECT_MASK (0x3 << 8)
299
300/*
301 * REVISIT: This list of registers is not comprehensive - there are more
302 * that should be added.
303 */
304
305/*
306 * Control module register bit defines - these should eventually go into
307 * their own regbits file. Some of these will be complicated, depending
308 * on the device type (general-purpose, emulator, test, secure, bad, other)
309 * and the security mode (secure, non-secure, don't care)
310 */
311/* CONTROL_DEVCONF0 bits */
312#define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */
313#define OMAP24XX_USBSTANDBYCTRL (1 << 15)
314#define OMAP2_MCBSP2_CLKS_MASK (1 << 6)
315#define OMAP2_MCBSP1_FSR_MASK (1 << 4)
316#define OMAP2_MCBSP1_CLKR_MASK (1 << 3)
317#define OMAP2_MCBSP1_CLKS_MASK (1 << 2)
318
319/* CONTROL_DEVCONF1 bits */
320#define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31)
321#define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */
322#define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */
323#define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */
324#define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */
325
326/* CONTROL_STATUS bits */
327#define OMAP2_DEVICETYPE_MASK (0x7 << 8)
328#define OMAP2_SYSBOOT_5_MASK (1 << 5)
329#define OMAP2_SYSBOOT_4_MASK (1 << 4)
330#define OMAP2_SYSBOOT_3_MASK (1 << 3)
331#define OMAP2_SYSBOOT_2_MASK (1 << 2)
332#define OMAP2_SYSBOOT_1_MASK (1 << 1)
333#define OMAP2_SYSBOOT_0_MASK (1 << 0)
334
335/* CONTROL_PBIAS_LITE bits */
336#define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15)
337#define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11)
338#define OMAP343X_PBIASSPEEDCTRL1 (1 << 10)
339#define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9)
340#define OMAP343X_PBIASLITEVMODE1 (1 << 8)
341#define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7)
342#define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3)
343#define OMAP2_PBIASSPEEDCTRL0 (1 << 2)
344#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
345#define OMAP2_PBIASLITEVMODE0 (1 << 0)
346
347/* CONTROL_PROG_IO1 bits */
348#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20)
349
350/* CONTROL_IVA2_BOOTMOD bits */
351#define OMAP3_IVA2_BOOTMOD_SHIFT 0
352#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0)
353#define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0)
354
355/* CONTROL_PADCONF_X bits */
356#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15)
357#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14)
358
359#define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860)
360#define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910)
361#define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C
362#define OMAP343X_SCRATCHPAD_REGADDR(reg) OMAP2_L4_IO_ADDRESS(\
363 OMAP343X_SCRATCHPAD + reg)
364
365/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
366#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0
367#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1
368#define AM35XX_VPFE_VBUSP_CLK_SHIFT 2
369#define AM35XX_HECC_VBUSP_CLK_SHIFT 3
370#define AM35XX_USBOTG_FCLK_SHIFT 8
371#define AM35XX_CPGMAC_FCLK_SHIFT 9
372#define AM35XX_VPFE_FCLK_SHIFT 10
373
374/* AM35XX CONTROL_LVL_INTR_CLEAR bits */
375#define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0)
376#define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1)
377#define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2)
378#define AM35XX_CPGMAC_C0_TX_PULSE_CLR BIT(3)
379#define AM35XX_USBOTGSS_INT_CLR BIT(4)
380#define AM35XX_VPFE_CCDC_VD0_INT_CLR BIT(5)
381#define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6)
382#define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7)
383
384/* AM35XX CONTROL_IP_SW_RESET bits */
385#define AM35XX_USBOTGSS_SW_RST BIT(0)
386#define AM35XX_CPGMACSS_SW_RST BIT(1)
387#define AM35XX_VPFE_VBUSP_SW_RST BIT(2)
388#define AM35XX_HECC_SW_RST BIT(3)
389#define AM35XX_VPFE_PCLK_SW_RST BIT(4)
390
391/* AM33XX CONTROL_STATUS register */
392#define AM33XX_CONTROL_STATUS 0x040
393#define AM33XX_CONTROL_SEC_CLK_CTRL 0x1bc
394
395/* AM33XX CONTROL_STATUS bitfields (partial) */
396#define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT 22
397#define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH 0x2
398#define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22)
399
400/* AM33XX PWMSS Control register */
401#define AM33XX_PWMSS_TBCLK_CLKCTRL 0x664
402
403/* AM33XX PWMSS Control bitfields */
404#define AM33XX_PWMSS0_TBCLKEN_SHIFT 0
405#define AM33XX_PWMSS1_TBCLKEN_SHIFT 1
406#define AM33XX_PWMSS2_TBCLKEN_SHIFT 2
407
408/* DEV Feature register to identify AM33XX features */
409#define AM33XX_DEV_FEATURE 0x604
410#define AM33XX_SGX_MASK BIT(29)
411
412/* Additional AM33XX/AM43XX CONTROL registers */
413#define AM33XX_CONTROL_SYSCONFIG_OFFSET 0x0010
414#define AM33XX_CONTROL_STATUS_OFFSET 0x0040
415#define AM43XX_CONTROL_MPU_L2_CTRL_OFFSET 0x01e0
416#define AM33XX_CONTROL_CORTEX_VBBLDO_CTRL_OFFSET 0x041c
417#define AM33XX_CONTROL_CORE_SLDO_CTRL_OFFSET 0x0428
418#define AM33XX_CONTROL_MPU_SLDO_CTRL_OFFSET 0x042c
419#define AM33XX_CONTROL_CLK32KDIVRATIO_CTRL_OFFSET 0x0444
420#define AM33XX_CONTROL_BANDGAP_CTRL_OFFSET 0x0448
421#define AM33XX_CONTROL_BANDGAP_TRIM_OFFSET 0x044c
422#define AM33XX_CONTROL_PLL_CLKINPULOW_CTRL_OFFSET 0x0458
423#define AM33XX_CONTROL_MOSC_CTRL_OFFSET 0x0468
424#define AM33XX_CONTROL_RCOSC_CTRL_OFFSET 0x046c
425#define AM33XX_CONTROL_DEEPSLEEP_CTRL_OFFSET 0x0470
426#define AM43XX_CONTROL_DISPLAY_PLL_SEL_OFFSET 0x0534
427#define AM33XX_CONTROL_INIT_PRIORITY_0_OFFSET 0x0608
428#define AM33XX_CONTROL_INIT_PRIORITY_1_OFFSET 0x060c
429#define AM33XX_CONTROL_MMU_CFG_OFFSET 0x0610
430#define AM33XX_CONTROL_TPTC_CFG_OFFSET 0x0614
431#define AM33XX_CONTROL_USB_CTRL0_OFFSET 0x0620
432#define AM33XX_CONTROL_USB_CTRL1_OFFSET 0x0628
433#define AM33XX_CONTROL_USB_WKUP_CTRL_OFFSET 0x0648
434#define AM43XX_CONTROL_USB_CTRL2_OFFSET 0x064c
435#define AM43XX_CONTROL_GMII_SEL_OFFSET 0x0650
436#define AM43XX_CONTROL_MPUSS_CTRL_OFFSET 0x0654
437#define AM43XX_CONTROL_TIMER_CASCADE_CTRL_OFFSET 0x0658
438#define AM43XX_CONTROL_PWMSS_CTRL_OFFSET 0x0664
439#define AM33XX_CONTROL_MREQPRIO_0_OFFSET 0x0670
440#define AM33XX_CONTROL_MREQPRIO_1_OFFSET 0x0674
441#define AM33XX_CONTROL_HW_EVENT_SEL_GRP1_OFFSET 0x0690
442#define AM33XX_CONTROL_HW_EVENT_SEL_GRP2_OFFSET 0x0694
443#define AM33XX_CONTROL_HW_EVENT_SEL_GRP3_OFFSET 0x0698
444#define AM33XX_CONTROL_HW_EVENT_SEL_GRP4_OFFSET 0x069c
445#define AM33XX_CONTROL_SMRT_CTRL_OFFSET 0x06a0
446#define AM33XX_CONTROL_MPUSS_HW_DEBUG_SEL_OFFSET 0x06a4
447#define AM43XX_CONTROL_CQDETECT_STS_OFFSET 0x0e00
448#define AM43XX_CONTROL_CQDETECT_STS2_OFFSET 0x0e08
449#define AM43XX_CONTROL_VTP_CTRL_OFFSET 0x0e0c
450#define AM33XX_CONTROL_VREF_CTRL_OFFSET 0x0e14
451#define AM33XX_CONTROL_TPCC_EVT_MUX_0_3_OFFSET 0x0f90
452#define AM33XX_CONTROL_TPCC_EVT_MUX_4_7_OFFSET 0x0f94
453#define AM33XX_CONTROL_TPCC_EVT_MUX_8_11_OFFSET 0x0f98
454#define AM33XX_CONTROL_TPCC_EVT_MUX_12_15_OFFSET 0x0f9c
455#define AM33XX_CONTROL_TPCC_EVT_MUX_16_19_OFFSET 0x0fa0
456#define AM33XX_CONTROL_TPCC_EVT_MUX_20_23_OFFSET 0x0fa4
457#define AM33XX_CONTROL_TPCC_EVT_MUX_24_27_OFFSET 0x0fa8
458#define AM33XX_CONTROL_TPCC_EVT_MUX_28_31_OFFSET 0x0fac
459#define AM33XX_CONTROL_TPCC_EVT_MUX_32_35_OFFSET 0x0fb0
460#define AM33XX_CONTROL_TPCC_EVT_MUX_36_39_OFFSET 0x0fb4
461#define AM33XX_CONTROL_TPCC_EVT_MUX_40_43_OFFSET 0x0fb8
462#define AM33XX_CONTROL_TPCC_EVT_MUX_44_47_OFFSET 0x0fbc
463#define AM33XX_CONTROL_TPCC_EVT_MUX_48_51_OFFSET 0x0fc0
464#define AM33XX_CONTROL_TPCC_EVT_MUX_52_55_OFFSET 0x0fc4
465#define AM33XX_CONTROL_TPCC_EVT_MUX_56_59_OFFSET 0x0fc8
466#define AM33XX_CONTROL_TPCC_EVT_MUX_60_63_OFFSET 0x0fcc
467#define AM33XX_CONTROL_TIMER_EVT_CAPT_OFFSET 0x0fd0
468#define AM33XX_CONTROL_ECAP_EVT_CAPT_OFFSET 0x0fd4
469#define AM33XX_CONTROL_ADC_EVT_CAPT_OFFSET 0x0fd8
470#define AM43XX_CONTROL_ADC1_EVT_CAPT_OFFSET 0x0fdc
471#define AM33XX_CONTROL_RESET_ISO_OFFSET 0x1000
472
473/* CONTROL OMAP STATUS register to identify OMAP3 features */
474#define OMAP3_CONTROL_OMAP_STATUS 0x044c
475
476#define OMAP3_SGX_SHIFT 13
477#define OMAP3_SGX_MASK (3 << OMAP3_SGX_SHIFT)
478#define FEAT_SGX_FULL 0
479#define FEAT_SGX_HALF 1
480#define FEAT_SGX_NONE 2
481
482#define OMAP3_IVA_SHIFT 12
483#define OMAP3_IVA_MASK (1 << OMAP3_IVA_SHIFT)
484#define FEAT_IVA 0
485#define FEAT_IVA_NONE 1
486
487#define OMAP3_L2CACHE_SHIFT 10
488#define OMAP3_L2CACHE_MASK (3 << OMAP3_L2CACHE_SHIFT)
489#define FEAT_L2CACHE_NONE 0
490#define FEAT_L2CACHE_64KB 1
491#define FEAT_L2CACHE_128KB 2
492#define FEAT_L2CACHE_256KB 3
493
494#define OMAP3_ISP_SHIFT 5
495#define OMAP3_ISP_MASK (1 << OMAP3_ISP_SHIFT)
496#define FEAT_ISP 0
497#define FEAT_ISP_NONE 1
498
499#define OMAP3_NEON_SHIFT 4
500#define OMAP3_NEON_MASK (1 << OMAP3_NEON_SHIFT)
501#define FEAT_NEON 0
502#define FEAT_NEON_NONE 1
503
504
505#ifndef __ASSEMBLY__
506#ifdef CONFIG_ARCH_OMAP2PLUS
507extern u8 omap_ctrl_readb(u16 offset);
508extern u16 omap_ctrl_readw(u16 offset);
509extern u32 omap_ctrl_readl(u16 offset);
510extern void omap_ctrl_writeb(u8 val, u16 offset);
511extern void omap_ctrl_writew(u16 val, u16 offset);
512extern void omap_ctrl_writel(u32 val, u16 offset);
513
514extern void omap3_save_scratchpad_contents(void);
515extern void omap3_clear_scratchpad_contents(void);
516extern void omap3_restore(void);
517extern void omap3_restore_es3(void);
518extern void omap3_restore_3630(void);
519extern u32 omap3_arm_context[128];
520extern void omap3_control_save_context(void);
521extern void omap3_control_restore_context(void);
522extern void omap3_ctrl_write_boot_mode(u8 bootmode);
523extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr);
524extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
525extern void omap3630_ctrl_disable_rta(void);
526extern int omap3_ctrl_save_padconf(void);
527void omap3_ctrl_init(void);
528int omap2_control_base_init(void);
529int omap_control_init(void);
530void omap2_set_globals_control(void __iomem *ctrl);
531void __init omap3_control_legacy_iomap_init(void);
532#else
533#define omap_ctrl_readb(x) 0
534#define omap_ctrl_readw(x) 0
535#define omap_ctrl_readl(x) 0
536#define omap4_ctrl_pad_readl(x) 0
537#define omap_ctrl_writeb(x, y) WARN_ON(1)
538#define omap_ctrl_writew(x, y) WARN_ON(1)
539#define omap_ctrl_writel(x, y) WARN_ON(1)
540#define omap4_ctrl_pad_writel(x, y) WARN_ON(1)
541#endif
542#endif /* __ASSEMBLY__ */
543
544#endif /* __ARCH_ARM_MACH_OMAP2_CONTROL_H */
545