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1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe_common.h"
33#include "ixgbe_phy.h"
34
35static void ixgbe_i2c_start(struct ixgbe_hw *hw);
36static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
37static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
38static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
39static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
40static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
41static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
42static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
43static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
44static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
45static bool ixgbe_get_i2c_data(u32 *i2cctl);
46static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
47static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
48static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
49
50/**
51 * ixgbe_identify_phy_generic - Get physical layer module
52 * @hw: pointer to hardware structure
53 *
54 * Determines the physical layer module found on the current adapter.
55 **/
56s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
57{
58 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
59 u32 phy_addr;
60 u16 ext_ability = 0;
61
62 if (hw->phy.type == ixgbe_phy_unknown) {
63 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
64 hw->phy.mdio.prtad = phy_addr;
65 if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
66 ixgbe_get_phy_id(hw);
67 hw->phy.type =
68 ixgbe_get_phy_type_from_id(hw->phy.id);
69
70 if (hw->phy.type == ixgbe_phy_unknown) {
71 hw->phy.ops.read_reg(hw,
72 MDIO_PMA_EXTABLE,
73 MDIO_MMD_PMAPMD,
74 &ext_ability);
75 if (ext_ability &
76 (MDIO_PMA_EXTABLE_10GBT |
77 MDIO_PMA_EXTABLE_1000BT))
78 hw->phy.type =
79 ixgbe_phy_cu_unknown;
80 else
81 hw->phy.type =
82 ixgbe_phy_generic;
83 }
84
85 status = 0;
86 break;
87 }
88 }
89 /* clear value if nothing found */
90 if (status != 0)
91 hw->phy.mdio.prtad = 0;
92 } else {
93 status = 0;
94 }
95
96 return status;
97}
98
99/**
100 * ixgbe_get_phy_id - Get the phy type
101 * @hw: pointer to hardware structure
102 *
103 **/
104static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
105{
106 u32 status;
107 u16 phy_id_high = 0;
108 u16 phy_id_low = 0;
109
110 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
111 &phy_id_high);
112
113 if (status == 0) {
114 hw->phy.id = (u32)(phy_id_high << 16);
115 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
116 &phy_id_low);
117 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
118 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
119 }
120 return status;
121}
122
123/**
124 * ixgbe_get_phy_type_from_id - Get the phy type
125 * @hw: pointer to hardware structure
126 *
127 **/
128static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
129{
130 enum ixgbe_phy_type phy_type;
131
132 switch (phy_id) {
133 case TN1010_PHY_ID:
134 phy_type = ixgbe_phy_tn;
135 break;
136 case X540_PHY_ID:
137 phy_type = ixgbe_phy_aq;
138 break;
139 case QT2022_PHY_ID:
140 phy_type = ixgbe_phy_qt;
141 break;
142 case ATH_PHY_ID:
143 phy_type = ixgbe_phy_nl;
144 break;
145 default:
146 phy_type = ixgbe_phy_unknown;
147 break;
148 }
149
150 return phy_type;
151}
152
153/**
154 * ixgbe_reset_phy_generic - Performs a PHY reset
155 * @hw: pointer to hardware structure
156 **/
157s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
158{
159 u32 i;
160 u16 ctrl = 0;
161 s32 status = 0;
162
163 if (hw->phy.type == ixgbe_phy_unknown)
164 status = ixgbe_identify_phy_generic(hw);
165
166 if (status != 0 || hw->phy.type == ixgbe_phy_none)
167 goto out;
168
169 /* Don't reset PHY if it's shut down due to overtemp. */
170 if (!hw->phy.reset_if_overtemp &&
171 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
172 goto out;
173
174 /*
175 * Perform soft PHY reset to the PHY_XS.
176 * This will cause a soft reset to the PHY
177 */
178 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
179 MDIO_MMD_PHYXS,
180 MDIO_CTRL1_RESET);
181
182 /*
183 * Poll for reset bit to self-clear indicating reset is complete.
184 * Some PHYs could take up to 3 seconds to complete and need about
185 * 1.7 usec delay after the reset is complete.
186 */
187 for (i = 0; i < 30; i++) {
188 msleep(100);
189 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
190 MDIO_MMD_PHYXS, &ctrl);
191 if (!(ctrl & MDIO_CTRL1_RESET)) {
192 udelay(2);
193 break;
194 }
195 }
196
197 if (ctrl & MDIO_CTRL1_RESET) {
198 status = IXGBE_ERR_RESET_FAILED;
199 hw_dbg(hw, "PHY reset polling failed to complete.\n");
200 }
201
202out:
203 return status;
204}
205
206/**
207 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
208 * @hw: pointer to hardware structure
209 * @reg_addr: 32 bit address of PHY register to read
210 * @phy_data: Pointer to read data from PHY register
211 **/
212s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
213 u32 device_type, u16 *phy_data)
214{
215 u32 command;
216 u32 i;
217 u32 data;
218 s32 status = 0;
219 u16 gssr;
220
221 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
222 gssr = IXGBE_GSSR_PHY1_SM;
223 else
224 gssr = IXGBE_GSSR_PHY0_SM;
225
226 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
227 status = IXGBE_ERR_SWFW_SYNC;
228
229 if (status == 0) {
230 /* Setup and write the address cycle command */
231 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
232 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
233 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
234 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
235
236 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
237
238 /*
239 * Check every 10 usec to see if the address cycle completed.
240 * The MDI Command bit will clear when the operation is
241 * complete
242 */
243 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
244 udelay(10);
245
246 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
247
248 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
249 break;
250 }
251
252 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
253 hw_dbg(hw, "PHY address command did not complete.\n");
254 status = IXGBE_ERR_PHY;
255 }
256
257 if (status == 0) {
258 /*
259 * Address cycle complete, setup and write the read
260 * command
261 */
262 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
263 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
264 (hw->phy.mdio.prtad <<
265 IXGBE_MSCA_PHY_ADDR_SHIFT) |
266 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
267
268 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
269
270 /*
271 * Check every 10 usec to see if the address cycle
272 * completed. The MDI Command bit will clear when the
273 * operation is complete
274 */
275 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
276 udelay(10);
277
278 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
279
280 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
281 break;
282 }
283
284 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
285 hw_dbg(hw, "PHY read command didn't complete\n");
286 status = IXGBE_ERR_PHY;
287 } else {
288 /*
289 * Read operation is complete. Get the data
290 * from MSRWD
291 */
292 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
293 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
294 *phy_data = (u16)(data);
295 }
296 }
297
298 hw->mac.ops.release_swfw_sync(hw, gssr);
299 }
300
301 return status;
302}
303
304/**
305 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
306 * @hw: pointer to hardware structure
307 * @reg_addr: 32 bit PHY register to write
308 * @device_type: 5 bit device type
309 * @phy_data: Data to write to the PHY register
310 **/
311s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
312 u32 device_type, u16 phy_data)
313{
314 u32 command;
315 u32 i;
316 s32 status = 0;
317 u16 gssr;
318
319 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
320 gssr = IXGBE_GSSR_PHY1_SM;
321 else
322 gssr = IXGBE_GSSR_PHY0_SM;
323
324 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
325 status = IXGBE_ERR_SWFW_SYNC;
326
327 if (status == 0) {
328 /* Put the data in the MDI single read and write data register*/
329 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
330
331 /* Setup and write the address cycle command */
332 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
333 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
334 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
335 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
336
337 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
338
339 /*
340 * Check every 10 usec to see if the address cycle completed.
341 * The MDI Command bit will clear when the operation is
342 * complete
343 */
344 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
345 udelay(10);
346
347 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
348
349 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
350 break;
351 }
352
353 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
354 hw_dbg(hw, "PHY address cmd didn't complete\n");
355 status = IXGBE_ERR_PHY;
356 }
357
358 if (status == 0) {
359 /*
360 * Address cycle complete, setup and write the write
361 * command
362 */
363 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
364 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
365 (hw->phy.mdio.prtad <<
366 IXGBE_MSCA_PHY_ADDR_SHIFT) |
367 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
368
369 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
370
371 /*
372 * Check every 10 usec to see if the address cycle
373 * completed. The MDI Command bit will clear when the
374 * operation is complete
375 */
376 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
377 udelay(10);
378
379 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
380
381 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
382 break;
383 }
384
385 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
386 hw_dbg(hw, "PHY address cmd didn't complete\n");
387 status = IXGBE_ERR_PHY;
388 }
389 }
390
391 hw->mac.ops.release_swfw_sync(hw, gssr);
392 }
393
394 return status;
395}
396
397/**
398 * ixgbe_setup_phy_link_generic - Set and restart autoneg
399 * @hw: pointer to hardware structure
400 *
401 * Restart autonegotiation and PHY and waits for completion.
402 **/
403s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
404{
405 s32 status = 0;
406 u32 time_out;
407 u32 max_time_out = 10;
408 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
409 bool autoneg = false;
410 ixgbe_link_speed speed;
411
412 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
413
414 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
415 /* Set or unset auto-negotiation 10G advertisement */
416 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
417 MDIO_MMD_AN,
418 &autoneg_reg);
419
420 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
421 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
422 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
423
424 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
425 MDIO_MMD_AN,
426 autoneg_reg);
427 }
428
429 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
430 /* Set or unset auto-negotiation 1G advertisement */
431 hw->phy.ops.read_reg(hw,
432 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
433 MDIO_MMD_AN,
434 &autoneg_reg);
435
436 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
437 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
438 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
439
440 hw->phy.ops.write_reg(hw,
441 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
442 MDIO_MMD_AN,
443 autoneg_reg);
444 }
445
446 if (speed & IXGBE_LINK_SPEED_100_FULL) {
447 /* Set or unset auto-negotiation 100M advertisement */
448 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
449 MDIO_MMD_AN,
450 &autoneg_reg);
451
452 autoneg_reg &= ~(ADVERTISE_100FULL |
453 ADVERTISE_100HALF);
454 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
455 autoneg_reg |= ADVERTISE_100FULL;
456
457 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
458 MDIO_MMD_AN,
459 autoneg_reg);
460 }
461
462 /* Restart PHY autonegotiation and wait for completion */
463 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
464 MDIO_MMD_AN, &autoneg_reg);
465
466 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
467
468 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
469 MDIO_MMD_AN, autoneg_reg);
470
471 /* Wait for autonegotiation to finish */
472 for (time_out = 0; time_out < max_time_out; time_out++) {
473 udelay(10);
474 /* Restart PHY autonegotiation and wait for completion */
475 status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
476 MDIO_MMD_AN,
477 &autoneg_reg);
478
479 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
480 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) {
481 break;
482 }
483 }
484
485 if (time_out == max_time_out) {
486 status = IXGBE_ERR_LINK_SETUP;
487 hw_dbg(hw, "ixgbe_setup_phy_link_generic: time out");
488 }
489
490 return status;
491}
492
493/**
494 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
495 * @hw: pointer to hardware structure
496 * @speed: new link speed
497 * @autoneg: true if autonegotiation enabled
498 **/
499s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
500 ixgbe_link_speed speed,
501 bool autoneg,
502 bool autoneg_wait_to_complete)
503{
504
505 /*
506 * Clear autoneg_advertised and set new values based on input link
507 * speed.
508 */
509 hw->phy.autoneg_advertised = 0;
510
511 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
512 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
513
514 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
515 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
516
517 if (speed & IXGBE_LINK_SPEED_100_FULL)
518 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
519
520 /* Setup link based on the new speed settings */
521 hw->phy.ops.setup_link(hw);
522
523 return 0;
524}
525
526/**
527 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
528 * @hw: pointer to hardware structure
529 * @speed: pointer to link speed
530 * @autoneg: boolean auto-negotiation value
531 *
532 * Determines the link capabilities by reading the AUTOC register.
533 */
534s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
535 ixgbe_link_speed *speed,
536 bool *autoneg)
537{
538 s32 status = IXGBE_ERR_LINK_SETUP;
539 u16 speed_ability;
540
541 *speed = 0;
542 *autoneg = true;
543
544 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
545 &speed_ability);
546
547 if (status == 0) {
548 if (speed_ability & MDIO_SPEED_10G)
549 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
550 if (speed_ability & MDIO_PMA_SPEED_1000)
551 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
552 if (speed_ability & MDIO_PMA_SPEED_100)
553 *speed |= IXGBE_LINK_SPEED_100_FULL;
554 }
555
556 return status;
557}
558
559/**
560 * ixgbe_check_phy_link_tnx - Determine link and speed status
561 * @hw: pointer to hardware structure
562 *
563 * Reads the VS1 register to determine if link is up and the current speed for
564 * the PHY.
565 **/
566s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
567 bool *link_up)
568{
569 s32 status = 0;
570 u32 time_out;
571 u32 max_time_out = 10;
572 u16 phy_link = 0;
573 u16 phy_speed = 0;
574 u16 phy_data = 0;
575
576 /* Initialize speed and link to default case */
577 *link_up = false;
578 *speed = IXGBE_LINK_SPEED_10GB_FULL;
579
580 /*
581 * Check current speed and link status of the PHY register.
582 * This is a vendor specific register and may have to
583 * be changed for other copper PHYs.
584 */
585 for (time_out = 0; time_out < max_time_out; time_out++) {
586 udelay(10);
587 status = hw->phy.ops.read_reg(hw,
588 MDIO_STAT1,
589 MDIO_MMD_VEND1,
590 &phy_data);
591 phy_link = phy_data &
592 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
593 phy_speed = phy_data &
594 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
595 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
596 *link_up = true;
597 if (phy_speed ==
598 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
599 *speed = IXGBE_LINK_SPEED_1GB_FULL;
600 break;
601 }
602 }
603
604 return status;
605}
606
607/**
608 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
609 * @hw: pointer to hardware structure
610 *
611 * Restart autonegotiation and PHY and waits for completion.
612 **/
613s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
614{
615 s32 status = 0;
616 u32 time_out;
617 u32 max_time_out = 10;
618 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
619 bool autoneg = false;
620 ixgbe_link_speed speed;
621
622 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
623
624 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
625 /* Set or unset auto-negotiation 10G advertisement */
626 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
627 MDIO_MMD_AN,
628 &autoneg_reg);
629
630 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
631 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
632 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
633
634 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
635 MDIO_MMD_AN,
636 autoneg_reg);
637 }
638
639 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
640 /* Set or unset auto-negotiation 1G advertisement */
641 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
642 MDIO_MMD_AN,
643 &autoneg_reg);
644
645 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
646 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
647 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
648
649 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
650 MDIO_MMD_AN,
651 autoneg_reg);
652 }
653
654 if (speed & IXGBE_LINK_SPEED_100_FULL) {
655 /* Set or unset auto-negotiation 100M advertisement */
656 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
657 MDIO_MMD_AN,
658 &autoneg_reg);
659
660 autoneg_reg &= ~(ADVERTISE_100FULL |
661 ADVERTISE_100HALF);
662 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
663 autoneg_reg |= ADVERTISE_100FULL;
664
665 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
666 MDIO_MMD_AN,
667 autoneg_reg);
668 }
669
670 /* Restart PHY autonegotiation and wait for completion */
671 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
672 MDIO_MMD_AN, &autoneg_reg);
673
674 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
675
676 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
677 MDIO_MMD_AN, autoneg_reg);
678
679 /* Wait for autonegotiation to finish */
680 for (time_out = 0; time_out < max_time_out; time_out++) {
681 udelay(10);
682 /* Restart PHY autonegotiation and wait for completion */
683 status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
684 MDIO_MMD_AN,
685 &autoneg_reg);
686
687 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
688 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE)
689 break;
690 }
691
692 if (time_out == max_time_out) {
693 status = IXGBE_ERR_LINK_SETUP;
694 hw_dbg(hw, "ixgbe_setup_phy_link_tnx: time out");
695 }
696
697 return status;
698}
699
700/**
701 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
702 * @hw: pointer to hardware structure
703 * @firmware_version: pointer to the PHY Firmware Version
704 **/
705s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
706 u16 *firmware_version)
707{
708 s32 status = 0;
709
710 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
711 MDIO_MMD_VEND1,
712 firmware_version);
713
714 return status;
715}
716
717/**
718 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
719 * @hw: pointer to hardware structure
720 * @firmware_version: pointer to the PHY Firmware Version
721 **/
722s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
723 u16 *firmware_version)
724{
725 s32 status = 0;
726
727 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
728 MDIO_MMD_VEND1,
729 firmware_version);
730
731 return status;
732}
733
734/**
735 * ixgbe_reset_phy_nl - Performs a PHY reset
736 * @hw: pointer to hardware structure
737 **/
738s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
739{
740 u16 phy_offset, control, eword, edata, block_crc;
741 bool end_data = false;
742 u16 list_offset, data_offset;
743 u16 phy_data = 0;
744 s32 ret_val = 0;
745 u32 i;
746
747 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
748
749 /* reset the PHY and poll for completion */
750 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
751 (phy_data | MDIO_CTRL1_RESET));
752
753 for (i = 0; i < 100; i++) {
754 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
755 &phy_data);
756 if ((phy_data & MDIO_CTRL1_RESET) == 0)
757 break;
758 usleep_range(10000, 20000);
759 }
760
761 if ((phy_data & MDIO_CTRL1_RESET) != 0) {
762 hw_dbg(hw, "PHY reset did not complete.\n");
763 ret_val = IXGBE_ERR_PHY;
764 goto out;
765 }
766
767 /* Get init offsets */
768 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
769 &data_offset);
770 if (ret_val != 0)
771 goto out;
772
773 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
774 data_offset++;
775 while (!end_data) {
776 /*
777 * Read control word from PHY init contents offset
778 */
779 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
780 control = (eword & IXGBE_CONTROL_MASK_NL) >>
781 IXGBE_CONTROL_SHIFT_NL;
782 edata = eword & IXGBE_DATA_MASK_NL;
783 switch (control) {
784 case IXGBE_DELAY_NL:
785 data_offset++;
786 hw_dbg(hw, "DELAY: %d MS\n", edata);
787 usleep_range(edata * 1000, edata * 2000);
788 break;
789 case IXGBE_DATA_NL:
790 hw_dbg(hw, "DATA:\n");
791 data_offset++;
792 hw->eeprom.ops.read(hw, data_offset++,
793 &phy_offset);
794 for (i = 0; i < edata; i++) {
795 hw->eeprom.ops.read(hw, data_offset, &eword);
796 hw->phy.ops.write_reg(hw, phy_offset,
797 MDIO_MMD_PMAPMD, eword);
798 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
799 phy_offset);
800 data_offset++;
801 phy_offset++;
802 }
803 break;
804 case IXGBE_CONTROL_NL:
805 data_offset++;
806 hw_dbg(hw, "CONTROL:\n");
807 if (edata == IXGBE_CONTROL_EOL_NL) {
808 hw_dbg(hw, "EOL\n");
809 end_data = true;
810 } else if (edata == IXGBE_CONTROL_SOL_NL) {
811 hw_dbg(hw, "SOL\n");
812 } else {
813 hw_dbg(hw, "Bad control value\n");
814 ret_val = IXGBE_ERR_PHY;
815 goto out;
816 }
817 break;
818 default:
819 hw_dbg(hw, "Bad control type\n");
820 ret_val = IXGBE_ERR_PHY;
821 goto out;
822 }
823 }
824
825out:
826 return ret_val;
827}
828
829/**
830 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
831 * @hw: pointer to hardware structure
832 *
833 * Searches for and identifies the SFP module and assigns appropriate PHY type.
834 **/
835s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
836{
837 struct ixgbe_adapter *adapter = hw->back;
838 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
839 u32 vendor_oui = 0;
840 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
841 u8 identifier = 0;
842 u8 comp_codes_1g = 0;
843 u8 comp_codes_10g = 0;
844 u8 oui_bytes[3] = {0, 0, 0};
845 u8 cable_tech = 0;
846 u8 cable_spec = 0;
847 u16 enforce_sfp = 0;
848
849 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
850 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
851 status = IXGBE_ERR_SFP_NOT_PRESENT;
852 goto out;
853 }
854
855 status = hw->phy.ops.read_i2c_eeprom(hw,
856 IXGBE_SFF_IDENTIFIER,
857 &identifier);
858
859 if (status == IXGBE_ERR_SWFW_SYNC ||
860 status == IXGBE_ERR_I2C ||
861 status == IXGBE_ERR_SFP_NOT_PRESENT)
862 goto err_read_i2c_eeprom;
863
864 /* LAN ID is needed for sfp_type determination */
865 hw->mac.ops.set_lan_id(hw);
866
867 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
868 hw->phy.type = ixgbe_phy_sfp_unsupported;
869 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
870 } else {
871 status = hw->phy.ops.read_i2c_eeprom(hw,
872 IXGBE_SFF_1GBE_COMP_CODES,
873 &comp_codes_1g);
874
875 if (status == IXGBE_ERR_SWFW_SYNC ||
876 status == IXGBE_ERR_I2C ||
877 status == IXGBE_ERR_SFP_NOT_PRESENT)
878 goto err_read_i2c_eeprom;
879
880 status = hw->phy.ops.read_i2c_eeprom(hw,
881 IXGBE_SFF_10GBE_COMP_CODES,
882 &comp_codes_10g);
883
884 if (status == IXGBE_ERR_SWFW_SYNC ||
885 status == IXGBE_ERR_I2C ||
886 status == IXGBE_ERR_SFP_NOT_PRESENT)
887 goto err_read_i2c_eeprom;
888 status = hw->phy.ops.read_i2c_eeprom(hw,
889 IXGBE_SFF_CABLE_TECHNOLOGY,
890 &cable_tech);
891
892 if (status == IXGBE_ERR_SWFW_SYNC ||
893 status == IXGBE_ERR_I2C ||
894 status == IXGBE_ERR_SFP_NOT_PRESENT)
895 goto err_read_i2c_eeprom;
896
897 /* ID Module
898 * =========
899 * 0 SFP_DA_CU
900 * 1 SFP_SR
901 * 2 SFP_LR
902 * 3 SFP_DA_CORE0 - 82599-specific
903 * 4 SFP_DA_CORE1 - 82599-specific
904 * 5 SFP_SR/LR_CORE0 - 82599-specific
905 * 6 SFP_SR/LR_CORE1 - 82599-specific
906 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
907 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
908 * 9 SFP_1g_cu_CORE0 - 82599-specific
909 * 10 SFP_1g_cu_CORE1 - 82599-specific
910 */
911 if (hw->mac.type == ixgbe_mac_82598EB) {
912 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
913 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
914 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
915 hw->phy.sfp_type = ixgbe_sfp_type_sr;
916 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
917 hw->phy.sfp_type = ixgbe_sfp_type_lr;
918 else
919 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
920 } else if (hw->mac.type == ixgbe_mac_82599EB) {
921 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
922 if (hw->bus.lan_id == 0)
923 hw->phy.sfp_type =
924 ixgbe_sfp_type_da_cu_core0;
925 else
926 hw->phy.sfp_type =
927 ixgbe_sfp_type_da_cu_core1;
928 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
929 hw->phy.ops.read_i2c_eeprom(
930 hw, IXGBE_SFF_CABLE_SPEC_COMP,
931 &cable_spec);
932 if (cable_spec &
933 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
934 if (hw->bus.lan_id == 0)
935 hw->phy.sfp_type =
936 ixgbe_sfp_type_da_act_lmt_core0;
937 else
938 hw->phy.sfp_type =
939 ixgbe_sfp_type_da_act_lmt_core1;
940 } else {
941 hw->phy.sfp_type =
942 ixgbe_sfp_type_unknown;
943 }
944 } else if (comp_codes_10g &
945 (IXGBE_SFF_10GBASESR_CAPABLE |
946 IXGBE_SFF_10GBASELR_CAPABLE)) {
947 if (hw->bus.lan_id == 0)
948 hw->phy.sfp_type =
949 ixgbe_sfp_type_srlr_core0;
950 else
951 hw->phy.sfp_type =
952 ixgbe_sfp_type_srlr_core1;
953 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
954 if (hw->bus.lan_id == 0)
955 hw->phy.sfp_type =
956 ixgbe_sfp_type_1g_cu_core0;
957 else
958 hw->phy.sfp_type =
959 ixgbe_sfp_type_1g_cu_core1;
960 } else {
961 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
962 }
963 }
964
965 if (hw->phy.sfp_type != stored_sfp_type)
966 hw->phy.sfp_setup_needed = true;
967
968 /* Determine if the SFP+ PHY is dual speed or not. */
969 hw->phy.multispeed_fiber = false;
970 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
971 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
972 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
973 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
974 hw->phy.multispeed_fiber = true;
975
976 /* Determine PHY vendor */
977 if (hw->phy.type != ixgbe_phy_nl) {
978 hw->phy.id = identifier;
979 status = hw->phy.ops.read_i2c_eeprom(hw,
980 IXGBE_SFF_VENDOR_OUI_BYTE0,
981 &oui_bytes[0]);
982
983 if (status == IXGBE_ERR_SWFW_SYNC ||
984 status == IXGBE_ERR_I2C ||
985 status == IXGBE_ERR_SFP_NOT_PRESENT)
986 goto err_read_i2c_eeprom;
987
988 status = hw->phy.ops.read_i2c_eeprom(hw,
989 IXGBE_SFF_VENDOR_OUI_BYTE1,
990 &oui_bytes[1]);
991
992 if (status == IXGBE_ERR_SWFW_SYNC ||
993 status == IXGBE_ERR_I2C ||
994 status == IXGBE_ERR_SFP_NOT_PRESENT)
995 goto err_read_i2c_eeprom;
996
997 status = hw->phy.ops.read_i2c_eeprom(hw,
998 IXGBE_SFF_VENDOR_OUI_BYTE2,
999 &oui_bytes[2]);
1000
1001 if (status == IXGBE_ERR_SWFW_SYNC ||
1002 status == IXGBE_ERR_I2C ||
1003 status == IXGBE_ERR_SFP_NOT_PRESENT)
1004 goto err_read_i2c_eeprom;
1005
1006 vendor_oui =
1007 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1008 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1009 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1010
1011 switch (vendor_oui) {
1012 case IXGBE_SFF_VENDOR_OUI_TYCO:
1013 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1014 hw->phy.type =
1015 ixgbe_phy_sfp_passive_tyco;
1016 break;
1017 case IXGBE_SFF_VENDOR_OUI_FTL:
1018 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1019 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1020 else
1021 hw->phy.type = ixgbe_phy_sfp_ftl;
1022 break;
1023 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1024 hw->phy.type = ixgbe_phy_sfp_avago;
1025 break;
1026 case IXGBE_SFF_VENDOR_OUI_INTEL:
1027 hw->phy.type = ixgbe_phy_sfp_intel;
1028 break;
1029 default:
1030 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1031 hw->phy.type =
1032 ixgbe_phy_sfp_passive_unknown;
1033 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1034 hw->phy.type =
1035 ixgbe_phy_sfp_active_unknown;
1036 else
1037 hw->phy.type = ixgbe_phy_sfp_unknown;
1038 break;
1039 }
1040 }
1041
1042 /* Allow any DA cable vendor */
1043 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1044 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1045 status = 0;
1046 goto out;
1047 }
1048
1049 /* Verify supported 1G SFP modules */
1050 if (comp_codes_10g == 0 &&
1051 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1052 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0)) {
1053 hw->phy.type = ixgbe_phy_sfp_unsupported;
1054 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1055 goto out;
1056 }
1057
1058 /* Anything else 82598-based is supported */
1059 if (hw->mac.type == ixgbe_mac_82598EB) {
1060 status = 0;
1061 goto out;
1062 }
1063
1064 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1065 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1066 !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
1067 (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1))) {
1068 /* Make sure we're a supported PHY type */
1069 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1070 status = 0;
1071 } else {
1072 if (hw->allow_unsupported_sfp) {
1073 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.");
1074 status = 0;
1075 } else {
1076 hw_dbg(hw,
1077 "SFP+ module not supported\n");
1078 hw->phy.type =
1079 ixgbe_phy_sfp_unsupported;
1080 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1081 }
1082 }
1083 } else {
1084 status = 0;
1085 }
1086 }
1087
1088out:
1089 return status;
1090
1091err_read_i2c_eeprom:
1092 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1093 if (hw->phy.type != ixgbe_phy_nl) {
1094 hw->phy.id = 0;
1095 hw->phy.type = ixgbe_phy_unknown;
1096 }
1097 return IXGBE_ERR_SFP_NOT_PRESENT;
1098}
1099
1100/**
1101 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1102 * @hw: pointer to hardware structure
1103 * @list_offset: offset to the SFP ID list
1104 * @data_offset: offset to the SFP data block
1105 *
1106 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1107 * so it returns the offsets to the phy init sequence block.
1108 **/
1109s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1110 u16 *list_offset,
1111 u16 *data_offset)
1112{
1113 u16 sfp_id;
1114 u16 sfp_type = hw->phy.sfp_type;
1115
1116 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1117 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1118
1119 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1120 return IXGBE_ERR_SFP_NOT_PRESENT;
1121
1122 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1123 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1124 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1125
1126 /*
1127 * Limiting active cables and 1G Phys must be initialized as
1128 * SR modules
1129 */
1130 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1131 sfp_type == ixgbe_sfp_type_1g_cu_core0)
1132 sfp_type = ixgbe_sfp_type_srlr_core0;
1133 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1134 sfp_type == ixgbe_sfp_type_1g_cu_core1)
1135 sfp_type = ixgbe_sfp_type_srlr_core1;
1136
1137 /* Read offset to PHY init contents */
1138 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
1139
1140 if ((!*list_offset) || (*list_offset == 0xFFFF))
1141 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1142
1143 /* Shift offset to first ID word */
1144 (*list_offset)++;
1145
1146 /*
1147 * Find the matching SFP ID in the EEPROM
1148 * and program the init sequence
1149 */
1150 hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
1151
1152 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1153 if (sfp_id == sfp_type) {
1154 (*list_offset)++;
1155 hw->eeprom.ops.read(hw, *list_offset, data_offset);
1156 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1157 hw_dbg(hw, "SFP+ module not supported\n");
1158 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1159 } else {
1160 break;
1161 }
1162 } else {
1163 (*list_offset) += 2;
1164 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1165 return IXGBE_ERR_PHY;
1166 }
1167 }
1168
1169 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1170 hw_dbg(hw, "No matching SFP+ module found\n");
1171 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1172 }
1173
1174 return 0;
1175}
1176
1177/**
1178 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1179 * @hw: pointer to hardware structure
1180 * @byte_offset: EEPROM byte offset to read
1181 * @eeprom_data: value read
1182 *
1183 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1184 **/
1185s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1186 u8 *eeprom_data)
1187{
1188 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1189 IXGBE_I2C_EEPROM_DEV_ADDR,
1190 eeprom_data);
1191}
1192
1193/**
1194 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1195 * @hw: pointer to hardware structure
1196 * @byte_offset: EEPROM byte offset to write
1197 * @eeprom_data: value to write
1198 *
1199 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1200 **/
1201s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1202 u8 eeprom_data)
1203{
1204 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1205 IXGBE_I2C_EEPROM_DEV_ADDR,
1206 eeprom_data);
1207}
1208
1209/**
1210 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1211 * @hw: pointer to hardware structure
1212 * @byte_offset: byte offset to read
1213 * @data: value read
1214 *
1215 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1216 * a specified device address.
1217 **/
1218s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1219 u8 dev_addr, u8 *data)
1220{
1221 s32 status = 0;
1222 u32 max_retry = 10;
1223 u32 retry = 0;
1224 u16 swfw_mask = 0;
1225 bool nack = true;
1226 *data = 0;
1227
1228 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1229 swfw_mask = IXGBE_GSSR_PHY1_SM;
1230 else
1231 swfw_mask = IXGBE_GSSR_PHY0_SM;
1232
1233 do {
1234 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
1235 status = IXGBE_ERR_SWFW_SYNC;
1236 goto read_byte_out;
1237 }
1238
1239 ixgbe_i2c_start(hw);
1240
1241 /* Device Address and write indication */
1242 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1243 if (status != 0)
1244 goto fail;
1245
1246 status = ixgbe_get_i2c_ack(hw);
1247 if (status != 0)
1248 goto fail;
1249
1250 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1251 if (status != 0)
1252 goto fail;
1253
1254 status = ixgbe_get_i2c_ack(hw);
1255 if (status != 0)
1256 goto fail;
1257
1258 ixgbe_i2c_start(hw);
1259
1260 /* Device Address and read indication */
1261 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1262 if (status != 0)
1263 goto fail;
1264
1265 status = ixgbe_get_i2c_ack(hw);
1266 if (status != 0)
1267 goto fail;
1268
1269 status = ixgbe_clock_in_i2c_byte(hw, data);
1270 if (status != 0)
1271 goto fail;
1272
1273 status = ixgbe_clock_out_i2c_bit(hw, nack);
1274 if (status != 0)
1275 goto fail;
1276
1277 ixgbe_i2c_stop(hw);
1278 break;
1279
1280fail:
1281 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1282 msleep(100);
1283 ixgbe_i2c_bus_clear(hw);
1284 retry++;
1285 if (retry < max_retry)
1286 hw_dbg(hw, "I2C byte read error - Retrying.\n");
1287 else
1288 hw_dbg(hw, "I2C byte read error.\n");
1289
1290 } while (retry < max_retry);
1291
1292 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1293
1294read_byte_out:
1295 return status;
1296}
1297
1298/**
1299 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1300 * @hw: pointer to hardware structure
1301 * @byte_offset: byte offset to write
1302 * @data: value to write
1303 *
1304 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1305 * a specified device address.
1306 **/
1307s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1308 u8 dev_addr, u8 data)
1309{
1310 s32 status = 0;
1311 u32 max_retry = 1;
1312 u32 retry = 0;
1313 u16 swfw_mask = 0;
1314
1315 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1316 swfw_mask = IXGBE_GSSR_PHY1_SM;
1317 else
1318 swfw_mask = IXGBE_GSSR_PHY0_SM;
1319
1320 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
1321 status = IXGBE_ERR_SWFW_SYNC;
1322 goto write_byte_out;
1323 }
1324
1325 do {
1326 ixgbe_i2c_start(hw);
1327
1328 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1329 if (status != 0)
1330 goto fail;
1331
1332 status = ixgbe_get_i2c_ack(hw);
1333 if (status != 0)
1334 goto fail;
1335
1336 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1337 if (status != 0)
1338 goto fail;
1339
1340 status = ixgbe_get_i2c_ack(hw);
1341 if (status != 0)
1342 goto fail;
1343
1344 status = ixgbe_clock_out_i2c_byte(hw, data);
1345 if (status != 0)
1346 goto fail;
1347
1348 status = ixgbe_get_i2c_ack(hw);
1349 if (status != 0)
1350 goto fail;
1351
1352 ixgbe_i2c_stop(hw);
1353 break;
1354
1355fail:
1356 ixgbe_i2c_bus_clear(hw);
1357 retry++;
1358 if (retry < max_retry)
1359 hw_dbg(hw, "I2C byte write error - Retrying.\n");
1360 else
1361 hw_dbg(hw, "I2C byte write error.\n");
1362 } while (retry < max_retry);
1363
1364 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1365
1366write_byte_out:
1367 return status;
1368}
1369
1370/**
1371 * ixgbe_i2c_start - Sets I2C start condition
1372 * @hw: pointer to hardware structure
1373 *
1374 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1375 **/
1376static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1377{
1378 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1379
1380 /* Start condition must begin with data and clock high */
1381 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1382 ixgbe_raise_i2c_clk(hw, &i2cctl);
1383
1384 /* Setup time for start condition (4.7us) */
1385 udelay(IXGBE_I2C_T_SU_STA);
1386
1387 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1388
1389 /* Hold time for start condition (4us) */
1390 udelay(IXGBE_I2C_T_HD_STA);
1391
1392 ixgbe_lower_i2c_clk(hw, &i2cctl);
1393
1394 /* Minimum low period of clock is 4.7 us */
1395 udelay(IXGBE_I2C_T_LOW);
1396
1397}
1398
1399/**
1400 * ixgbe_i2c_stop - Sets I2C stop condition
1401 * @hw: pointer to hardware structure
1402 *
1403 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1404 **/
1405static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1406{
1407 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1408
1409 /* Stop condition must begin with data low and clock high */
1410 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1411 ixgbe_raise_i2c_clk(hw, &i2cctl);
1412
1413 /* Setup time for stop condition (4us) */
1414 udelay(IXGBE_I2C_T_SU_STO);
1415
1416 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1417
1418 /* bus free time between stop and start (4.7us)*/
1419 udelay(IXGBE_I2C_T_BUF);
1420}
1421
1422/**
1423 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1424 * @hw: pointer to hardware structure
1425 * @data: data byte to clock in
1426 *
1427 * Clocks in one byte data via I2C data/clock
1428 **/
1429static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1430{
1431 s32 i;
1432 bool bit = false;
1433
1434 for (i = 7; i >= 0; i--) {
1435 ixgbe_clock_in_i2c_bit(hw, &bit);
1436 *data |= bit << i;
1437 }
1438
1439 return 0;
1440}
1441
1442/**
1443 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1444 * @hw: pointer to hardware structure
1445 * @data: data byte clocked out
1446 *
1447 * Clocks out one byte data via I2C data/clock
1448 **/
1449static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1450{
1451 s32 status = 0;
1452 s32 i;
1453 u32 i2cctl;
1454 bool bit = false;
1455
1456 for (i = 7; i >= 0; i--) {
1457 bit = (data >> i) & 0x1;
1458 status = ixgbe_clock_out_i2c_bit(hw, bit);
1459
1460 if (status != 0)
1461 break;
1462 }
1463
1464 /* Release SDA line (set high) */
1465 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1466 i2cctl |= IXGBE_I2C_DATA_OUT;
1467 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1468 IXGBE_WRITE_FLUSH(hw);
1469
1470 return status;
1471}
1472
1473/**
1474 * ixgbe_get_i2c_ack - Polls for I2C ACK
1475 * @hw: pointer to hardware structure
1476 *
1477 * Clocks in/out one bit via I2C data/clock
1478 **/
1479static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1480{
1481 s32 status = 0;
1482 u32 i = 0;
1483 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1484 u32 timeout = 10;
1485 bool ack = true;
1486
1487 ixgbe_raise_i2c_clk(hw, &i2cctl);
1488
1489
1490 /* Minimum high period of clock is 4us */
1491 udelay(IXGBE_I2C_T_HIGH);
1492
1493 /* Poll for ACK. Note that ACK in I2C spec is
1494 * transition from 1 to 0 */
1495 for (i = 0; i < timeout; i++) {
1496 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1497 ack = ixgbe_get_i2c_data(&i2cctl);
1498
1499 udelay(1);
1500 if (ack == 0)
1501 break;
1502 }
1503
1504 if (ack == 1) {
1505 hw_dbg(hw, "I2C ack was not received.\n");
1506 status = IXGBE_ERR_I2C;
1507 }
1508
1509 ixgbe_lower_i2c_clk(hw, &i2cctl);
1510
1511 /* Minimum low period of clock is 4.7 us */
1512 udelay(IXGBE_I2C_T_LOW);
1513
1514 return status;
1515}
1516
1517/**
1518 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1519 * @hw: pointer to hardware structure
1520 * @data: read data value
1521 *
1522 * Clocks in one bit via I2C data/clock
1523 **/
1524static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1525{
1526 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1527
1528 ixgbe_raise_i2c_clk(hw, &i2cctl);
1529
1530 /* Minimum high period of clock is 4us */
1531 udelay(IXGBE_I2C_T_HIGH);
1532
1533 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1534 *data = ixgbe_get_i2c_data(&i2cctl);
1535
1536 ixgbe_lower_i2c_clk(hw, &i2cctl);
1537
1538 /* Minimum low period of clock is 4.7 us */
1539 udelay(IXGBE_I2C_T_LOW);
1540
1541 return 0;
1542}
1543
1544/**
1545 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1546 * @hw: pointer to hardware structure
1547 * @data: data value to write
1548 *
1549 * Clocks out one bit via I2C data/clock
1550 **/
1551static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1552{
1553 s32 status;
1554 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1555
1556 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1557 if (status == 0) {
1558 ixgbe_raise_i2c_clk(hw, &i2cctl);
1559
1560 /* Minimum high period of clock is 4us */
1561 udelay(IXGBE_I2C_T_HIGH);
1562
1563 ixgbe_lower_i2c_clk(hw, &i2cctl);
1564
1565 /* Minimum low period of clock is 4.7 us.
1566 * This also takes care of the data hold time.
1567 */
1568 udelay(IXGBE_I2C_T_LOW);
1569 } else {
1570 status = IXGBE_ERR_I2C;
1571 hw_dbg(hw, "I2C data was not set to %X\n", data);
1572 }
1573
1574 return status;
1575}
1576/**
1577 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1578 * @hw: pointer to hardware structure
1579 * @i2cctl: Current value of I2CCTL register
1580 *
1581 * Raises the I2C clock line '0'->'1'
1582 **/
1583static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1584{
1585 u32 i = 0;
1586 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1587 u32 i2cctl_r = 0;
1588
1589 for (i = 0; i < timeout; i++) {
1590 *i2cctl |= IXGBE_I2C_CLK_OUT;
1591 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1592 IXGBE_WRITE_FLUSH(hw);
1593 /* SCL rise time (1000ns) */
1594 udelay(IXGBE_I2C_T_RISE);
1595
1596 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1597 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1598 break;
1599 }
1600}
1601
1602/**
1603 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1604 * @hw: pointer to hardware structure
1605 * @i2cctl: Current value of I2CCTL register
1606 *
1607 * Lowers the I2C clock line '1'->'0'
1608 **/
1609static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1610{
1611
1612 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1613
1614 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1615 IXGBE_WRITE_FLUSH(hw);
1616
1617 /* SCL fall time (300ns) */
1618 udelay(IXGBE_I2C_T_FALL);
1619}
1620
1621/**
1622 * ixgbe_set_i2c_data - Sets the I2C data bit
1623 * @hw: pointer to hardware structure
1624 * @i2cctl: Current value of I2CCTL register
1625 * @data: I2C data value (0 or 1) to set
1626 *
1627 * Sets the I2C data bit
1628 **/
1629static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1630{
1631 s32 status = 0;
1632
1633 if (data)
1634 *i2cctl |= IXGBE_I2C_DATA_OUT;
1635 else
1636 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1637
1638 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1639 IXGBE_WRITE_FLUSH(hw);
1640
1641 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1642 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1643
1644 /* Verify data was set correctly */
1645 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1646 if (data != ixgbe_get_i2c_data(i2cctl)) {
1647 status = IXGBE_ERR_I2C;
1648 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1649 }
1650
1651 return status;
1652}
1653
1654/**
1655 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1656 * @hw: pointer to hardware structure
1657 * @i2cctl: Current value of I2CCTL register
1658 *
1659 * Returns the I2C data bit value
1660 **/
1661static bool ixgbe_get_i2c_data(u32 *i2cctl)
1662{
1663 bool data;
1664
1665 if (*i2cctl & IXGBE_I2C_DATA_IN)
1666 data = true;
1667 else
1668 data = false;
1669
1670 return data;
1671}
1672
1673/**
1674 * ixgbe_i2c_bus_clear - Clears the I2C bus
1675 * @hw: pointer to hardware structure
1676 *
1677 * Clears the I2C bus by sending nine clock pulses.
1678 * Used when data line is stuck low.
1679 **/
1680static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1681{
1682 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1683 u32 i;
1684
1685 ixgbe_i2c_start(hw);
1686
1687 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1688
1689 for (i = 0; i < 9; i++) {
1690 ixgbe_raise_i2c_clk(hw, &i2cctl);
1691
1692 /* Min high period of clock is 4us */
1693 udelay(IXGBE_I2C_T_HIGH);
1694
1695 ixgbe_lower_i2c_clk(hw, &i2cctl);
1696
1697 /* Min low period of clock is 4.7us*/
1698 udelay(IXGBE_I2C_T_LOW);
1699 }
1700
1701 ixgbe_i2c_start(hw);
1702
1703 /* Put the i2c bus back to default state */
1704 ixgbe_i2c_stop(hw);
1705}
1706
1707/**
1708 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
1709 * @hw: pointer to hardware structure
1710 *
1711 * Checks if the LASI temp alarm status was triggered due to overtemp
1712 **/
1713s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1714{
1715 s32 status = 0;
1716 u16 phy_data = 0;
1717
1718 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1719 goto out;
1720
1721 /* Check that the LASI temp alarm status was triggered */
1722 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1723 MDIO_MMD_PMAPMD, &phy_data);
1724
1725 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1726 goto out;
1727
1728 status = IXGBE_ERR_OVERTEMP;
1729out:
1730 return status;
1731}
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4#include <linux/pci.h>
5#include <linux/delay.h>
6#include <linux/iopoll.h>
7#include <linux/sched.h>
8
9#include "ixgbe.h"
10#include "ixgbe_phy.h"
11
12static void ixgbe_i2c_start(struct ixgbe_hw *hw);
13static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
14static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
15static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
16static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
17static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
18static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
19static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
20static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
21static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
22static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
23static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
24static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
25static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
26static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
27
28/**
29 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
30 * @hw: pointer to the hardware structure
31 * @byte: byte to send
32 *
33 * Returns an error code on error.
34 **/
35static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
36{
37 s32 status;
38
39 status = ixgbe_clock_out_i2c_byte(hw, byte);
40 if (status)
41 return status;
42 return ixgbe_get_i2c_ack(hw);
43}
44
45/**
46 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
47 * @hw: pointer to the hardware structure
48 * @byte: pointer to a u8 to receive the byte
49 *
50 * Returns an error code on error.
51 **/
52static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
53{
54 s32 status;
55
56 status = ixgbe_clock_in_i2c_byte(hw, byte);
57 if (status)
58 return status;
59 /* ACK */
60 return ixgbe_clock_out_i2c_bit(hw, false);
61}
62
63/**
64 * ixgbe_ones_comp_byte_add - Perform one's complement addition
65 * @add1: addend 1
66 * @add2: addend 2
67 *
68 * Returns one's complement 8-bit sum.
69 **/
70static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
71{
72 u16 sum = add1 + add2;
73
74 sum = (sum & 0xFF) + (sum >> 8);
75 return sum & 0xFF;
76}
77
78/**
79 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
80 * @hw: pointer to the hardware structure
81 * @addr: I2C bus address to read from
82 * @reg: I2C device register to read from
83 * @val: pointer to location to receive read value
84 * @lock: true if to take and release semaphore
85 *
86 * Returns an error code on error.
87 */
88s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
89 u16 reg, u16 *val, bool lock)
90{
91 u32 swfw_mask = hw->phy.phy_semaphore_mask;
92 int max_retry = 3;
93 int retry = 0;
94 u8 csum_byte;
95 u8 high_bits;
96 u8 low_bits;
97 u8 reg_high;
98 u8 csum;
99
100 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
101 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
102 csum = ~csum;
103 do {
104 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
105 return IXGBE_ERR_SWFW_SYNC;
106 ixgbe_i2c_start(hw);
107 /* Device Address and write indication */
108 if (ixgbe_out_i2c_byte_ack(hw, addr))
109 goto fail;
110 /* Write bits 14:8 */
111 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
112 goto fail;
113 /* Write bits 7:0 */
114 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
115 goto fail;
116 /* Write csum */
117 if (ixgbe_out_i2c_byte_ack(hw, csum))
118 goto fail;
119 /* Re-start condition */
120 ixgbe_i2c_start(hw);
121 /* Device Address and read indication */
122 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
123 goto fail;
124 /* Get upper bits */
125 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
126 goto fail;
127 /* Get low bits */
128 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
129 goto fail;
130 /* Get csum */
131 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
132 goto fail;
133 /* NACK */
134 if (ixgbe_clock_out_i2c_bit(hw, false))
135 goto fail;
136 ixgbe_i2c_stop(hw);
137 if (lock)
138 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
139 *val = (high_bits << 8) | low_bits;
140 return 0;
141
142fail:
143 ixgbe_i2c_bus_clear(hw);
144 if (lock)
145 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
146 retry++;
147 if (retry < max_retry)
148 hw_dbg(hw, "I2C byte read combined error - Retry.\n");
149 else
150 hw_dbg(hw, "I2C byte read combined error.\n");
151 } while (retry < max_retry);
152
153 return IXGBE_ERR_I2C;
154}
155
156/**
157 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
158 * @hw: pointer to the hardware structure
159 * @addr: I2C bus address to write to
160 * @reg: I2C device register to write to
161 * @val: value to write
162 * @lock: true if to take and release semaphore
163 *
164 * Returns an error code on error.
165 */
166s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
167 u16 reg, u16 val, bool lock)
168{
169 u32 swfw_mask = hw->phy.phy_semaphore_mask;
170 int max_retry = 1;
171 int retry = 0;
172 u8 reg_high;
173 u8 csum;
174
175 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
176 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
177 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
178 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
179 csum = ~csum;
180 do {
181 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
182 return IXGBE_ERR_SWFW_SYNC;
183 ixgbe_i2c_start(hw);
184 /* Device Address and write indication */
185 if (ixgbe_out_i2c_byte_ack(hw, addr))
186 goto fail;
187 /* Write bits 14:8 */
188 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
189 goto fail;
190 /* Write bits 7:0 */
191 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
192 goto fail;
193 /* Write data 15:8 */
194 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
195 goto fail;
196 /* Write data 7:0 */
197 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
198 goto fail;
199 /* Write csum */
200 if (ixgbe_out_i2c_byte_ack(hw, csum))
201 goto fail;
202 ixgbe_i2c_stop(hw);
203 if (lock)
204 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
205 return 0;
206
207fail:
208 ixgbe_i2c_bus_clear(hw);
209 if (lock)
210 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
211 retry++;
212 if (retry < max_retry)
213 hw_dbg(hw, "I2C byte write combined error - Retry.\n");
214 else
215 hw_dbg(hw, "I2C byte write combined error.\n");
216 } while (retry < max_retry);
217
218 return IXGBE_ERR_I2C;
219}
220
221/**
222 * ixgbe_probe_phy - Probe a single address for a PHY
223 * @hw: pointer to hardware structure
224 * @phy_addr: PHY address to probe
225 *
226 * Returns true if PHY found
227 **/
228static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
229{
230 u16 ext_ability = 0;
231
232 hw->phy.mdio.prtad = phy_addr;
233 if (mdio45_probe(&hw->phy.mdio, phy_addr) != 0)
234 return false;
235
236 if (ixgbe_get_phy_id(hw))
237 return false;
238
239 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
240
241 if (hw->phy.type == ixgbe_phy_unknown) {
242 hw->phy.ops.read_reg(hw,
243 MDIO_PMA_EXTABLE,
244 MDIO_MMD_PMAPMD,
245 &ext_ability);
246 if (ext_ability &
247 (MDIO_PMA_EXTABLE_10GBT |
248 MDIO_PMA_EXTABLE_1000BT))
249 hw->phy.type = ixgbe_phy_cu_unknown;
250 else
251 hw->phy.type = ixgbe_phy_generic;
252 }
253
254 return true;
255}
256
257/**
258 * ixgbe_identify_phy_generic - Get physical layer module
259 * @hw: pointer to hardware structure
260 *
261 * Determines the physical layer module found on the current adapter.
262 **/
263s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
264{
265 u32 phy_addr;
266 u32 status = IXGBE_ERR_PHY_ADDR_INVALID;
267
268 if (!hw->phy.phy_semaphore_mask) {
269 if (hw->bus.lan_id)
270 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
271 else
272 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
273 }
274
275 if (hw->phy.type != ixgbe_phy_unknown)
276 return 0;
277
278 if (hw->phy.nw_mng_if_sel) {
279 phy_addr = (hw->phy.nw_mng_if_sel &
280 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
281 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
282 if (ixgbe_probe_phy(hw, phy_addr))
283 return 0;
284 else
285 return IXGBE_ERR_PHY_ADDR_INVALID;
286 }
287
288 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
289 if (ixgbe_probe_phy(hw, phy_addr)) {
290 status = 0;
291 break;
292 }
293 }
294
295 /* Certain media types do not have a phy so an address will not
296 * be found and the code will take this path. Caller has to
297 * decide if it is an error or not.
298 */
299 if (status)
300 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
301
302 return status;
303}
304
305/**
306 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
307 * @hw: pointer to the hardware structure
308 *
309 * This function checks the MMNGC.MNG_VETO bit to see if there are
310 * any constraints on link from manageability. For MAC's that don't
311 * have this bit just return false since the link can not be blocked
312 * via this method.
313 **/
314bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
315{
316 u32 mmngc;
317
318 /* If we don't have this bit, it can't be blocking */
319 if (hw->mac.type == ixgbe_mac_82598EB)
320 return false;
321
322 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
323 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
324 hw_dbg(hw, "MNG_VETO bit detected.\n");
325 return true;
326 }
327
328 return false;
329}
330
331/**
332 * ixgbe_get_phy_id - Get the phy type
333 * @hw: pointer to hardware structure
334 *
335 **/
336static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
337{
338 s32 status;
339 u16 phy_id_high = 0;
340 u16 phy_id_low = 0;
341
342 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
343 &phy_id_high);
344
345 if (!status) {
346 hw->phy.id = (u32)(phy_id_high << 16);
347 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
348 &phy_id_low);
349 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
350 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
351 }
352 return status;
353}
354
355/**
356 * ixgbe_get_phy_type_from_id - Get the phy type
357 * @phy_id: hardware phy id
358 *
359 **/
360static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
361{
362 enum ixgbe_phy_type phy_type;
363
364 switch (phy_id) {
365 case TN1010_PHY_ID:
366 phy_type = ixgbe_phy_tn;
367 break;
368 case X550_PHY_ID2:
369 case X550_PHY_ID3:
370 case X540_PHY_ID:
371 phy_type = ixgbe_phy_aq;
372 break;
373 case QT2022_PHY_ID:
374 phy_type = ixgbe_phy_qt;
375 break;
376 case ATH_PHY_ID:
377 phy_type = ixgbe_phy_nl;
378 break;
379 case X557_PHY_ID:
380 case X557_PHY_ID2:
381 phy_type = ixgbe_phy_x550em_ext_t;
382 break;
383 case BCM54616S_E_PHY_ID:
384 phy_type = ixgbe_phy_ext_1g_t;
385 break;
386 default:
387 phy_type = ixgbe_phy_unknown;
388 break;
389 }
390
391 return phy_type;
392}
393
394/**
395 * ixgbe_reset_phy_generic - Performs a PHY reset
396 * @hw: pointer to hardware structure
397 **/
398s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
399{
400 u32 i;
401 u16 ctrl = 0;
402 s32 status = 0;
403
404 if (hw->phy.type == ixgbe_phy_unknown)
405 status = ixgbe_identify_phy_generic(hw);
406
407 if (status != 0 || hw->phy.type == ixgbe_phy_none)
408 return status;
409
410 /* Don't reset PHY if it's shut down due to overtemp. */
411 if (!hw->phy.reset_if_overtemp &&
412 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
413 return 0;
414
415 /* Blocked by MNG FW so bail */
416 if (ixgbe_check_reset_blocked(hw))
417 return 0;
418
419 /*
420 * Perform soft PHY reset to the PHY_XS.
421 * This will cause a soft reset to the PHY
422 */
423 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
424 MDIO_MMD_PHYXS,
425 MDIO_CTRL1_RESET);
426
427 /*
428 * Poll for reset bit to self-clear indicating reset is complete.
429 * Some PHYs could take up to 3 seconds to complete and need about
430 * 1.7 usec delay after the reset is complete.
431 */
432 for (i = 0; i < 30; i++) {
433 msleep(100);
434 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
435 status = hw->phy.ops.read_reg(hw,
436 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
437 MDIO_MMD_PMAPMD, &ctrl);
438 if (status)
439 return status;
440
441 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
442 udelay(2);
443 break;
444 }
445 } else {
446 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1,
447 MDIO_MMD_PHYXS, &ctrl);
448 if (status)
449 return status;
450
451 if (!(ctrl & MDIO_CTRL1_RESET)) {
452 udelay(2);
453 break;
454 }
455 }
456 }
457
458 if (ctrl & MDIO_CTRL1_RESET) {
459 hw_dbg(hw, "PHY reset polling failed to complete.\n");
460 return IXGBE_ERR_RESET_FAILED;
461 }
462
463 return 0;
464}
465
466/**
467 * ixgbe_read_phy_reg_mdi - read PHY register
468 * @hw: pointer to hardware structure
469 * @reg_addr: 32 bit address of PHY register to read
470 * @device_type: 5 bit device type
471 * @phy_data: Pointer to read data from PHY register
472 *
473 * Reads a value from a specified PHY register without the SWFW lock
474 **/
475s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
476 u16 *phy_data)
477{
478 u32 i, data, command;
479
480 /* Setup and write the address cycle command */
481 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
482 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
483 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
484 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
485
486 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
487
488 /* Check every 10 usec to see if the address cycle completed.
489 * The MDI Command bit will clear when the operation is
490 * complete
491 */
492 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
493 udelay(10);
494
495 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
496 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
497 break;
498 }
499
500
501 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
502 hw_dbg(hw, "PHY address command did not complete.\n");
503 return IXGBE_ERR_PHY;
504 }
505
506 /* Address cycle complete, setup and write the read
507 * command
508 */
509 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
510 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
511 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
512 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
513
514 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
515
516 /* Check every 10 usec to see if the address cycle
517 * completed. The MDI Command bit will clear when the
518 * operation is complete
519 */
520 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
521 udelay(10);
522
523 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
524 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
525 break;
526 }
527
528 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
529 hw_dbg(hw, "PHY read command didn't complete\n");
530 return IXGBE_ERR_PHY;
531 }
532
533 /* Read operation is complete. Get the data
534 * from MSRWD
535 */
536 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
537 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
538 *phy_data = (u16)(data);
539
540 return 0;
541}
542
543/**
544 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
545 * using the SWFW lock - this function is needed in most cases
546 * @hw: pointer to hardware structure
547 * @reg_addr: 32 bit address of PHY register to read
548 * @device_type: 5 bit device type
549 * @phy_data: Pointer to read data from PHY register
550 **/
551s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
552 u32 device_type, u16 *phy_data)
553{
554 s32 status;
555 u32 gssr = hw->phy.phy_semaphore_mask;
556
557 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
558 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
559 phy_data);
560 hw->mac.ops.release_swfw_sync(hw, gssr);
561 } else {
562 return IXGBE_ERR_SWFW_SYNC;
563 }
564
565 return status;
566}
567
568/**
569 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
570 * without SWFW lock
571 * @hw: pointer to hardware structure
572 * @reg_addr: 32 bit PHY register to write
573 * @device_type: 5 bit device type
574 * @phy_data: Data to write to the PHY register
575 **/
576s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
577 u32 device_type, u16 phy_data)
578{
579 u32 i, command;
580
581 /* Put the data in the MDI single read and write data register*/
582 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
583
584 /* Setup and write the address cycle command */
585 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
586 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
587 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
588 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
589
590 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
591
592 /*
593 * Check every 10 usec to see if the address cycle completed.
594 * The MDI Command bit will clear when the operation is
595 * complete
596 */
597 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
598 udelay(10);
599
600 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
601 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
602 break;
603 }
604
605 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
606 hw_dbg(hw, "PHY address cmd didn't complete\n");
607 return IXGBE_ERR_PHY;
608 }
609
610 /*
611 * Address cycle complete, setup and write the write
612 * command
613 */
614 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
615 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
616 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
617 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
618
619 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
620
621 /* Check every 10 usec to see if the address cycle
622 * completed. The MDI Command bit will clear when the
623 * operation is complete
624 */
625 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
626 udelay(10);
627
628 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
629 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
630 break;
631 }
632
633 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
634 hw_dbg(hw, "PHY write cmd didn't complete\n");
635 return IXGBE_ERR_PHY;
636 }
637
638 return 0;
639}
640
641/**
642 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
643 * using SWFW lock- this function is needed in most cases
644 * @hw: pointer to hardware structure
645 * @reg_addr: 32 bit PHY register to write
646 * @device_type: 5 bit device type
647 * @phy_data: Data to write to the PHY register
648 **/
649s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
650 u32 device_type, u16 phy_data)
651{
652 s32 status;
653 u32 gssr = hw->phy.phy_semaphore_mask;
654
655 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
656 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
657 phy_data);
658 hw->mac.ops.release_swfw_sync(hw, gssr);
659 } else {
660 return IXGBE_ERR_SWFW_SYNC;
661 }
662
663 return status;
664}
665
666#define IXGBE_HW_READ_REG(addr) IXGBE_READ_REG(hw, addr)
667
668/**
669 * ixgbe_msca_cmd - Write the command register and poll for completion/timeout
670 * @hw: pointer to hardware structure
671 * @cmd: command register value to write
672 **/
673static s32 ixgbe_msca_cmd(struct ixgbe_hw *hw, u32 cmd)
674{
675 IXGBE_WRITE_REG(hw, IXGBE_MSCA, cmd);
676
677 return readx_poll_timeout(IXGBE_HW_READ_REG, IXGBE_MSCA, cmd,
678 !(cmd & IXGBE_MSCA_MDI_COMMAND), 10,
679 10 * IXGBE_MDIO_COMMAND_TIMEOUT);
680}
681
682/**
683 * ixgbe_mii_bus_read_generic - Read a clause 22/45 register with gssr flags
684 * @hw: pointer to hardware structure
685 * @addr: address
686 * @regnum: register number
687 * @gssr: semaphore flags to acquire
688 **/
689static s32 ixgbe_mii_bus_read_generic(struct ixgbe_hw *hw, int addr,
690 int regnum, u32 gssr)
691{
692 u32 hwaddr, cmd;
693 s32 data;
694
695 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
696 return -EBUSY;
697
698 hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
699 if (regnum & MII_ADDR_C45) {
700 hwaddr |= regnum & GENMASK(21, 0);
701 cmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND;
702 } else {
703 hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;
704 cmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL |
705 IXGBE_MSCA_READ_AUTOINC | IXGBE_MSCA_MDI_COMMAND;
706 }
707
708 data = ixgbe_msca_cmd(hw, cmd);
709 if (data < 0)
710 goto mii_bus_read_done;
711
712 /* For a clause 45 access the address cycle just completed, we still
713 * need to do the read command, otherwise just get the data
714 */
715 if (!(regnum & MII_ADDR_C45))
716 goto do_mii_bus_read;
717
718 cmd = hwaddr | IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND;
719 data = ixgbe_msca_cmd(hw, cmd);
720 if (data < 0)
721 goto mii_bus_read_done;
722
723do_mii_bus_read:
724 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
725 data = (data >> IXGBE_MSRWD_READ_DATA_SHIFT) & GENMASK(16, 0);
726
727mii_bus_read_done:
728 hw->mac.ops.release_swfw_sync(hw, gssr);
729 return data;
730}
731
732/**
733 * ixgbe_mii_bus_write_generic - Write a clause 22/45 register with gssr flags
734 * @hw: pointer to hardware structure
735 * @addr: address
736 * @regnum: register number
737 * @val: value to write
738 * @gssr: semaphore flags to acquire
739 **/
740static s32 ixgbe_mii_bus_write_generic(struct ixgbe_hw *hw, int addr,
741 int regnum, u16 val, u32 gssr)
742{
743 u32 hwaddr, cmd;
744 s32 err;
745
746 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
747 return -EBUSY;
748
749 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)val);
750
751 hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
752 if (regnum & MII_ADDR_C45) {
753 hwaddr |= regnum & GENMASK(21, 0);
754 cmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND;
755 } else {
756 hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;
757 cmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
758 IXGBE_MSCA_MDI_COMMAND;
759 }
760
761 /* For clause 45 this is an address cycle, for clause 22 this is the
762 * entire transaction
763 */
764 err = ixgbe_msca_cmd(hw, cmd);
765 if (err < 0 || !(regnum & MII_ADDR_C45))
766 goto mii_bus_write_done;
767
768 cmd = hwaddr | IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND;
769 err = ixgbe_msca_cmd(hw, cmd);
770
771mii_bus_write_done:
772 hw->mac.ops.release_swfw_sync(hw, gssr);
773 return err;
774}
775
776/**
777 * ixgbe_mii_bus_read - Read a clause 22/45 register
778 * @bus: pointer to mii_bus structure which points to our driver private
779 * @addr: address
780 * @regnum: register number
781 **/
782static s32 ixgbe_mii_bus_read(struct mii_bus *bus, int addr, int regnum)
783{
784 struct ixgbe_adapter *adapter = bus->priv;
785 struct ixgbe_hw *hw = &adapter->hw;
786 u32 gssr = hw->phy.phy_semaphore_mask;
787
788 return ixgbe_mii_bus_read_generic(hw, addr, regnum, gssr);
789}
790
791/**
792 * ixgbe_mii_bus_write - Write a clause 22/45 register
793 * @bus: pointer to mii_bus structure which points to our driver private
794 * @addr: address
795 * @regnum: register number
796 * @val: value to write
797 **/
798static s32 ixgbe_mii_bus_write(struct mii_bus *bus, int addr, int regnum,
799 u16 val)
800{
801 struct ixgbe_adapter *adapter = bus->priv;
802 struct ixgbe_hw *hw = &adapter->hw;
803 u32 gssr = hw->phy.phy_semaphore_mask;
804
805 return ixgbe_mii_bus_write_generic(hw, addr, regnum, val, gssr);
806}
807
808/**
809 * ixgbe_x550em_a_mii_bus_read - Read a clause 22/45 register on x550em_a
810 * @bus: pointer to mii_bus structure which points to our driver private
811 * @addr: address
812 * @regnum: register number
813 **/
814static s32 ixgbe_x550em_a_mii_bus_read(struct mii_bus *bus, int addr,
815 int regnum)
816{
817 struct ixgbe_adapter *adapter = bus->priv;
818 struct ixgbe_hw *hw = &adapter->hw;
819 u32 gssr = hw->phy.phy_semaphore_mask;
820
821 gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
822 return ixgbe_mii_bus_read_generic(hw, addr, regnum, gssr);
823}
824
825/**
826 * ixgbe_x550em_a_mii_bus_write - Write a clause 22/45 register on x550em_a
827 * @bus: pointer to mii_bus structure which points to our driver private
828 * @addr: address
829 * @regnum: register number
830 * @val: value to write
831 **/
832static s32 ixgbe_x550em_a_mii_bus_write(struct mii_bus *bus, int addr,
833 int regnum, u16 val)
834{
835 struct ixgbe_adapter *adapter = bus->priv;
836 struct ixgbe_hw *hw = &adapter->hw;
837 u32 gssr = hw->phy.phy_semaphore_mask;
838
839 gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
840 return ixgbe_mii_bus_write_generic(hw, addr, regnum, val, gssr);
841}
842
843/**
844 * ixgbe_get_first_secondary_devfn - get first device downstream of root port
845 * @devfn: PCI_DEVFN of root port on domain 0, bus 0
846 *
847 * Returns pci_dev pointer to PCI_DEVFN(0, 0) on subordinate side of root
848 * on domain 0, bus 0, devfn = 'devfn'
849 **/
850static struct pci_dev *ixgbe_get_first_secondary_devfn(unsigned int devfn)
851{
852 struct pci_dev *rp_pdev;
853 int bus;
854
855 rp_pdev = pci_get_domain_bus_and_slot(0, 0, devfn);
856 if (rp_pdev && rp_pdev->subordinate) {
857 bus = rp_pdev->subordinate->number;
858 return pci_get_domain_bus_and_slot(0, bus, 0);
859 }
860
861 return NULL;
862}
863
864/**
865 * ixgbe_x550em_a_has_mii - is this the first ixgbe x550em_a PCI function?
866 * @hw: pointer to hardware structure
867 *
868 * Returns true if hw points to lowest numbered PCI B:D.F x550_em_a device in
869 * the SoC. There are up to 4 MACs sharing a single MDIO bus on the x550em_a,
870 * but we only want to register one MDIO bus.
871 **/
872static bool ixgbe_x550em_a_has_mii(struct ixgbe_hw *hw)
873{
874 struct ixgbe_adapter *adapter = hw->back;
875 struct pci_dev *pdev = adapter->pdev;
876 struct pci_dev *func0_pdev;
877
878 /* For the C3000 family of SoCs (x550em_a) the internal ixgbe devices
879 * are always downstream of root ports @ 0000:00:16.0 & 0000:00:17.0
880 * It's not valid for function 0 to be disabled and function 1 is up,
881 * so the lowest numbered ixgbe dev will be device 0 function 0 on one
882 * of those two root ports
883 */
884 func0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x16, 0));
885 if (func0_pdev) {
886 if (func0_pdev == pdev)
887 return true;
888 else
889 return false;
890 }
891 func0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x17, 0));
892 if (func0_pdev == pdev)
893 return true;
894
895 return false;
896}
897
898/**
899 * ixgbe_mii_bus_init - mii_bus structure setup
900 * @hw: pointer to hardware structure
901 *
902 * Returns 0 on success, negative on failure
903 *
904 * ixgbe_mii_bus_init initializes a mii_bus structure in adapter
905 **/
906s32 ixgbe_mii_bus_init(struct ixgbe_hw *hw)
907{
908 s32 (*write)(struct mii_bus *bus, int addr, int regnum, u16 val);
909 s32 (*read)(struct mii_bus *bus, int addr, int regnum);
910 struct ixgbe_adapter *adapter = hw->back;
911 struct pci_dev *pdev = adapter->pdev;
912 struct device *dev = &adapter->netdev->dev;
913 struct mii_bus *bus;
914
915 switch (hw->device_id) {
916 /* C3000 SoCs */
917 case IXGBE_DEV_ID_X550EM_A_KR:
918 case IXGBE_DEV_ID_X550EM_A_KR_L:
919 case IXGBE_DEV_ID_X550EM_A_SFP_N:
920 case IXGBE_DEV_ID_X550EM_A_SGMII:
921 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
922 case IXGBE_DEV_ID_X550EM_A_10G_T:
923 case IXGBE_DEV_ID_X550EM_A_SFP:
924 case IXGBE_DEV_ID_X550EM_A_1G_T:
925 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
926 if (!ixgbe_x550em_a_has_mii(hw))
927 return 0;
928 read = &ixgbe_x550em_a_mii_bus_read;
929 write = &ixgbe_x550em_a_mii_bus_write;
930 break;
931 default:
932 read = &ixgbe_mii_bus_read;
933 write = &ixgbe_mii_bus_write;
934 break;
935 }
936
937 bus = devm_mdiobus_alloc(dev);
938 if (!bus)
939 return -ENOMEM;
940
941 bus->read = read;
942 bus->write = write;
943
944 /* Use the position of the device in the PCI hierarchy as the id */
945 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mdio-%s", ixgbe_driver_name,
946 pci_name(pdev));
947
948 bus->name = "ixgbe-mdio";
949 bus->priv = adapter;
950 bus->parent = dev;
951 bus->phy_mask = GENMASK(31, 0);
952
953 /* Support clause 22/45 natively. ixgbe_probe() sets MDIO_EMULATE_C22
954 * unfortunately that causes some clause 22 frames to be sent with
955 * clause 45 addressing. We don't want that.
956 */
957 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_SUPPORTS_C22;
958
959 adapter->mii_bus = bus;
960 return mdiobus_register(bus);
961}
962
963/**
964 * ixgbe_setup_phy_link_generic - Set and restart autoneg
965 * @hw: pointer to hardware structure
966 *
967 * Restart autonegotiation and PHY and waits for completion.
968 **/
969s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
970{
971 s32 status = 0;
972 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
973 bool autoneg = false;
974 ixgbe_link_speed speed;
975
976 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
977
978 /* Set or unset auto-negotiation 10G advertisement */
979 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, &autoneg_reg);
980
981 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
982 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
983 (speed & IXGBE_LINK_SPEED_10GB_FULL))
984 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
985
986 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, autoneg_reg);
987
988 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
989 MDIO_MMD_AN, &autoneg_reg);
990
991 if (hw->mac.type == ixgbe_mac_X550) {
992 /* Set or unset auto-negotiation 5G advertisement */
993 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
994 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
995 (speed & IXGBE_LINK_SPEED_5GB_FULL))
996 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
997
998 /* Set or unset auto-negotiation 2.5G advertisement */
999 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
1000 if ((hw->phy.autoneg_advertised &
1001 IXGBE_LINK_SPEED_2_5GB_FULL) &&
1002 (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
1003 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
1004 }
1005
1006 /* Set or unset auto-negotiation 1G advertisement */
1007 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
1008 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
1009 (speed & IXGBE_LINK_SPEED_1GB_FULL))
1010 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
1011
1012 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
1013 MDIO_MMD_AN, autoneg_reg);
1014
1015 /* Set or unset auto-negotiation 100M advertisement */
1016 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
1017
1018 autoneg_reg &= ~(ADVERTISE_100FULL | ADVERTISE_100HALF);
1019 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
1020 (speed & IXGBE_LINK_SPEED_100_FULL))
1021 autoneg_reg |= ADVERTISE_100FULL;
1022
1023 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
1024
1025 /* Blocked by MNG FW so don't reset PHY */
1026 if (ixgbe_check_reset_blocked(hw))
1027 return 0;
1028
1029 /* Restart PHY autonegotiation and wait for completion */
1030 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1031 MDIO_MMD_AN, &autoneg_reg);
1032
1033 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
1034
1035 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1036 MDIO_MMD_AN, autoneg_reg);
1037
1038 return status;
1039}
1040
1041/**
1042 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
1043 * @hw: pointer to hardware structure
1044 * @speed: new link speed
1045 * @autoneg_wait_to_complete: unused
1046 **/
1047s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
1048 ixgbe_link_speed speed,
1049 bool autoneg_wait_to_complete)
1050{
1051 /* Clear autoneg_advertised and set new values based on input link
1052 * speed.
1053 */
1054 hw->phy.autoneg_advertised = 0;
1055
1056 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1057 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
1058
1059 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
1060 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
1061
1062 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
1063 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
1064
1065 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1066 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
1067
1068 if (speed & IXGBE_LINK_SPEED_100_FULL)
1069 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
1070
1071 if (speed & IXGBE_LINK_SPEED_10_FULL)
1072 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
1073
1074 /* Setup link based on the new speed settings */
1075 if (hw->phy.ops.setup_link)
1076 hw->phy.ops.setup_link(hw);
1077
1078 return 0;
1079}
1080
1081/**
1082 * ixgbe_get_copper_speeds_supported - Get copper link speed from phy
1083 * @hw: pointer to hardware structure
1084 *
1085 * Determines the supported link capabilities by reading the PHY auto
1086 * negotiation register.
1087 */
1088static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
1089{
1090 u16 speed_ability;
1091 s32 status;
1092
1093 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
1094 &speed_ability);
1095 if (status)
1096 return status;
1097
1098 if (speed_ability & MDIO_SPEED_10G)
1099 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
1100 if (speed_ability & MDIO_PMA_SPEED_1000)
1101 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
1102 if (speed_ability & MDIO_PMA_SPEED_100)
1103 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
1104
1105 switch (hw->mac.type) {
1106 case ixgbe_mac_X550:
1107 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
1108 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
1109 break;
1110 case ixgbe_mac_X550EM_x:
1111 case ixgbe_mac_x550em_a:
1112 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
1113 break;
1114 default:
1115 break;
1116 }
1117
1118 return 0;
1119}
1120
1121/**
1122 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
1123 * @hw: pointer to hardware structure
1124 * @speed: pointer to link speed
1125 * @autoneg: boolean auto-negotiation value
1126 */
1127s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
1128 ixgbe_link_speed *speed,
1129 bool *autoneg)
1130{
1131 s32 status = 0;
1132
1133 *autoneg = true;
1134 if (!hw->phy.speeds_supported)
1135 status = ixgbe_get_copper_speeds_supported(hw);
1136
1137 *speed = hw->phy.speeds_supported;
1138 return status;
1139}
1140
1141/**
1142 * ixgbe_check_phy_link_tnx - Determine link and speed status
1143 * @hw: pointer to hardware structure
1144 * @speed: link speed
1145 * @link_up: status of link
1146 *
1147 * Reads the VS1 register to determine if link is up and the current speed for
1148 * the PHY.
1149 **/
1150s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1151 bool *link_up)
1152{
1153 s32 status;
1154 u32 time_out;
1155 u32 max_time_out = 10;
1156 u16 phy_link = 0;
1157 u16 phy_speed = 0;
1158 u16 phy_data = 0;
1159
1160 /* Initialize speed and link to default case */
1161 *link_up = false;
1162 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1163
1164 /*
1165 * Check current speed and link status of the PHY register.
1166 * This is a vendor specific register and may have to
1167 * be changed for other copper PHYs.
1168 */
1169 for (time_out = 0; time_out < max_time_out; time_out++) {
1170 udelay(10);
1171 status = hw->phy.ops.read_reg(hw,
1172 MDIO_STAT1,
1173 MDIO_MMD_VEND1,
1174 &phy_data);
1175 phy_link = phy_data &
1176 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1177 phy_speed = phy_data &
1178 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1179 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1180 *link_up = true;
1181 if (phy_speed ==
1182 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1183 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1184 break;
1185 }
1186 }
1187
1188 return status;
1189}
1190
1191/**
1192 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
1193 * @hw: pointer to hardware structure
1194 *
1195 * Restart autonegotiation and PHY and waits for completion.
1196 * This function always returns success, this is nessary since
1197 * it is called via a function pointer that could call other
1198 * functions that could return an error.
1199 **/
1200s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1201{
1202 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1203 bool autoneg = false;
1204 ixgbe_link_speed speed;
1205
1206 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1207
1208 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1209 /* Set or unset auto-negotiation 10G advertisement */
1210 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
1211 MDIO_MMD_AN,
1212 &autoneg_reg);
1213
1214 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
1215 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1216 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
1217
1218 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
1219 MDIO_MMD_AN,
1220 autoneg_reg);
1221 }
1222
1223 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1224 /* Set or unset auto-negotiation 1G advertisement */
1225 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1226 MDIO_MMD_AN,
1227 &autoneg_reg);
1228
1229 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1230 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1231 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1232
1233 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1234 MDIO_MMD_AN,
1235 autoneg_reg);
1236 }
1237
1238 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1239 /* Set or unset auto-negotiation 100M advertisement */
1240 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
1241 MDIO_MMD_AN,
1242 &autoneg_reg);
1243
1244 autoneg_reg &= ~(ADVERTISE_100FULL |
1245 ADVERTISE_100HALF);
1246 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1247 autoneg_reg |= ADVERTISE_100FULL;
1248
1249 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
1250 MDIO_MMD_AN,
1251 autoneg_reg);
1252 }
1253
1254 /* Blocked by MNG FW so don't reset PHY */
1255 if (ixgbe_check_reset_blocked(hw))
1256 return 0;
1257
1258 /* Restart PHY autonegotiation and wait for completion */
1259 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1260 MDIO_MMD_AN, &autoneg_reg);
1261
1262 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
1263
1264 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1265 MDIO_MMD_AN, autoneg_reg);
1266 return 0;
1267}
1268
1269/**
1270 * ixgbe_reset_phy_nl - Performs a PHY reset
1271 * @hw: pointer to hardware structure
1272 **/
1273s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1274{
1275 u16 phy_offset, control, eword, edata, block_crc;
1276 bool end_data = false;
1277 u16 list_offset, data_offset;
1278 u16 phy_data = 0;
1279 s32 ret_val;
1280 u32 i;
1281
1282 /* Blocked by MNG FW so bail */
1283 if (ixgbe_check_reset_blocked(hw))
1284 return 0;
1285
1286 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
1287
1288 /* reset the PHY and poll for completion */
1289 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1290 (phy_data | MDIO_CTRL1_RESET));
1291
1292 for (i = 0; i < 100; i++) {
1293 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1294 &phy_data);
1295 if ((phy_data & MDIO_CTRL1_RESET) == 0)
1296 break;
1297 usleep_range(10000, 20000);
1298 }
1299
1300 if ((phy_data & MDIO_CTRL1_RESET) != 0) {
1301 hw_dbg(hw, "PHY reset did not complete.\n");
1302 return IXGBE_ERR_PHY;
1303 }
1304
1305 /* Get init offsets */
1306 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1307 &data_offset);
1308 if (ret_val)
1309 return ret_val;
1310
1311 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1312 data_offset++;
1313 while (!end_data) {
1314 /*
1315 * Read control word from PHY init contents offset
1316 */
1317 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1318 if (ret_val)
1319 goto err_eeprom;
1320 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1321 IXGBE_CONTROL_SHIFT_NL;
1322 edata = eword & IXGBE_DATA_MASK_NL;
1323 switch (control) {
1324 case IXGBE_DELAY_NL:
1325 data_offset++;
1326 hw_dbg(hw, "DELAY: %d MS\n", edata);
1327 usleep_range(edata * 1000, edata * 2000);
1328 break;
1329 case IXGBE_DATA_NL:
1330 hw_dbg(hw, "DATA:\n");
1331 data_offset++;
1332 ret_val = hw->eeprom.ops.read(hw, data_offset++,
1333 &phy_offset);
1334 if (ret_val)
1335 goto err_eeprom;
1336 for (i = 0; i < edata; i++) {
1337 ret_val = hw->eeprom.ops.read(hw, data_offset,
1338 &eword);
1339 if (ret_val)
1340 goto err_eeprom;
1341 hw->phy.ops.write_reg(hw, phy_offset,
1342 MDIO_MMD_PMAPMD, eword);
1343 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
1344 phy_offset);
1345 data_offset++;
1346 phy_offset++;
1347 }
1348 break;
1349 case IXGBE_CONTROL_NL:
1350 data_offset++;
1351 hw_dbg(hw, "CONTROL:\n");
1352 if (edata == IXGBE_CONTROL_EOL_NL) {
1353 hw_dbg(hw, "EOL\n");
1354 end_data = true;
1355 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1356 hw_dbg(hw, "SOL\n");
1357 } else {
1358 hw_dbg(hw, "Bad control value\n");
1359 return IXGBE_ERR_PHY;
1360 }
1361 break;
1362 default:
1363 hw_dbg(hw, "Bad control type\n");
1364 return IXGBE_ERR_PHY;
1365 }
1366 }
1367
1368 return ret_val;
1369
1370err_eeprom:
1371 hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
1372 return IXGBE_ERR_PHY;
1373}
1374
1375/**
1376 * ixgbe_identify_module_generic - Identifies module type
1377 * @hw: pointer to hardware structure
1378 *
1379 * Determines HW type and calls appropriate function.
1380 **/
1381s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1382{
1383 switch (hw->mac.ops.get_media_type(hw)) {
1384 case ixgbe_media_type_fiber:
1385 return ixgbe_identify_sfp_module_generic(hw);
1386 case ixgbe_media_type_fiber_qsfp:
1387 return ixgbe_identify_qsfp_module_generic(hw);
1388 default:
1389 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1390 return IXGBE_ERR_SFP_NOT_PRESENT;
1391 }
1392
1393 return IXGBE_ERR_SFP_NOT_PRESENT;
1394}
1395
1396/**
1397 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1398 * @hw: pointer to hardware structure
1399 *
1400 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1401 **/
1402s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1403{
1404 struct ixgbe_adapter *adapter = hw->back;
1405 s32 status;
1406 u32 vendor_oui = 0;
1407 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1408 u8 identifier = 0;
1409 u8 comp_codes_1g = 0;
1410 u8 comp_codes_10g = 0;
1411 u8 oui_bytes[3] = {0, 0, 0};
1412 u8 cable_tech = 0;
1413 u8 cable_spec = 0;
1414 u16 enforce_sfp = 0;
1415
1416 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1417 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1418 return IXGBE_ERR_SFP_NOT_PRESENT;
1419 }
1420
1421 /* LAN ID is needed for sfp_type determination */
1422 hw->mac.ops.set_lan_id(hw);
1423
1424 status = hw->phy.ops.read_i2c_eeprom(hw,
1425 IXGBE_SFF_IDENTIFIER,
1426 &identifier);
1427
1428 if (status)
1429 goto err_read_i2c_eeprom;
1430
1431 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1432 hw->phy.type = ixgbe_phy_sfp_unsupported;
1433 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1434 }
1435 status = hw->phy.ops.read_i2c_eeprom(hw,
1436 IXGBE_SFF_1GBE_COMP_CODES,
1437 &comp_codes_1g);
1438
1439 if (status)
1440 goto err_read_i2c_eeprom;
1441
1442 status = hw->phy.ops.read_i2c_eeprom(hw,
1443 IXGBE_SFF_10GBE_COMP_CODES,
1444 &comp_codes_10g);
1445
1446 if (status)
1447 goto err_read_i2c_eeprom;
1448 status = hw->phy.ops.read_i2c_eeprom(hw,
1449 IXGBE_SFF_CABLE_TECHNOLOGY,
1450 &cable_tech);
1451
1452 if (status)
1453 goto err_read_i2c_eeprom;
1454
1455 /* ID Module
1456 * =========
1457 * 0 SFP_DA_CU
1458 * 1 SFP_SR
1459 * 2 SFP_LR
1460 * 3 SFP_DA_CORE0 - 82599-specific
1461 * 4 SFP_DA_CORE1 - 82599-specific
1462 * 5 SFP_SR/LR_CORE0 - 82599-specific
1463 * 6 SFP_SR/LR_CORE1 - 82599-specific
1464 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1465 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1466 * 9 SFP_1g_cu_CORE0 - 82599-specific
1467 * 10 SFP_1g_cu_CORE1 - 82599-specific
1468 * 11 SFP_1g_sx_CORE0 - 82599-specific
1469 * 12 SFP_1g_sx_CORE1 - 82599-specific
1470 */
1471 if (hw->mac.type == ixgbe_mac_82598EB) {
1472 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1473 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1474 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1475 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1476 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1477 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1478 else
1479 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1480 } else {
1481 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1482 if (hw->bus.lan_id == 0)
1483 hw->phy.sfp_type =
1484 ixgbe_sfp_type_da_cu_core0;
1485 else
1486 hw->phy.sfp_type =
1487 ixgbe_sfp_type_da_cu_core1;
1488 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1489 hw->phy.ops.read_i2c_eeprom(
1490 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1491 &cable_spec);
1492 if (cable_spec &
1493 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1494 if (hw->bus.lan_id == 0)
1495 hw->phy.sfp_type =
1496 ixgbe_sfp_type_da_act_lmt_core0;
1497 else
1498 hw->phy.sfp_type =
1499 ixgbe_sfp_type_da_act_lmt_core1;
1500 } else {
1501 hw->phy.sfp_type =
1502 ixgbe_sfp_type_unknown;
1503 }
1504 } else if (comp_codes_10g &
1505 (IXGBE_SFF_10GBASESR_CAPABLE |
1506 IXGBE_SFF_10GBASELR_CAPABLE)) {
1507 if (hw->bus.lan_id == 0)
1508 hw->phy.sfp_type =
1509 ixgbe_sfp_type_srlr_core0;
1510 else
1511 hw->phy.sfp_type =
1512 ixgbe_sfp_type_srlr_core1;
1513 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1514 if (hw->bus.lan_id == 0)
1515 hw->phy.sfp_type =
1516 ixgbe_sfp_type_1g_cu_core0;
1517 else
1518 hw->phy.sfp_type =
1519 ixgbe_sfp_type_1g_cu_core1;
1520 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1521 if (hw->bus.lan_id == 0)
1522 hw->phy.sfp_type =
1523 ixgbe_sfp_type_1g_sx_core0;
1524 else
1525 hw->phy.sfp_type =
1526 ixgbe_sfp_type_1g_sx_core1;
1527 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1528 if (hw->bus.lan_id == 0)
1529 hw->phy.sfp_type =
1530 ixgbe_sfp_type_1g_lx_core0;
1531 else
1532 hw->phy.sfp_type =
1533 ixgbe_sfp_type_1g_lx_core1;
1534 } else {
1535 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1536 }
1537 }
1538
1539 if (hw->phy.sfp_type != stored_sfp_type)
1540 hw->phy.sfp_setup_needed = true;
1541
1542 /* Determine if the SFP+ PHY is dual speed or not. */
1543 hw->phy.multispeed_fiber = false;
1544 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1545 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1546 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1547 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1548 hw->phy.multispeed_fiber = true;
1549
1550 /* Determine PHY vendor */
1551 if (hw->phy.type != ixgbe_phy_nl) {
1552 hw->phy.id = identifier;
1553 status = hw->phy.ops.read_i2c_eeprom(hw,
1554 IXGBE_SFF_VENDOR_OUI_BYTE0,
1555 &oui_bytes[0]);
1556
1557 if (status != 0)
1558 goto err_read_i2c_eeprom;
1559
1560 status = hw->phy.ops.read_i2c_eeprom(hw,
1561 IXGBE_SFF_VENDOR_OUI_BYTE1,
1562 &oui_bytes[1]);
1563
1564 if (status != 0)
1565 goto err_read_i2c_eeprom;
1566
1567 status = hw->phy.ops.read_i2c_eeprom(hw,
1568 IXGBE_SFF_VENDOR_OUI_BYTE2,
1569 &oui_bytes[2]);
1570
1571 if (status != 0)
1572 goto err_read_i2c_eeprom;
1573
1574 vendor_oui =
1575 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1576 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1577 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1578
1579 switch (vendor_oui) {
1580 case IXGBE_SFF_VENDOR_OUI_TYCO:
1581 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1582 hw->phy.type =
1583 ixgbe_phy_sfp_passive_tyco;
1584 break;
1585 case IXGBE_SFF_VENDOR_OUI_FTL:
1586 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1587 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1588 else
1589 hw->phy.type = ixgbe_phy_sfp_ftl;
1590 break;
1591 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1592 hw->phy.type = ixgbe_phy_sfp_avago;
1593 break;
1594 case IXGBE_SFF_VENDOR_OUI_INTEL:
1595 hw->phy.type = ixgbe_phy_sfp_intel;
1596 break;
1597 default:
1598 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1599 hw->phy.type =
1600 ixgbe_phy_sfp_passive_unknown;
1601 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1602 hw->phy.type =
1603 ixgbe_phy_sfp_active_unknown;
1604 else
1605 hw->phy.type = ixgbe_phy_sfp_unknown;
1606 break;
1607 }
1608 }
1609
1610 /* Allow any DA cable vendor */
1611 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1612 IXGBE_SFF_DA_ACTIVE_CABLE))
1613 return 0;
1614
1615 /* Verify supported 1G SFP modules */
1616 if (comp_codes_10g == 0 &&
1617 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1618 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1619 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1620 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1621 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1622 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1623 hw->phy.type = ixgbe_phy_sfp_unsupported;
1624 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1625 }
1626
1627 /* Anything else 82598-based is supported */
1628 if (hw->mac.type == ixgbe_mac_82598EB)
1629 return 0;
1630
1631 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1632 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1633 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1634 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1635 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1636 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1637 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1638 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1639 /* Make sure we're a supported PHY type */
1640 if (hw->phy.type == ixgbe_phy_sfp_intel)
1641 return 0;
1642 if (hw->allow_unsupported_sfp) {
1643 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1644 return 0;
1645 }
1646 hw_dbg(hw, "SFP+ module not supported\n");
1647 hw->phy.type = ixgbe_phy_sfp_unsupported;
1648 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1649 }
1650 return 0;
1651
1652err_read_i2c_eeprom:
1653 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1654 if (hw->phy.type != ixgbe_phy_nl) {
1655 hw->phy.id = 0;
1656 hw->phy.type = ixgbe_phy_unknown;
1657 }
1658 return IXGBE_ERR_SFP_NOT_PRESENT;
1659}
1660
1661/**
1662 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1663 * @hw: pointer to hardware structure
1664 *
1665 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1666 **/
1667static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1668{
1669 struct ixgbe_adapter *adapter = hw->back;
1670 s32 status;
1671 u32 vendor_oui = 0;
1672 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1673 u8 identifier = 0;
1674 u8 comp_codes_1g = 0;
1675 u8 comp_codes_10g = 0;
1676 u8 oui_bytes[3] = {0, 0, 0};
1677 u16 enforce_sfp = 0;
1678 u8 connector = 0;
1679 u8 cable_length = 0;
1680 u8 device_tech = 0;
1681 bool active_cable = false;
1682
1683 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1684 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1685 return IXGBE_ERR_SFP_NOT_PRESENT;
1686 }
1687
1688 /* LAN ID is needed for sfp_type determination */
1689 hw->mac.ops.set_lan_id(hw);
1690
1691 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1692 &identifier);
1693
1694 if (status != 0)
1695 goto err_read_i2c_eeprom;
1696
1697 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1698 hw->phy.type = ixgbe_phy_sfp_unsupported;
1699 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1700 }
1701
1702 hw->phy.id = identifier;
1703
1704 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1705 &comp_codes_10g);
1706
1707 if (status != 0)
1708 goto err_read_i2c_eeprom;
1709
1710 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1711 &comp_codes_1g);
1712
1713 if (status != 0)
1714 goto err_read_i2c_eeprom;
1715
1716 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1717 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1718 if (hw->bus.lan_id == 0)
1719 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1720 else
1721 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1722 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1723 IXGBE_SFF_10GBASELR_CAPABLE)) {
1724 if (hw->bus.lan_id == 0)
1725 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1726 else
1727 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1728 } else {
1729 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1730 active_cable = true;
1731
1732 if (!active_cable) {
1733 /* check for active DA cables that pre-date
1734 * SFF-8436 v3.6
1735 */
1736 hw->phy.ops.read_i2c_eeprom(hw,
1737 IXGBE_SFF_QSFP_CONNECTOR,
1738 &connector);
1739
1740 hw->phy.ops.read_i2c_eeprom(hw,
1741 IXGBE_SFF_QSFP_CABLE_LENGTH,
1742 &cable_length);
1743
1744 hw->phy.ops.read_i2c_eeprom(hw,
1745 IXGBE_SFF_QSFP_DEVICE_TECH,
1746 &device_tech);
1747
1748 if ((connector ==
1749 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1750 (cable_length > 0) &&
1751 ((device_tech >> 4) ==
1752 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1753 active_cable = true;
1754 }
1755
1756 if (active_cable) {
1757 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1758 if (hw->bus.lan_id == 0)
1759 hw->phy.sfp_type =
1760 ixgbe_sfp_type_da_act_lmt_core0;
1761 else
1762 hw->phy.sfp_type =
1763 ixgbe_sfp_type_da_act_lmt_core1;
1764 } else {
1765 /* unsupported module type */
1766 hw->phy.type = ixgbe_phy_sfp_unsupported;
1767 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1768 }
1769 }
1770
1771 if (hw->phy.sfp_type != stored_sfp_type)
1772 hw->phy.sfp_setup_needed = true;
1773
1774 /* Determine if the QSFP+ PHY is dual speed or not. */
1775 hw->phy.multispeed_fiber = false;
1776 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1777 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1778 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1779 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1780 hw->phy.multispeed_fiber = true;
1781
1782 /* Determine PHY vendor for optical modules */
1783 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1784 IXGBE_SFF_10GBASELR_CAPABLE)) {
1785 status = hw->phy.ops.read_i2c_eeprom(hw,
1786 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1787 &oui_bytes[0]);
1788
1789 if (status != 0)
1790 goto err_read_i2c_eeprom;
1791
1792 status = hw->phy.ops.read_i2c_eeprom(hw,
1793 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1794 &oui_bytes[1]);
1795
1796 if (status != 0)
1797 goto err_read_i2c_eeprom;
1798
1799 status = hw->phy.ops.read_i2c_eeprom(hw,
1800 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1801 &oui_bytes[2]);
1802
1803 if (status != 0)
1804 goto err_read_i2c_eeprom;
1805
1806 vendor_oui =
1807 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1808 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1809 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1810
1811 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1812 hw->phy.type = ixgbe_phy_qsfp_intel;
1813 else
1814 hw->phy.type = ixgbe_phy_qsfp_unknown;
1815
1816 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1817 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1818 /* Make sure we're a supported PHY type */
1819 if (hw->phy.type == ixgbe_phy_qsfp_intel)
1820 return 0;
1821 if (hw->allow_unsupported_sfp) {
1822 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1823 return 0;
1824 }
1825 hw_dbg(hw, "QSFP module not supported\n");
1826 hw->phy.type = ixgbe_phy_sfp_unsupported;
1827 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1828 }
1829 return 0;
1830 }
1831 return 0;
1832
1833err_read_i2c_eeprom:
1834 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1835 hw->phy.id = 0;
1836 hw->phy.type = ixgbe_phy_unknown;
1837
1838 return IXGBE_ERR_SFP_NOT_PRESENT;
1839}
1840
1841/**
1842 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1843 * @hw: pointer to hardware structure
1844 * @list_offset: offset to the SFP ID list
1845 * @data_offset: offset to the SFP data block
1846 *
1847 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1848 * so it returns the offsets to the phy init sequence block.
1849 **/
1850s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1851 u16 *list_offset,
1852 u16 *data_offset)
1853{
1854 u16 sfp_id;
1855 u16 sfp_type = hw->phy.sfp_type;
1856
1857 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1858 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1859
1860 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1861 return IXGBE_ERR_SFP_NOT_PRESENT;
1862
1863 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1864 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1865 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1866
1867 /*
1868 * Limiting active cables and 1G Phys must be initialized as
1869 * SR modules
1870 */
1871 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1872 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1873 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1874 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1875 sfp_type = ixgbe_sfp_type_srlr_core0;
1876 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1877 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1878 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1879 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1880 sfp_type = ixgbe_sfp_type_srlr_core1;
1881
1882 /* Read offset to PHY init contents */
1883 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1884 hw_err(hw, "eeprom read at %d failed\n",
1885 IXGBE_PHY_INIT_OFFSET_NL);
1886 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1887 }
1888
1889 if ((!*list_offset) || (*list_offset == 0xFFFF))
1890 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1891
1892 /* Shift offset to first ID word */
1893 (*list_offset)++;
1894
1895 /*
1896 * Find the matching SFP ID in the EEPROM
1897 * and program the init sequence
1898 */
1899 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1900 goto err_phy;
1901
1902 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1903 if (sfp_id == sfp_type) {
1904 (*list_offset)++;
1905 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1906 goto err_phy;
1907 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1908 hw_dbg(hw, "SFP+ module not supported\n");
1909 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1910 } else {
1911 break;
1912 }
1913 } else {
1914 (*list_offset) += 2;
1915 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1916 goto err_phy;
1917 }
1918 }
1919
1920 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1921 hw_dbg(hw, "No matching SFP+ module found\n");
1922 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1923 }
1924
1925 return 0;
1926
1927err_phy:
1928 hw_err(hw, "eeprom read at offset %d failed\n", *list_offset);
1929 return IXGBE_ERR_PHY;
1930}
1931
1932/**
1933 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1934 * @hw: pointer to hardware structure
1935 * @byte_offset: EEPROM byte offset to read
1936 * @eeprom_data: value read
1937 *
1938 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1939 **/
1940s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1941 u8 *eeprom_data)
1942{
1943 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1944 IXGBE_I2C_EEPROM_DEV_ADDR,
1945 eeprom_data);
1946}
1947
1948/**
1949 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1950 * @hw: pointer to hardware structure
1951 * @byte_offset: byte offset at address 0xA2
1952 * @sff8472_data: value read
1953 *
1954 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1955 **/
1956s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1957 u8 *sff8472_data)
1958{
1959 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1960 IXGBE_I2C_EEPROM_DEV_ADDR2,
1961 sff8472_data);
1962}
1963
1964/**
1965 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1966 * @hw: pointer to hardware structure
1967 * @byte_offset: EEPROM byte offset to write
1968 * @eeprom_data: value to write
1969 *
1970 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1971 **/
1972s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1973 u8 eeprom_data)
1974{
1975 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1976 IXGBE_I2C_EEPROM_DEV_ADDR,
1977 eeprom_data);
1978}
1979
1980/**
1981 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1982 * @hw: pointer to hardware structure
1983 * @offset: eeprom offset to be read
1984 * @addr: I2C address to be read
1985 */
1986static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1987{
1988 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1989 offset == IXGBE_SFF_IDENTIFIER &&
1990 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1991 return true;
1992 return false;
1993}
1994
1995/**
1996 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1997 * @hw: pointer to hardware structure
1998 * @byte_offset: byte offset to read
1999 * @dev_addr: device address
2000 * @data: value read
2001 * @lock: true if to take and release semaphore
2002 *
2003 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2004 * a specified device address.
2005 */
2006static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2007 u8 dev_addr, u8 *data, bool lock)
2008{
2009 s32 status;
2010 u32 max_retry = 10;
2011 u32 retry = 0;
2012 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2013 bool nack = true;
2014
2015 if (hw->mac.type >= ixgbe_mac_X550)
2016 max_retry = 3;
2017 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2018 max_retry = IXGBE_SFP_DETECT_RETRIES;
2019
2020 *data = 0;
2021
2022 do {
2023 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2024 return IXGBE_ERR_SWFW_SYNC;
2025
2026 ixgbe_i2c_start(hw);
2027
2028 /* Device Address and write indication */
2029 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2030 if (status != 0)
2031 goto fail;
2032
2033 status = ixgbe_get_i2c_ack(hw);
2034 if (status != 0)
2035 goto fail;
2036
2037 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2038 if (status != 0)
2039 goto fail;
2040
2041 status = ixgbe_get_i2c_ack(hw);
2042 if (status != 0)
2043 goto fail;
2044
2045 ixgbe_i2c_start(hw);
2046
2047 /* Device Address and read indication */
2048 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2049 if (status != 0)
2050 goto fail;
2051
2052 status = ixgbe_get_i2c_ack(hw);
2053 if (status != 0)
2054 goto fail;
2055
2056 status = ixgbe_clock_in_i2c_byte(hw, data);
2057 if (status != 0)
2058 goto fail;
2059
2060 status = ixgbe_clock_out_i2c_bit(hw, nack);
2061 if (status != 0)
2062 goto fail;
2063
2064 ixgbe_i2c_stop(hw);
2065 if (lock)
2066 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2067 return 0;
2068
2069fail:
2070 ixgbe_i2c_bus_clear(hw);
2071 if (lock) {
2072 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2073 msleep(100);
2074 }
2075 retry++;
2076 if (retry < max_retry)
2077 hw_dbg(hw, "I2C byte read error - Retrying.\n");
2078 else
2079 hw_dbg(hw, "I2C byte read error.\n");
2080
2081 } while (retry < max_retry);
2082
2083 return status;
2084}
2085
2086/**
2087 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2088 * @hw: pointer to hardware structure
2089 * @byte_offset: byte offset to read
2090 * @dev_addr: device address
2091 * @data: value read
2092 *
2093 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2094 * a specified device address.
2095 */
2096s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2097 u8 dev_addr, u8 *data)
2098{
2099 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2100 data, true);
2101}
2102
2103/**
2104 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2105 * @hw: pointer to hardware structure
2106 * @byte_offset: byte offset to read
2107 * @dev_addr: device address
2108 * @data: value read
2109 *
2110 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2111 * a specified device address.
2112 */
2113s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2114 u8 dev_addr, u8 *data)
2115{
2116 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2117 data, false);
2118}
2119
2120/**
2121 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2122 * @hw: pointer to hardware structure
2123 * @byte_offset: byte offset to write
2124 * @dev_addr: device address
2125 * @data: value to write
2126 * @lock: true if to take and release semaphore
2127 *
2128 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2129 * a specified device address.
2130 */
2131static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2132 u8 dev_addr, u8 data, bool lock)
2133{
2134 s32 status;
2135 u32 max_retry = 1;
2136 u32 retry = 0;
2137 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2138
2139 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2140 return IXGBE_ERR_SWFW_SYNC;
2141
2142 do {
2143 ixgbe_i2c_start(hw);
2144
2145 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2146 if (status != 0)
2147 goto fail;
2148
2149 status = ixgbe_get_i2c_ack(hw);
2150 if (status != 0)
2151 goto fail;
2152
2153 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2154 if (status != 0)
2155 goto fail;
2156
2157 status = ixgbe_get_i2c_ack(hw);
2158 if (status != 0)
2159 goto fail;
2160
2161 status = ixgbe_clock_out_i2c_byte(hw, data);
2162 if (status != 0)
2163 goto fail;
2164
2165 status = ixgbe_get_i2c_ack(hw);
2166 if (status != 0)
2167 goto fail;
2168
2169 ixgbe_i2c_stop(hw);
2170 if (lock)
2171 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2172 return 0;
2173
2174fail:
2175 ixgbe_i2c_bus_clear(hw);
2176 retry++;
2177 if (retry < max_retry)
2178 hw_dbg(hw, "I2C byte write error - Retrying.\n");
2179 else
2180 hw_dbg(hw, "I2C byte write error.\n");
2181 } while (retry < max_retry);
2182
2183 if (lock)
2184 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2185
2186 return status;
2187}
2188
2189/**
2190 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2191 * @hw: pointer to hardware structure
2192 * @byte_offset: byte offset to write
2193 * @dev_addr: device address
2194 * @data: value to write
2195 *
2196 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2197 * a specified device address.
2198 */
2199s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2200 u8 dev_addr, u8 data)
2201{
2202 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2203 data, true);
2204}
2205
2206/**
2207 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2208 * @hw: pointer to hardware structure
2209 * @byte_offset: byte offset to write
2210 * @dev_addr: device address
2211 * @data: value to write
2212 *
2213 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2214 * a specified device address.
2215 */
2216s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2217 u8 dev_addr, u8 data)
2218{
2219 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2220 data, false);
2221}
2222
2223/**
2224 * ixgbe_i2c_start - Sets I2C start condition
2225 * @hw: pointer to hardware structure
2226 *
2227 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2228 * Set bit-bang mode on X550 hardware.
2229 **/
2230static void ixgbe_i2c_start(struct ixgbe_hw *hw)
2231{
2232 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2233
2234 i2cctl |= IXGBE_I2C_BB_EN(hw);
2235
2236 /* Start condition must begin with data and clock high */
2237 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2238 ixgbe_raise_i2c_clk(hw, &i2cctl);
2239
2240 /* Setup time for start condition (4.7us) */
2241 udelay(IXGBE_I2C_T_SU_STA);
2242
2243 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2244
2245 /* Hold time for start condition (4us) */
2246 udelay(IXGBE_I2C_T_HD_STA);
2247
2248 ixgbe_lower_i2c_clk(hw, &i2cctl);
2249
2250 /* Minimum low period of clock is 4.7 us */
2251 udelay(IXGBE_I2C_T_LOW);
2252
2253}
2254
2255/**
2256 * ixgbe_i2c_stop - Sets I2C stop condition
2257 * @hw: pointer to hardware structure
2258 *
2259 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2260 * Disables bit-bang mode and negates data output enable on X550
2261 * hardware.
2262 **/
2263static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2264{
2265 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2266 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2267 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2268 u32 bb_en_bit = IXGBE_I2C_BB_EN(hw);
2269
2270 /* Stop condition must begin with data low and clock high */
2271 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2272 ixgbe_raise_i2c_clk(hw, &i2cctl);
2273
2274 /* Setup time for stop condition (4us) */
2275 udelay(IXGBE_I2C_T_SU_STO);
2276
2277 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2278
2279 /* bus free time between stop and start (4.7us)*/
2280 udelay(IXGBE_I2C_T_BUF);
2281
2282 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2283 i2cctl &= ~bb_en_bit;
2284 i2cctl |= data_oe_bit | clk_oe_bit;
2285 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2286 IXGBE_WRITE_FLUSH(hw);
2287 }
2288}
2289
2290/**
2291 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2292 * @hw: pointer to hardware structure
2293 * @data: data byte to clock in
2294 *
2295 * Clocks in one byte data via I2C data/clock
2296 **/
2297static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2298{
2299 s32 i;
2300 bool bit = false;
2301
2302 *data = 0;
2303 for (i = 7; i >= 0; i--) {
2304 ixgbe_clock_in_i2c_bit(hw, &bit);
2305 *data |= bit << i;
2306 }
2307
2308 return 0;
2309}
2310
2311/**
2312 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2313 * @hw: pointer to hardware structure
2314 * @data: data byte clocked out
2315 *
2316 * Clocks out one byte data via I2C data/clock
2317 **/
2318static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2319{
2320 s32 status;
2321 s32 i;
2322 u32 i2cctl;
2323 bool bit = false;
2324
2325 for (i = 7; i >= 0; i--) {
2326 bit = (data >> i) & 0x1;
2327 status = ixgbe_clock_out_i2c_bit(hw, bit);
2328
2329 if (status != 0)
2330 break;
2331 }
2332
2333 /* Release SDA line (set high) */
2334 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2335 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2336 i2cctl |= IXGBE_I2C_DATA_OE_N_EN(hw);
2337 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2338 IXGBE_WRITE_FLUSH(hw);
2339
2340 return status;
2341}
2342
2343/**
2344 * ixgbe_get_i2c_ack - Polls for I2C ACK
2345 * @hw: pointer to hardware structure
2346 *
2347 * Clocks in/out one bit via I2C data/clock
2348 **/
2349static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2350{
2351 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2352 s32 status = 0;
2353 u32 i = 0;
2354 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2355 u32 timeout = 10;
2356 bool ack = true;
2357
2358 if (data_oe_bit) {
2359 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2360 i2cctl |= data_oe_bit;
2361 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2362 IXGBE_WRITE_FLUSH(hw);
2363 }
2364 ixgbe_raise_i2c_clk(hw, &i2cctl);
2365
2366 /* Minimum high period of clock is 4us */
2367 udelay(IXGBE_I2C_T_HIGH);
2368
2369 /* Poll for ACK. Note that ACK in I2C spec is
2370 * transition from 1 to 0 */
2371 for (i = 0; i < timeout; i++) {
2372 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2373 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2374
2375 udelay(1);
2376 if (ack == 0)
2377 break;
2378 }
2379
2380 if (ack == 1) {
2381 hw_dbg(hw, "I2C ack was not received.\n");
2382 status = IXGBE_ERR_I2C;
2383 }
2384
2385 ixgbe_lower_i2c_clk(hw, &i2cctl);
2386
2387 /* Minimum low period of clock is 4.7 us */
2388 udelay(IXGBE_I2C_T_LOW);
2389
2390 return status;
2391}
2392
2393/**
2394 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2395 * @hw: pointer to hardware structure
2396 * @data: read data value
2397 *
2398 * Clocks in one bit via I2C data/clock
2399 **/
2400static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2401{
2402 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2403 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2404
2405 if (data_oe_bit) {
2406 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2407 i2cctl |= data_oe_bit;
2408 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2409 IXGBE_WRITE_FLUSH(hw);
2410 }
2411 ixgbe_raise_i2c_clk(hw, &i2cctl);
2412
2413 /* Minimum high period of clock is 4us */
2414 udelay(IXGBE_I2C_T_HIGH);
2415
2416 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2417 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2418
2419 ixgbe_lower_i2c_clk(hw, &i2cctl);
2420
2421 /* Minimum low period of clock is 4.7 us */
2422 udelay(IXGBE_I2C_T_LOW);
2423
2424 return 0;
2425}
2426
2427/**
2428 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2429 * @hw: pointer to hardware structure
2430 * @data: data value to write
2431 *
2432 * Clocks out one bit via I2C data/clock
2433 **/
2434static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2435{
2436 s32 status;
2437 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2438
2439 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2440 if (status == 0) {
2441 ixgbe_raise_i2c_clk(hw, &i2cctl);
2442
2443 /* Minimum high period of clock is 4us */
2444 udelay(IXGBE_I2C_T_HIGH);
2445
2446 ixgbe_lower_i2c_clk(hw, &i2cctl);
2447
2448 /* Minimum low period of clock is 4.7 us.
2449 * This also takes care of the data hold time.
2450 */
2451 udelay(IXGBE_I2C_T_LOW);
2452 } else {
2453 hw_dbg(hw, "I2C data was not set to %X\n", data);
2454 return IXGBE_ERR_I2C;
2455 }
2456
2457 return 0;
2458}
2459/**
2460 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2461 * @hw: pointer to hardware structure
2462 * @i2cctl: Current value of I2CCTL register
2463 *
2464 * Raises the I2C clock line '0'->'1'
2465 * Negates the I2C clock output enable on X550 hardware.
2466 **/
2467static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2468{
2469 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2470 u32 i = 0;
2471 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2472 u32 i2cctl_r = 0;
2473
2474 if (clk_oe_bit) {
2475 *i2cctl |= clk_oe_bit;
2476 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2477 }
2478
2479 for (i = 0; i < timeout; i++) {
2480 *i2cctl |= IXGBE_I2C_CLK_OUT(hw);
2481 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2482 IXGBE_WRITE_FLUSH(hw);
2483 /* SCL rise time (1000ns) */
2484 udelay(IXGBE_I2C_T_RISE);
2485
2486 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2487 if (i2cctl_r & IXGBE_I2C_CLK_IN(hw))
2488 break;
2489 }
2490}
2491
2492/**
2493 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2494 * @hw: pointer to hardware structure
2495 * @i2cctl: Current value of I2CCTL register
2496 *
2497 * Lowers the I2C clock line '1'->'0'
2498 * Asserts the I2C clock output enable on X550 hardware.
2499 **/
2500static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2501{
2502
2503 *i2cctl &= ~IXGBE_I2C_CLK_OUT(hw);
2504 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN(hw);
2505
2506 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2507 IXGBE_WRITE_FLUSH(hw);
2508
2509 /* SCL fall time (300ns) */
2510 udelay(IXGBE_I2C_T_FALL);
2511}
2512
2513/**
2514 * ixgbe_set_i2c_data - Sets the I2C data bit
2515 * @hw: pointer to hardware structure
2516 * @i2cctl: Current value of I2CCTL register
2517 * @data: I2C data value (0 or 1) to set
2518 *
2519 * Sets the I2C data bit
2520 * Asserts the I2C data output enable on X550 hardware.
2521 **/
2522static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2523{
2524 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2525
2526 if (data)
2527 *i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2528 else
2529 *i2cctl &= ~IXGBE_I2C_DATA_OUT(hw);
2530 *i2cctl &= ~data_oe_bit;
2531
2532 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2533 IXGBE_WRITE_FLUSH(hw);
2534
2535 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2536 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2537
2538 if (!data) /* Can't verify data in this case */
2539 return 0;
2540 if (data_oe_bit) {
2541 *i2cctl |= data_oe_bit;
2542 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2543 IXGBE_WRITE_FLUSH(hw);
2544 }
2545
2546 /* Verify data was set correctly */
2547 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2548 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2549 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
2550 return IXGBE_ERR_I2C;
2551 }
2552
2553 return 0;
2554}
2555
2556/**
2557 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2558 * @hw: pointer to hardware structure
2559 * @i2cctl: Current value of I2CCTL register
2560 *
2561 * Returns the I2C data bit value
2562 * Negates the I2C data output enable on X550 hardware.
2563 **/
2564static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2565{
2566 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2567
2568 if (data_oe_bit) {
2569 *i2cctl |= data_oe_bit;
2570 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2571 IXGBE_WRITE_FLUSH(hw);
2572 udelay(IXGBE_I2C_T_FALL);
2573 }
2574
2575 if (*i2cctl & IXGBE_I2C_DATA_IN(hw))
2576 return true;
2577 return false;
2578}
2579
2580/**
2581 * ixgbe_i2c_bus_clear - Clears the I2C bus
2582 * @hw: pointer to hardware structure
2583 *
2584 * Clears the I2C bus by sending nine clock pulses.
2585 * Used when data line is stuck low.
2586 **/
2587static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2588{
2589 u32 i2cctl;
2590 u32 i;
2591
2592 ixgbe_i2c_start(hw);
2593 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2594
2595 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2596
2597 for (i = 0; i < 9; i++) {
2598 ixgbe_raise_i2c_clk(hw, &i2cctl);
2599
2600 /* Min high period of clock is 4us */
2601 udelay(IXGBE_I2C_T_HIGH);
2602
2603 ixgbe_lower_i2c_clk(hw, &i2cctl);
2604
2605 /* Min low period of clock is 4.7us*/
2606 udelay(IXGBE_I2C_T_LOW);
2607 }
2608
2609 ixgbe_i2c_start(hw);
2610
2611 /* Put the i2c bus back to default state */
2612 ixgbe_i2c_stop(hw);
2613}
2614
2615/**
2616 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2617 * @hw: pointer to hardware structure
2618 *
2619 * Checks if the LASI temp alarm status was triggered due to overtemp
2620 **/
2621s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2622{
2623 u16 phy_data = 0;
2624
2625 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2626 return 0;
2627
2628 /* Check that the LASI temp alarm status was triggered */
2629 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2630 MDIO_MMD_PMAPMD, &phy_data);
2631
2632 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2633 return 0;
2634
2635 return IXGBE_ERR_OVERTEMP;
2636}
2637
2638/** ixgbe_set_copper_phy_power - Control power for copper phy
2639 * @hw: pointer to hardware structure
2640 * @on: true for on, false for off
2641 **/
2642s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2643{
2644 u32 status;
2645 u16 reg;
2646
2647 /* Bail if we don't have copper phy */
2648 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2649 return 0;
2650
2651 if (!on && ixgbe_mng_present(hw))
2652 return 0;
2653
2654 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, ®);
2655 if (status)
2656 return status;
2657
2658 if (on) {
2659 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2660 } else {
2661 if (ixgbe_check_reset_blocked(hw))
2662 return 0;
2663 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2664 }
2665
2666 status = hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, reg);
2667 return status;
2668}