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1/*
2 * tifm_sd.c - TI FlashMedia driver
3 *
4 * Copyright (C) 2006 Alex Dubov <oakad@yahoo.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Special thanks to Brad Campbell for extensive testing of this driver.
11 *
12 */
13
14
15#include <linux/tifm.h>
16#include <linux/mmc/host.h>
17#include <linux/highmem.h>
18#include <linux/scatterlist.h>
19#include <linux/module.h>
20#include <asm/io.h>
21
22#define DRIVER_NAME "tifm_sd"
23#define DRIVER_VERSION "0.8"
24
25static bool no_dma = 0;
26static bool fixed_timeout = 0;
27module_param(no_dma, bool, 0644);
28module_param(fixed_timeout, bool, 0644);
29
30/* Constants here are mostly from OMAP5912 datasheet */
31#define TIFM_MMCSD_RESET 0x0002
32#define TIFM_MMCSD_CLKMASK 0x03ff
33#define TIFM_MMCSD_POWER 0x0800
34#define TIFM_MMCSD_4BBUS 0x8000
35#define TIFM_MMCSD_RXDE 0x8000 /* rx dma enable */
36#define TIFM_MMCSD_TXDE 0x0080 /* tx dma enable */
37#define TIFM_MMCSD_BUFINT 0x0c00 /* set bits: AE, AF */
38#define TIFM_MMCSD_DPE 0x0020 /* data timeout counted in kilocycles */
39#define TIFM_MMCSD_INAB 0x0080 /* abort / initialize command */
40#define TIFM_MMCSD_READ 0x8000
41
42#define TIFM_MMCSD_ERRMASK 0x01e0 /* set bits: CCRC, CTO, DCRC, DTO */
43#define TIFM_MMCSD_EOC 0x0001 /* end of command phase */
44#define TIFM_MMCSD_CD 0x0002 /* card detect */
45#define TIFM_MMCSD_CB 0x0004 /* card enter busy state */
46#define TIFM_MMCSD_BRS 0x0008 /* block received/sent */
47#define TIFM_MMCSD_EOFB 0x0010 /* card exit busy state */
48#define TIFM_MMCSD_DTO 0x0020 /* data time-out */
49#define TIFM_MMCSD_DCRC 0x0040 /* data crc error */
50#define TIFM_MMCSD_CTO 0x0080 /* command time-out */
51#define TIFM_MMCSD_CCRC 0x0100 /* command crc error */
52#define TIFM_MMCSD_AF 0x0400 /* fifo almost full */
53#define TIFM_MMCSD_AE 0x0800 /* fifo almost empty */
54#define TIFM_MMCSD_OCRB 0x1000 /* OCR busy */
55#define TIFM_MMCSD_CIRQ 0x2000 /* card irq (cmd40/sdio) */
56#define TIFM_MMCSD_CERR 0x4000 /* card status error */
57
58#define TIFM_MMCSD_ODTO 0x0040 /* open drain / extended timeout */
59#define TIFM_MMCSD_CARD_RO 0x0200 /* card is read-only */
60
61#define TIFM_MMCSD_FIFO_SIZE 0x0020
62
63#define TIFM_MMCSD_RSP_R0 0x0000
64#define TIFM_MMCSD_RSP_R1 0x0100
65#define TIFM_MMCSD_RSP_R2 0x0200
66#define TIFM_MMCSD_RSP_R3 0x0300
67#define TIFM_MMCSD_RSP_R4 0x0400
68#define TIFM_MMCSD_RSP_R5 0x0500
69#define TIFM_MMCSD_RSP_R6 0x0600
70
71#define TIFM_MMCSD_RSP_BUSY 0x0800
72
73#define TIFM_MMCSD_CMD_BC 0x0000
74#define TIFM_MMCSD_CMD_BCR 0x1000
75#define TIFM_MMCSD_CMD_AC 0x2000
76#define TIFM_MMCSD_CMD_ADTC 0x3000
77
78#define TIFM_MMCSD_MAX_BLOCK_SIZE 0x0800UL
79
80enum {
81 CMD_READY = 0x0001,
82 FIFO_READY = 0x0002,
83 BRS_READY = 0x0004,
84 SCMD_ACTIVE = 0x0008,
85 SCMD_READY = 0x0010,
86 CARD_BUSY = 0x0020,
87 DATA_CARRY = 0x0040
88};
89
90struct tifm_sd {
91 struct tifm_dev *dev;
92
93 unsigned short eject:1,
94 open_drain:1,
95 no_dma:1;
96 unsigned short cmd_flags;
97
98 unsigned int clk_freq;
99 unsigned int clk_div;
100 unsigned long timeout_jiffies;
101
102 struct tasklet_struct finish_tasklet;
103 struct timer_list timer;
104 struct mmc_request *req;
105
106 int sg_len;
107 int sg_pos;
108 unsigned int block_pos;
109 struct scatterlist bounce_buf;
110 unsigned char bounce_buf_data[TIFM_MMCSD_MAX_BLOCK_SIZE];
111};
112
113/* for some reason, host won't respond correctly to readw/writew */
114static void tifm_sd_read_fifo(struct tifm_sd *host, struct page *pg,
115 unsigned int off, unsigned int cnt)
116{
117 struct tifm_dev *sock = host->dev;
118 unsigned char *buf;
119 unsigned int pos = 0, val;
120
121 buf = kmap_atomic(pg) + off;
122 if (host->cmd_flags & DATA_CARRY) {
123 buf[pos++] = host->bounce_buf_data[0];
124 host->cmd_flags &= ~DATA_CARRY;
125 }
126
127 while (pos < cnt) {
128 val = readl(sock->addr + SOCK_MMCSD_DATA);
129 buf[pos++] = val & 0xff;
130 if (pos == cnt) {
131 host->bounce_buf_data[0] = (val >> 8) & 0xff;
132 host->cmd_flags |= DATA_CARRY;
133 break;
134 }
135 buf[pos++] = (val >> 8) & 0xff;
136 }
137 kunmap_atomic(buf - off);
138}
139
140static void tifm_sd_write_fifo(struct tifm_sd *host, struct page *pg,
141 unsigned int off, unsigned int cnt)
142{
143 struct tifm_dev *sock = host->dev;
144 unsigned char *buf;
145 unsigned int pos = 0, val;
146
147 buf = kmap_atomic(pg) + off;
148 if (host->cmd_flags & DATA_CARRY) {
149 val = host->bounce_buf_data[0] | ((buf[pos++] << 8) & 0xff00);
150 writel(val, sock->addr + SOCK_MMCSD_DATA);
151 host->cmd_flags &= ~DATA_CARRY;
152 }
153
154 while (pos < cnt) {
155 val = buf[pos++];
156 if (pos == cnt) {
157 host->bounce_buf_data[0] = val & 0xff;
158 host->cmd_flags |= DATA_CARRY;
159 break;
160 }
161 val |= (buf[pos++] << 8) & 0xff00;
162 writel(val, sock->addr + SOCK_MMCSD_DATA);
163 }
164 kunmap_atomic(buf - off);
165}
166
167static void tifm_sd_transfer_data(struct tifm_sd *host)
168{
169 struct mmc_data *r_data = host->req->cmd->data;
170 struct scatterlist *sg = r_data->sg;
171 unsigned int off, cnt, t_size = TIFM_MMCSD_FIFO_SIZE * 2;
172 unsigned int p_off, p_cnt;
173 struct page *pg;
174
175 if (host->sg_pos == host->sg_len)
176 return;
177 while (t_size) {
178 cnt = sg[host->sg_pos].length - host->block_pos;
179 if (!cnt) {
180 host->block_pos = 0;
181 host->sg_pos++;
182 if (host->sg_pos == host->sg_len) {
183 if ((r_data->flags & MMC_DATA_WRITE)
184 && (host->cmd_flags & DATA_CARRY))
185 writel(host->bounce_buf_data[0],
186 host->dev->addr
187 + SOCK_MMCSD_DATA);
188
189 return;
190 }
191 cnt = sg[host->sg_pos].length;
192 }
193 off = sg[host->sg_pos].offset + host->block_pos;
194
195 pg = nth_page(sg_page(&sg[host->sg_pos]), off >> PAGE_SHIFT);
196 p_off = offset_in_page(off);
197 p_cnt = PAGE_SIZE - p_off;
198 p_cnt = min(p_cnt, cnt);
199 p_cnt = min(p_cnt, t_size);
200
201 if (r_data->flags & MMC_DATA_READ)
202 tifm_sd_read_fifo(host, pg, p_off, p_cnt);
203 else if (r_data->flags & MMC_DATA_WRITE)
204 tifm_sd_write_fifo(host, pg, p_off, p_cnt);
205
206 t_size -= p_cnt;
207 host->block_pos += p_cnt;
208 }
209}
210
211static void tifm_sd_copy_page(struct page *dst, unsigned int dst_off,
212 struct page *src, unsigned int src_off,
213 unsigned int count)
214{
215 unsigned char *src_buf = kmap_atomic(src) + src_off;
216 unsigned char *dst_buf = kmap_atomic(dst) + dst_off;
217
218 memcpy(dst_buf, src_buf, count);
219
220 kunmap_atomic(dst_buf - dst_off);
221 kunmap_atomic(src_buf - src_off);
222}
223
224static void tifm_sd_bounce_block(struct tifm_sd *host, struct mmc_data *r_data)
225{
226 struct scatterlist *sg = r_data->sg;
227 unsigned int t_size = r_data->blksz;
228 unsigned int off, cnt;
229 unsigned int p_off, p_cnt;
230 struct page *pg;
231
232 dev_dbg(&host->dev->dev, "bouncing block\n");
233 while (t_size) {
234 cnt = sg[host->sg_pos].length - host->block_pos;
235 if (!cnt) {
236 host->block_pos = 0;
237 host->sg_pos++;
238 if (host->sg_pos == host->sg_len)
239 return;
240 cnt = sg[host->sg_pos].length;
241 }
242 off = sg[host->sg_pos].offset + host->block_pos;
243
244 pg = nth_page(sg_page(&sg[host->sg_pos]), off >> PAGE_SHIFT);
245 p_off = offset_in_page(off);
246 p_cnt = PAGE_SIZE - p_off;
247 p_cnt = min(p_cnt, cnt);
248 p_cnt = min(p_cnt, t_size);
249
250 if (r_data->flags & MMC_DATA_WRITE)
251 tifm_sd_copy_page(sg_page(&host->bounce_buf),
252 r_data->blksz - t_size,
253 pg, p_off, p_cnt);
254 else if (r_data->flags & MMC_DATA_READ)
255 tifm_sd_copy_page(pg, p_off, sg_page(&host->bounce_buf),
256 r_data->blksz - t_size, p_cnt);
257
258 t_size -= p_cnt;
259 host->block_pos += p_cnt;
260 }
261}
262
263static int tifm_sd_set_dma_data(struct tifm_sd *host, struct mmc_data *r_data)
264{
265 struct tifm_dev *sock = host->dev;
266 unsigned int t_size = TIFM_DMA_TSIZE * r_data->blksz;
267 unsigned int dma_len, dma_blk_cnt, dma_off;
268 struct scatterlist *sg = NULL;
269 unsigned long flags;
270
271 if (host->sg_pos == host->sg_len)
272 return 1;
273
274 if (host->cmd_flags & DATA_CARRY) {
275 host->cmd_flags &= ~DATA_CARRY;
276 local_irq_save(flags);
277 tifm_sd_bounce_block(host, r_data);
278 local_irq_restore(flags);
279 if (host->sg_pos == host->sg_len)
280 return 1;
281 }
282
283 dma_len = sg_dma_len(&r_data->sg[host->sg_pos]) - host->block_pos;
284 if (!dma_len) {
285 host->block_pos = 0;
286 host->sg_pos++;
287 if (host->sg_pos == host->sg_len)
288 return 1;
289 dma_len = sg_dma_len(&r_data->sg[host->sg_pos]);
290 }
291
292 if (dma_len < t_size) {
293 dma_blk_cnt = dma_len / r_data->blksz;
294 dma_off = host->block_pos;
295 host->block_pos += dma_blk_cnt * r_data->blksz;
296 } else {
297 dma_blk_cnt = TIFM_DMA_TSIZE;
298 dma_off = host->block_pos;
299 host->block_pos += t_size;
300 }
301
302 if (dma_blk_cnt)
303 sg = &r_data->sg[host->sg_pos];
304 else if (dma_len) {
305 if (r_data->flags & MMC_DATA_WRITE) {
306 local_irq_save(flags);
307 tifm_sd_bounce_block(host, r_data);
308 local_irq_restore(flags);
309 } else
310 host->cmd_flags |= DATA_CARRY;
311
312 sg = &host->bounce_buf;
313 dma_off = 0;
314 dma_blk_cnt = 1;
315 } else
316 return 1;
317
318 dev_dbg(&sock->dev, "setting dma for %d blocks\n", dma_blk_cnt);
319 writel(sg_dma_address(sg) + dma_off, sock->addr + SOCK_DMA_ADDRESS);
320 if (r_data->flags & MMC_DATA_WRITE)
321 writel((dma_blk_cnt << 8) | TIFM_DMA_TX | TIFM_DMA_EN,
322 sock->addr + SOCK_DMA_CONTROL);
323 else
324 writel((dma_blk_cnt << 8) | TIFM_DMA_EN,
325 sock->addr + SOCK_DMA_CONTROL);
326
327 return 0;
328}
329
330static unsigned int tifm_sd_op_flags(struct mmc_command *cmd)
331{
332 unsigned int rc = 0;
333
334 switch (mmc_resp_type(cmd)) {
335 case MMC_RSP_NONE:
336 rc |= TIFM_MMCSD_RSP_R0;
337 break;
338 case MMC_RSP_R1B:
339 rc |= TIFM_MMCSD_RSP_BUSY; // deliberate fall-through
340 case MMC_RSP_R1:
341 rc |= TIFM_MMCSD_RSP_R1;
342 break;
343 case MMC_RSP_R2:
344 rc |= TIFM_MMCSD_RSP_R2;
345 break;
346 case MMC_RSP_R3:
347 rc |= TIFM_MMCSD_RSP_R3;
348 break;
349 default:
350 BUG();
351 }
352
353 switch (mmc_cmd_type(cmd)) {
354 case MMC_CMD_BC:
355 rc |= TIFM_MMCSD_CMD_BC;
356 break;
357 case MMC_CMD_BCR:
358 rc |= TIFM_MMCSD_CMD_BCR;
359 break;
360 case MMC_CMD_AC:
361 rc |= TIFM_MMCSD_CMD_AC;
362 break;
363 case MMC_CMD_ADTC:
364 rc |= TIFM_MMCSD_CMD_ADTC;
365 break;
366 default:
367 BUG();
368 }
369 return rc;
370}
371
372static void tifm_sd_exec(struct tifm_sd *host, struct mmc_command *cmd)
373{
374 struct tifm_dev *sock = host->dev;
375 unsigned int cmd_mask = tifm_sd_op_flags(cmd);
376
377 if (host->open_drain)
378 cmd_mask |= TIFM_MMCSD_ODTO;
379
380 if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
381 cmd_mask |= TIFM_MMCSD_READ;
382
383 dev_dbg(&sock->dev, "executing opcode 0x%x, arg: 0x%x, mask: 0x%x\n",
384 cmd->opcode, cmd->arg, cmd_mask);
385
386 writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH);
387 writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW);
388 writel(cmd->opcode | cmd_mask, sock->addr + SOCK_MMCSD_COMMAND);
389}
390
391static void tifm_sd_fetch_resp(struct mmc_command *cmd, struct tifm_dev *sock)
392{
393 cmd->resp[0] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x1c) << 16)
394 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x18);
395 cmd->resp[1] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x14) << 16)
396 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x10);
397 cmd->resp[2] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x0c) << 16)
398 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x08);
399 cmd->resp[3] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x04) << 16)
400 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x00);
401}
402
403static void tifm_sd_check_status(struct tifm_sd *host)
404{
405 struct tifm_dev *sock = host->dev;
406 struct mmc_command *cmd = host->req->cmd;
407
408 if (cmd->error)
409 goto finish_request;
410
411 if (!(host->cmd_flags & CMD_READY))
412 return;
413
414 if (cmd->data) {
415 if (cmd->data->error) {
416 if ((host->cmd_flags & SCMD_ACTIVE)
417 && !(host->cmd_flags & SCMD_READY))
418 return;
419
420 goto finish_request;
421 }
422
423 if (!(host->cmd_flags & BRS_READY))
424 return;
425
426 if (!(host->no_dma || (host->cmd_flags & FIFO_READY)))
427 return;
428
429 if (cmd->data->flags & MMC_DATA_WRITE) {
430 if (host->req->stop) {
431 if (!(host->cmd_flags & SCMD_ACTIVE)) {
432 host->cmd_flags |= SCMD_ACTIVE;
433 writel(TIFM_MMCSD_EOFB
434 | readl(sock->addr
435 + SOCK_MMCSD_INT_ENABLE),
436 sock->addr
437 + SOCK_MMCSD_INT_ENABLE);
438 tifm_sd_exec(host, host->req->stop);
439 return;
440 } else {
441 if (!(host->cmd_flags & SCMD_READY)
442 || (host->cmd_flags & CARD_BUSY))
443 return;
444 writel((~TIFM_MMCSD_EOFB)
445 & readl(sock->addr
446 + SOCK_MMCSD_INT_ENABLE),
447 sock->addr
448 + SOCK_MMCSD_INT_ENABLE);
449 }
450 } else {
451 if (host->cmd_flags & CARD_BUSY)
452 return;
453 writel((~TIFM_MMCSD_EOFB)
454 & readl(sock->addr
455 + SOCK_MMCSD_INT_ENABLE),
456 sock->addr + SOCK_MMCSD_INT_ENABLE);
457 }
458 } else {
459 if (host->req->stop) {
460 if (!(host->cmd_flags & SCMD_ACTIVE)) {
461 host->cmd_flags |= SCMD_ACTIVE;
462 tifm_sd_exec(host, host->req->stop);
463 return;
464 } else {
465 if (!(host->cmd_flags & SCMD_READY))
466 return;
467 }
468 }
469 }
470 }
471finish_request:
472 tasklet_schedule(&host->finish_tasklet);
473}
474
475/* Called from interrupt handler */
476static void tifm_sd_data_event(struct tifm_dev *sock)
477{
478 struct tifm_sd *host;
479 unsigned int fifo_status = 0;
480 struct mmc_data *r_data = NULL;
481
482 spin_lock(&sock->lock);
483 host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
484 fifo_status = readl(sock->addr + SOCK_DMA_FIFO_STATUS);
485 dev_dbg(&sock->dev, "data event: fifo_status %x, flags %x\n",
486 fifo_status, host->cmd_flags);
487
488 if (host->req) {
489 r_data = host->req->cmd->data;
490
491 if (r_data && (fifo_status & TIFM_FIFO_READY)) {
492 if (tifm_sd_set_dma_data(host, r_data)) {
493 host->cmd_flags |= FIFO_READY;
494 tifm_sd_check_status(host);
495 }
496 }
497 }
498
499 writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS);
500 spin_unlock(&sock->lock);
501}
502
503/* Called from interrupt handler */
504static void tifm_sd_card_event(struct tifm_dev *sock)
505{
506 struct tifm_sd *host;
507 unsigned int host_status = 0;
508 int cmd_error = 0;
509 struct mmc_command *cmd = NULL;
510 unsigned long flags;
511
512 spin_lock(&sock->lock);
513 host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
514 host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
515 dev_dbg(&sock->dev, "host event: host_status %x, flags %x\n",
516 host_status, host->cmd_flags);
517
518 if (host->req) {
519 cmd = host->req->cmd;
520
521 if (host_status & TIFM_MMCSD_ERRMASK) {
522 writel(host_status & TIFM_MMCSD_ERRMASK,
523 sock->addr + SOCK_MMCSD_STATUS);
524 if (host_status & TIFM_MMCSD_CTO)
525 cmd_error = -ETIMEDOUT;
526 else if (host_status & TIFM_MMCSD_CCRC)
527 cmd_error = -EILSEQ;
528
529 if (cmd->data) {
530 if (host_status & TIFM_MMCSD_DTO)
531 cmd->data->error = -ETIMEDOUT;
532 else if (host_status & TIFM_MMCSD_DCRC)
533 cmd->data->error = -EILSEQ;
534 }
535
536 writel(TIFM_FIFO_INT_SETALL,
537 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
538 writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
539
540 if (host->req->stop) {
541 if (host->cmd_flags & SCMD_ACTIVE) {
542 host->req->stop->error = cmd_error;
543 host->cmd_flags |= SCMD_READY;
544 } else {
545 cmd->error = cmd_error;
546 host->cmd_flags |= SCMD_ACTIVE;
547 tifm_sd_exec(host, host->req->stop);
548 goto done;
549 }
550 } else
551 cmd->error = cmd_error;
552 } else {
553 if (host_status & (TIFM_MMCSD_EOC | TIFM_MMCSD_CERR)) {
554 if (!(host->cmd_flags & CMD_READY)) {
555 host->cmd_flags |= CMD_READY;
556 tifm_sd_fetch_resp(cmd, sock);
557 } else if (host->cmd_flags & SCMD_ACTIVE) {
558 host->cmd_flags |= SCMD_READY;
559 tifm_sd_fetch_resp(host->req->stop,
560 sock);
561 }
562 }
563 if (host_status & TIFM_MMCSD_BRS)
564 host->cmd_flags |= BRS_READY;
565 }
566
567 if (host->no_dma && cmd->data) {
568 if (host_status & TIFM_MMCSD_AE)
569 writel(host_status & TIFM_MMCSD_AE,
570 sock->addr + SOCK_MMCSD_STATUS);
571
572 if (host_status & (TIFM_MMCSD_AE | TIFM_MMCSD_AF
573 | TIFM_MMCSD_BRS)) {
574 local_irq_save(flags);
575 tifm_sd_transfer_data(host);
576 local_irq_restore(flags);
577 host_status &= ~TIFM_MMCSD_AE;
578 }
579 }
580
581 if (host_status & TIFM_MMCSD_EOFB)
582 host->cmd_flags &= ~CARD_BUSY;
583 else if (host_status & TIFM_MMCSD_CB)
584 host->cmd_flags |= CARD_BUSY;
585
586 tifm_sd_check_status(host);
587 }
588done:
589 writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
590 spin_unlock(&sock->lock);
591}
592
593static void tifm_sd_set_data_timeout(struct tifm_sd *host,
594 struct mmc_data *data)
595{
596 struct tifm_dev *sock = host->dev;
597 unsigned int data_timeout = data->timeout_clks;
598
599 if (fixed_timeout)
600 return;
601
602 data_timeout += data->timeout_ns /
603 ((1000000000UL / host->clk_freq) * host->clk_div);
604
605 if (data_timeout < 0xffff) {
606 writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
607 writel((~TIFM_MMCSD_DPE)
608 & readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
609 sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
610 } else {
611 data_timeout = (data_timeout >> 10) + 1;
612 if (data_timeout > 0xffff)
613 data_timeout = 0; /* set to unlimited */
614 writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
615 writel(TIFM_MMCSD_DPE
616 | readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
617 sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
618 }
619}
620
621static void tifm_sd_request(struct mmc_host *mmc, struct mmc_request *mrq)
622{
623 struct tifm_sd *host = mmc_priv(mmc);
624 struct tifm_dev *sock = host->dev;
625 unsigned long flags;
626 struct mmc_data *r_data = mrq->cmd->data;
627
628 spin_lock_irqsave(&sock->lock, flags);
629 if (host->eject) {
630 mrq->cmd->error = -ENOMEDIUM;
631 goto err_out;
632 }
633
634 if (host->req) {
635 pr_err("%s : unfinished request detected\n",
636 dev_name(&sock->dev));
637 mrq->cmd->error = -ETIMEDOUT;
638 goto err_out;
639 }
640
641 host->cmd_flags = 0;
642 host->block_pos = 0;
643 host->sg_pos = 0;
644
645 if (mrq->data && !is_power_of_2(mrq->data->blksz))
646 host->no_dma = 1;
647 else
648 host->no_dma = no_dma ? 1 : 0;
649
650 if (r_data) {
651 tifm_sd_set_data_timeout(host, r_data);
652
653 if ((r_data->flags & MMC_DATA_WRITE) && !mrq->stop)
654 writel(TIFM_MMCSD_EOFB
655 | readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
656 sock->addr + SOCK_MMCSD_INT_ENABLE);
657
658 if (host->no_dma) {
659 writel(TIFM_MMCSD_BUFINT
660 | readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
661 sock->addr + SOCK_MMCSD_INT_ENABLE);
662 writel(((TIFM_MMCSD_FIFO_SIZE - 1) << 8)
663 | (TIFM_MMCSD_FIFO_SIZE - 1),
664 sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
665
666 host->sg_len = r_data->sg_len;
667 } else {
668 sg_init_one(&host->bounce_buf, host->bounce_buf_data,
669 r_data->blksz);
670
671 if(1 != tifm_map_sg(sock, &host->bounce_buf, 1,
672 r_data->flags & MMC_DATA_WRITE
673 ? PCI_DMA_TODEVICE
674 : PCI_DMA_FROMDEVICE)) {
675 pr_err("%s : scatterlist map failed\n",
676 dev_name(&sock->dev));
677 mrq->cmd->error = -ENOMEM;
678 goto err_out;
679 }
680 host->sg_len = tifm_map_sg(sock, r_data->sg,
681 r_data->sg_len,
682 r_data->flags
683 & MMC_DATA_WRITE
684 ? PCI_DMA_TODEVICE
685 : PCI_DMA_FROMDEVICE);
686 if (host->sg_len < 1) {
687 pr_err("%s : scatterlist map failed\n",
688 dev_name(&sock->dev));
689 tifm_unmap_sg(sock, &host->bounce_buf, 1,
690 r_data->flags & MMC_DATA_WRITE
691 ? PCI_DMA_TODEVICE
692 : PCI_DMA_FROMDEVICE);
693 mrq->cmd->error = -ENOMEM;
694 goto err_out;
695 }
696
697 writel(TIFM_FIFO_INT_SETALL,
698 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
699 writel(ilog2(r_data->blksz) - 2,
700 sock->addr + SOCK_FIFO_PAGE_SIZE);
701 writel(TIFM_FIFO_ENABLE,
702 sock->addr + SOCK_FIFO_CONTROL);
703 writel(TIFM_FIFO_INTMASK,
704 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
705
706 if (r_data->flags & MMC_DATA_WRITE)
707 writel(TIFM_MMCSD_TXDE,
708 sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
709 else
710 writel(TIFM_MMCSD_RXDE,
711 sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
712
713 tifm_sd_set_dma_data(host, r_data);
714 }
715
716 writel(r_data->blocks - 1,
717 sock->addr + SOCK_MMCSD_NUM_BLOCKS);
718 writel(r_data->blksz - 1,
719 sock->addr + SOCK_MMCSD_BLOCK_LEN);
720 }
721
722 host->req = mrq;
723 mod_timer(&host->timer, jiffies + host->timeout_jiffies);
724 writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
725 sock->addr + SOCK_CONTROL);
726 tifm_sd_exec(host, mrq->cmd);
727 spin_unlock_irqrestore(&sock->lock, flags);
728 return;
729
730err_out:
731 spin_unlock_irqrestore(&sock->lock, flags);
732 mmc_request_done(mmc, mrq);
733}
734
735static void tifm_sd_end_cmd(unsigned long data)
736{
737 struct tifm_sd *host = (struct tifm_sd*)data;
738 struct tifm_dev *sock = host->dev;
739 struct mmc_host *mmc = tifm_get_drvdata(sock);
740 struct mmc_request *mrq;
741 struct mmc_data *r_data = NULL;
742 unsigned long flags;
743
744 spin_lock_irqsave(&sock->lock, flags);
745
746 del_timer(&host->timer);
747 mrq = host->req;
748 host->req = NULL;
749
750 if (!mrq) {
751 pr_err(" %s : no request to complete?\n",
752 dev_name(&sock->dev));
753 spin_unlock_irqrestore(&sock->lock, flags);
754 return;
755 }
756
757 r_data = mrq->cmd->data;
758 if (r_data) {
759 if (host->no_dma) {
760 writel((~TIFM_MMCSD_BUFINT)
761 & readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
762 sock->addr + SOCK_MMCSD_INT_ENABLE);
763 } else {
764 tifm_unmap_sg(sock, &host->bounce_buf, 1,
765 (r_data->flags & MMC_DATA_WRITE)
766 ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
767 tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
768 (r_data->flags & MMC_DATA_WRITE)
769 ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
770 }
771
772 r_data->bytes_xfered = r_data->blocks
773 - readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
774 r_data->bytes_xfered *= r_data->blksz;
775 r_data->bytes_xfered += r_data->blksz
776 - readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
777 }
778
779 writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
780 sock->addr + SOCK_CONTROL);
781
782 spin_unlock_irqrestore(&sock->lock, flags);
783 mmc_request_done(mmc, mrq);
784}
785
786static void tifm_sd_abort(unsigned long data)
787{
788 struct tifm_sd *host = (struct tifm_sd*)data;
789
790 pr_err("%s : card failed to respond for a long period of time "
791 "(%x, %x)\n",
792 dev_name(&host->dev->dev), host->req->cmd->opcode, host->cmd_flags);
793
794 tifm_eject(host->dev);
795}
796
797static void tifm_sd_ios(struct mmc_host *mmc, struct mmc_ios *ios)
798{
799 struct tifm_sd *host = mmc_priv(mmc);
800 struct tifm_dev *sock = host->dev;
801 unsigned int clk_div1, clk_div2;
802 unsigned long flags;
803
804 spin_lock_irqsave(&sock->lock, flags);
805
806 dev_dbg(&sock->dev, "ios: clock = %u, vdd = %x, bus_mode = %x, "
807 "chip_select = %x, power_mode = %x, bus_width = %x\n",
808 ios->clock, ios->vdd, ios->bus_mode, ios->chip_select,
809 ios->power_mode, ios->bus_width);
810
811 if (ios->bus_width == MMC_BUS_WIDTH_4) {
812 writel(TIFM_MMCSD_4BBUS | readl(sock->addr + SOCK_MMCSD_CONFIG),
813 sock->addr + SOCK_MMCSD_CONFIG);
814 } else {
815 writel((~TIFM_MMCSD_4BBUS)
816 & readl(sock->addr + SOCK_MMCSD_CONFIG),
817 sock->addr + SOCK_MMCSD_CONFIG);
818 }
819
820 if (ios->clock) {
821 clk_div1 = 20000000 / ios->clock;
822 if (!clk_div1)
823 clk_div1 = 1;
824
825 clk_div2 = 24000000 / ios->clock;
826 if (!clk_div2)
827 clk_div2 = 1;
828
829 if ((20000000 / clk_div1) > ios->clock)
830 clk_div1++;
831 if ((24000000 / clk_div2) > ios->clock)
832 clk_div2++;
833 if ((20000000 / clk_div1) > (24000000 / clk_div2)) {
834 host->clk_freq = 20000000;
835 host->clk_div = clk_div1;
836 writel((~TIFM_CTRL_FAST_CLK)
837 & readl(sock->addr + SOCK_CONTROL),
838 sock->addr + SOCK_CONTROL);
839 } else {
840 host->clk_freq = 24000000;
841 host->clk_div = clk_div2;
842 writel(TIFM_CTRL_FAST_CLK
843 | readl(sock->addr + SOCK_CONTROL),
844 sock->addr + SOCK_CONTROL);
845 }
846 } else {
847 host->clk_div = 0;
848 }
849 host->clk_div &= TIFM_MMCSD_CLKMASK;
850 writel(host->clk_div
851 | ((~TIFM_MMCSD_CLKMASK)
852 & readl(sock->addr + SOCK_MMCSD_CONFIG)),
853 sock->addr + SOCK_MMCSD_CONFIG);
854
855 host->open_drain = (ios->bus_mode == MMC_BUSMODE_OPENDRAIN);
856
857 /* chip_select : maybe later */
858 //vdd
859 //power is set before probe / after remove
860
861 spin_unlock_irqrestore(&sock->lock, flags);
862}
863
864static int tifm_sd_ro(struct mmc_host *mmc)
865{
866 int rc = 0;
867 struct tifm_sd *host = mmc_priv(mmc);
868 struct tifm_dev *sock = host->dev;
869 unsigned long flags;
870
871 spin_lock_irqsave(&sock->lock, flags);
872 if (TIFM_MMCSD_CARD_RO & readl(sock->addr + SOCK_PRESENT_STATE))
873 rc = 1;
874 spin_unlock_irqrestore(&sock->lock, flags);
875 return rc;
876}
877
878static const struct mmc_host_ops tifm_sd_ops = {
879 .request = tifm_sd_request,
880 .set_ios = tifm_sd_ios,
881 .get_ro = tifm_sd_ro
882};
883
884static int tifm_sd_initialize_host(struct tifm_sd *host)
885{
886 int rc;
887 unsigned int host_status = 0;
888 struct tifm_dev *sock = host->dev;
889
890 writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
891 mmiowb();
892 host->clk_div = 61;
893 host->clk_freq = 20000000;
894 writel(TIFM_MMCSD_RESET, sock->addr + SOCK_MMCSD_SYSTEM_CONTROL);
895 writel(host->clk_div | TIFM_MMCSD_POWER,
896 sock->addr + SOCK_MMCSD_CONFIG);
897
898 /* wait up to 0.51 sec for reset */
899 for (rc = 32; rc <= 256; rc <<= 1) {
900 if (1 & readl(sock->addr + SOCK_MMCSD_SYSTEM_STATUS)) {
901 rc = 0;
902 break;
903 }
904 msleep(rc);
905 }
906
907 if (rc) {
908 pr_err("%s : controller failed to reset\n",
909 dev_name(&sock->dev));
910 return -ENODEV;
911 }
912
913 writel(0, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
914 writel(host->clk_div | TIFM_MMCSD_POWER,
915 sock->addr + SOCK_MMCSD_CONFIG);
916 writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
917
918 // command timeout fixed to 64 clocks for now
919 writel(64, sock->addr + SOCK_MMCSD_COMMAND_TO);
920 writel(TIFM_MMCSD_INAB, sock->addr + SOCK_MMCSD_COMMAND);
921
922 for (rc = 16; rc <= 64; rc <<= 1) {
923 host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
924 writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
925 if (!(host_status & TIFM_MMCSD_ERRMASK)
926 && (host_status & TIFM_MMCSD_EOC)) {
927 rc = 0;
928 break;
929 }
930 msleep(rc);
931 }
932
933 if (rc) {
934 pr_err("%s : card not ready - probe failed on initialization\n",
935 dev_name(&sock->dev));
936 return -ENODEV;
937 }
938
939 writel(TIFM_MMCSD_CERR | TIFM_MMCSD_BRS | TIFM_MMCSD_EOC
940 | TIFM_MMCSD_ERRMASK,
941 sock->addr + SOCK_MMCSD_INT_ENABLE);
942 mmiowb();
943
944 return 0;
945}
946
947static int tifm_sd_probe(struct tifm_dev *sock)
948{
949 struct mmc_host *mmc;
950 struct tifm_sd *host;
951 int rc = -EIO;
952
953 if (!(TIFM_SOCK_STATE_OCCUPIED
954 & readl(sock->addr + SOCK_PRESENT_STATE))) {
955 pr_warning("%s : card gone, unexpectedly\n",
956 dev_name(&sock->dev));
957 return rc;
958 }
959
960 mmc = mmc_alloc_host(sizeof(struct tifm_sd), &sock->dev);
961 if (!mmc)
962 return -ENOMEM;
963
964 host = mmc_priv(mmc);
965 tifm_set_drvdata(sock, mmc);
966 host->dev = sock;
967 host->timeout_jiffies = msecs_to_jiffies(1000);
968
969 tasklet_init(&host->finish_tasklet, tifm_sd_end_cmd,
970 (unsigned long)host);
971 setup_timer(&host->timer, tifm_sd_abort, (unsigned long)host);
972
973 mmc->ops = &tifm_sd_ops;
974 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
975 mmc->caps = MMC_CAP_4_BIT_DATA;
976 mmc->f_min = 20000000 / 60;
977 mmc->f_max = 24000000;
978
979 mmc->max_blk_count = 2048;
980 mmc->max_segs = mmc->max_blk_count;
981 mmc->max_blk_size = min(TIFM_MMCSD_MAX_BLOCK_SIZE, PAGE_SIZE);
982 mmc->max_seg_size = mmc->max_blk_count * mmc->max_blk_size;
983 mmc->max_req_size = mmc->max_seg_size;
984
985 sock->card_event = tifm_sd_card_event;
986 sock->data_event = tifm_sd_data_event;
987 rc = tifm_sd_initialize_host(host);
988
989 if (!rc)
990 rc = mmc_add_host(mmc);
991 if (!rc)
992 return 0;
993
994 mmc_free_host(mmc);
995 return rc;
996}
997
998static void tifm_sd_remove(struct tifm_dev *sock)
999{
1000 struct mmc_host *mmc = tifm_get_drvdata(sock);
1001 struct tifm_sd *host = mmc_priv(mmc);
1002 unsigned long flags;
1003
1004 spin_lock_irqsave(&sock->lock, flags);
1005 host->eject = 1;
1006 writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
1007 mmiowb();
1008 spin_unlock_irqrestore(&sock->lock, flags);
1009
1010 tasklet_kill(&host->finish_tasklet);
1011
1012 spin_lock_irqsave(&sock->lock, flags);
1013 if (host->req) {
1014 writel(TIFM_FIFO_INT_SETALL,
1015 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
1016 writel(0, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
1017 host->req->cmd->error = -ENOMEDIUM;
1018 if (host->req->stop)
1019 host->req->stop->error = -ENOMEDIUM;
1020 tasklet_schedule(&host->finish_tasklet);
1021 }
1022 spin_unlock_irqrestore(&sock->lock, flags);
1023 mmc_remove_host(mmc);
1024 dev_dbg(&sock->dev, "after remove\n");
1025
1026 mmc_free_host(mmc);
1027}
1028
1029#ifdef CONFIG_PM
1030
1031static int tifm_sd_suspend(struct tifm_dev *sock, pm_message_t state)
1032{
1033 return mmc_suspend_host(tifm_get_drvdata(sock));
1034}
1035
1036static int tifm_sd_resume(struct tifm_dev *sock)
1037{
1038 struct mmc_host *mmc = tifm_get_drvdata(sock);
1039 struct tifm_sd *host = mmc_priv(mmc);
1040 int rc;
1041
1042 rc = tifm_sd_initialize_host(host);
1043 dev_dbg(&sock->dev, "resume initialize %d\n", rc);
1044
1045 if (rc)
1046 host->eject = 1;
1047 else
1048 rc = mmc_resume_host(mmc);
1049
1050 return rc;
1051}
1052
1053#else
1054
1055#define tifm_sd_suspend NULL
1056#define tifm_sd_resume NULL
1057
1058#endif /* CONFIG_PM */
1059
1060static struct tifm_device_id tifm_sd_id_tbl[] = {
1061 { TIFM_TYPE_SD }, { }
1062};
1063
1064static struct tifm_driver tifm_sd_driver = {
1065 .driver = {
1066 .name = DRIVER_NAME,
1067 .owner = THIS_MODULE
1068 },
1069 .id_table = tifm_sd_id_tbl,
1070 .probe = tifm_sd_probe,
1071 .remove = tifm_sd_remove,
1072 .suspend = tifm_sd_suspend,
1073 .resume = tifm_sd_resume
1074};
1075
1076static int __init tifm_sd_init(void)
1077{
1078 return tifm_register_driver(&tifm_sd_driver);
1079}
1080
1081static void __exit tifm_sd_exit(void)
1082{
1083 tifm_unregister_driver(&tifm_sd_driver);
1084}
1085
1086MODULE_AUTHOR("Alex Dubov");
1087MODULE_DESCRIPTION("TI FlashMedia SD driver");
1088MODULE_LICENSE("GPL");
1089MODULE_DEVICE_TABLE(tifm, tifm_sd_id_tbl);
1090MODULE_VERSION(DRIVER_VERSION);
1091
1092module_init(tifm_sd_init);
1093module_exit(tifm_sd_exit);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * tifm_sd.c - TI FlashMedia driver
4 *
5 * Copyright (C) 2006 Alex Dubov <oakad@yahoo.com>
6 *
7 * Special thanks to Brad Campbell for extensive testing of this driver.
8 */
9
10
11#include <linux/tifm.h>
12#include <linux/mmc/host.h>
13#include <linux/highmem.h>
14#include <linux/scatterlist.h>
15#include <linux/module.h>
16#include <asm/io.h>
17
18#define DRIVER_NAME "tifm_sd"
19#define DRIVER_VERSION "0.8"
20
21static bool no_dma = 0;
22static bool fixed_timeout = 0;
23module_param(no_dma, bool, 0644);
24module_param(fixed_timeout, bool, 0644);
25
26/* Constants here are mostly from OMAP5912 datasheet */
27#define TIFM_MMCSD_RESET 0x0002
28#define TIFM_MMCSD_CLKMASK 0x03ff
29#define TIFM_MMCSD_POWER 0x0800
30#define TIFM_MMCSD_4BBUS 0x8000
31#define TIFM_MMCSD_RXDE 0x8000 /* rx dma enable */
32#define TIFM_MMCSD_TXDE 0x0080 /* tx dma enable */
33#define TIFM_MMCSD_BUFINT 0x0c00 /* set bits: AE, AF */
34#define TIFM_MMCSD_DPE 0x0020 /* data timeout counted in kilocycles */
35#define TIFM_MMCSD_INAB 0x0080 /* abort / initialize command */
36#define TIFM_MMCSD_READ 0x8000
37
38#define TIFM_MMCSD_ERRMASK 0x01e0 /* set bits: CCRC, CTO, DCRC, DTO */
39#define TIFM_MMCSD_EOC 0x0001 /* end of command phase */
40#define TIFM_MMCSD_CD 0x0002 /* card detect */
41#define TIFM_MMCSD_CB 0x0004 /* card enter busy state */
42#define TIFM_MMCSD_BRS 0x0008 /* block received/sent */
43#define TIFM_MMCSD_EOFB 0x0010 /* card exit busy state */
44#define TIFM_MMCSD_DTO 0x0020 /* data time-out */
45#define TIFM_MMCSD_DCRC 0x0040 /* data crc error */
46#define TIFM_MMCSD_CTO 0x0080 /* command time-out */
47#define TIFM_MMCSD_CCRC 0x0100 /* command crc error */
48#define TIFM_MMCSD_AF 0x0400 /* fifo almost full */
49#define TIFM_MMCSD_AE 0x0800 /* fifo almost empty */
50#define TIFM_MMCSD_OCRB 0x1000 /* OCR busy */
51#define TIFM_MMCSD_CIRQ 0x2000 /* card irq (cmd40/sdio) */
52#define TIFM_MMCSD_CERR 0x4000 /* card status error */
53
54#define TIFM_MMCSD_ODTO 0x0040 /* open drain / extended timeout */
55#define TIFM_MMCSD_CARD_RO 0x0200 /* card is read-only */
56
57#define TIFM_MMCSD_FIFO_SIZE 0x0020
58
59#define TIFM_MMCSD_RSP_R0 0x0000
60#define TIFM_MMCSD_RSP_R1 0x0100
61#define TIFM_MMCSD_RSP_R2 0x0200
62#define TIFM_MMCSD_RSP_R3 0x0300
63#define TIFM_MMCSD_RSP_R4 0x0400
64#define TIFM_MMCSD_RSP_R5 0x0500
65#define TIFM_MMCSD_RSP_R6 0x0600
66
67#define TIFM_MMCSD_RSP_BUSY 0x0800
68
69#define TIFM_MMCSD_CMD_BC 0x0000
70#define TIFM_MMCSD_CMD_BCR 0x1000
71#define TIFM_MMCSD_CMD_AC 0x2000
72#define TIFM_MMCSD_CMD_ADTC 0x3000
73
74#define TIFM_MMCSD_MAX_BLOCK_SIZE 0x0800UL
75
76#define TIFM_MMCSD_REQ_TIMEOUT_MS 1000
77
78enum {
79 CMD_READY = 0x0001,
80 FIFO_READY = 0x0002,
81 BRS_READY = 0x0004,
82 SCMD_ACTIVE = 0x0008,
83 SCMD_READY = 0x0010,
84 CARD_BUSY = 0x0020,
85 DATA_CARRY = 0x0040
86};
87
88struct tifm_sd {
89 struct tifm_dev *dev;
90
91 unsigned short eject:1,
92 open_drain:1,
93 no_dma:1;
94 unsigned short cmd_flags;
95
96 unsigned int clk_freq;
97 unsigned int clk_div;
98 unsigned long timeout_jiffies;
99
100 struct tasklet_struct finish_tasklet;
101 struct timer_list timer;
102 struct mmc_request *req;
103
104 int sg_len;
105 int sg_pos;
106 unsigned int block_pos;
107 struct scatterlist bounce_buf;
108 unsigned char bounce_buf_data[TIFM_MMCSD_MAX_BLOCK_SIZE];
109};
110
111/* for some reason, host won't respond correctly to readw/writew */
112static void tifm_sd_read_fifo(struct tifm_sd *host, struct page *pg,
113 unsigned int off, unsigned int cnt)
114{
115 struct tifm_dev *sock = host->dev;
116 unsigned char *buf;
117 unsigned int pos = 0, val;
118
119 buf = kmap_atomic(pg) + off;
120 if (host->cmd_flags & DATA_CARRY) {
121 buf[pos++] = host->bounce_buf_data[0];
122 host->cmd_flags &= ~DATA_CARRY;
123 }
124
125 while (pos < cnt) {
126 val = readl(sock->addr + SOCK_MMCSD_DATA);
127 buf[pos++] = val & 0xff;
128 if (pos == cnt) {
129 host->bounce_buf_data[0] = (val >> 8) & 0xff;
130 host->cmd_flags |= DATA_CARRY;
131 break;
132 }
133 buf[pos++] = (val >> 8) & 0xff;
134 }
135 kunmap_atomic(buf - off);
136}
137
138static void tifm_sd_write_fifo(struct tifm_sd *host, struct page *pg,
139 unsigned int off, unsigned int cnt)
140{
141 struct tifm_dev *sock = host->dev;
142 unsigned char *buf;
143 unsigned int pos = 0, val;
144
145 buf = kmap_atomic(pg) + off;
146 if (host->cmd_flags & DATA_CARRY) {
147 val = host->bounce_buf_data[0] | ((buf[pos++] << 8) & 0xff00);
148 writel(val, sock->addr + SOCK_MMCSD_DATA);
149 host->cmd_flags &= ~DATA_CARRY;
150 }
151
152 while (pos < cnt) {
153 val = buf[pos++];
154 if (pos == cnt) {
155 host->bounce_buf_data[0] = val & 0xff;
156 host->cmd_flags |= DATA_CARRY;
157 break;
158 }
159 val |= (buf[pos++] << 8) & 0xff00;
160 writel(val, sock->addr + SOCK_MMCSD_DATA);
161 }
162 kunmap_atomic(buf - off);
163}
164
165static void tifm_sd_transfer_data(struct tifm_sd *host)
166{
167 struct mmc_data *r_data = host->req->cmd->data;
168 struct scatterlist *sg = r_data->sg;
169 unsigned int off, cnt, t_size = TIFM_MMCSD_FIFO_SIZE * 2;
170 unsigned int p_off, p_cnt;
171 struct page *pg;
172
173 if (host->sg_pos == host->sg_len)
174 return;
175 while (t_size) {
176 cnt = sg[host->sg_pos].length - host->block_pos;
177 if (!cnt) {
178 host->block_pos = 0;
179 host->sg_pos++;
180 if (host->sg_pos == host->sg_len) {
181 if ((r_data->flags & MMC_DATA_WRITE)
182 && (host->cmd_flags & DATA_CARRY))
183 writel(host->bounce_buf_data[0],
184 host->dev->addr
185 + SOCK_MMCSD_DATA);
186
187 return;
188 }
189 cnt = sg[host->sg_pos].length;
190 }
191 off = sg[host->sg_pos].offset + host->block_pos;
192
193 pg = nth_page(sg_page(&sg[host->sg_pos]), off >> PAGE_SHIFT);
194 p_off = offset_in_page(off);
195 p_cnt = PAGE_SIZE - p_off;
196 p_cnt = min(p_cnt, cnt);
197 p_cnt = min(p_cnt, t_size);
198
199 if (r_data->flags & MMC_DATA_READ)
200 tifm_sd_read_fifo(host, pg, p_off, p_cnt);
201 else if (r_data->flags & MMC_DATA_WRITE)
202 tifm_sd_write_fifo(host, pg, p_off, p_cnt);
203
204 t_size -= p_cnt;
205 host->block_pos += p_cnt;
206 }
207}
208
209static void tifm_sd_copy_page(struct page *dst, unsigned int dst_off,
210 struct page *src, unsigned int src_off,
211 unsigned int count)
212{
213 unsigned char *src_buf = kmap_atomic(src) + src_off;
214 unsigned char *dst_buf = kmap_atomic(dst) + dst_off;
215
216 memcpy(dst_buf, src_buf, count);
217
218 kunmap_atomic(dst_buf - dst_off);
219 kunmap_atomic(src_buf - src_off);
220}
221
222static void tifm_sd_bounce_block(struct tifm_sd *host, struct mmc_data *r_data)
223{
224 struct scatterlist *sg = r_data->sg;
225 unsigned int t_size = r_data->blksz;
226 unsigned int off, cnt;
227 unsigned int p_off, p_cnt;
228 struct page *pg;
229
230 dev_dbg(&host->dev->dev, "bouncing block\n");
231 while (t_size) {
232 cnt = sg[host->sg_pos].length - host->block_pos;
233 if (!cnt) {
234 host->block_pos = 0;
235 host->sg_pos++;
236 if (host->sg_pos == host->sg_len)
237 return;
238 cnt = sg[host->sg_pos].length;
239 }
240 off = sg[host->sg_pos].offset + host->block_pos;
241
242 pg = nth_page(sg_page(&sg[host->sg_pos]), off >> PAGE_SHIFT);
243 p_off = offset_in_page(off);
244 p_cnt = PAGE_SIZE - p_off;
245 p_cnt = min(p_cnt, cnt);
246 p_cnt = min(p_cnt, t_size);
247
248 if (r_data->flags & MMC_DATA_WRITE)
249 tifm_sd_copy_page(sg_page(&host->bounce_buf),
250 r_data->blksz - t_size,
251 pg, p_off, p_cnt);
252 else if (r_data->flags & MMC_DATA_READ)
253 tifm_sd_copy_page(pg, p_off, sg_page(&host->bounce_buf),
254 r_data->blksz - t_size, p_cnt);
255
256 t_size -= p_cnt;
257 host->block_pos += p_cnt;
258 }
259}
260
261static int tifm_sd_set_dma_data(struct tifm_sd *host, struct mmc_data *r_data)
262{
263 struct tifm_dev *sock = host->dev;
264 unsigned int t_size = TIFM_DMA_TSIZE * r_data->blksz;
265 unsigned int dma_len, dma_blk_cnt, dma_off;
266 struct scatterlist *sg = NULL;
267 unsigned long flags;
268
269 if (host->sg_pos == host->sg_len)
270 return 1;
271
272 if (host->cmd_flags & DATA_CARRY) {
273 host->cmd_flags &= ~DATA_CARRY;
274 local_irq_save(flags);
275 tifm_sd_bounce_block(host, r_data);
276 local_irq_restore(flags);
277 if (host->sg_pos == host->sg_len)
278 return 1;
279 }
280
281 dma_len = sg_dma_len(&r_data->sg[host->sg_pos]) - host->block_pos;
282 if (!dma_len) {
283 host->block_pos = 0;
284 host->sg_pos++;
285 if (host->sg_pos == host->sg_len)
286 return 1;
287 dma_len = sg_dma_len(&r_data->sg[host->sg_pos]);
288 }
289
290 if (dma_len < t_size) {
291 dma_blk_cnt = dma_len / r_data->blksz;
292 dma_off = host->block_pos;
293 host->block_pos += dma_blk_cnt * r_data->blksz;
294 } else {
295 dma_blk_cnt = TIFM_DMA_TSIZE;
296 dma_off = host->block_pos;
297 host->block_pos += t_size;
298 }
299
300 if (dma_blk_cnt)
301 sg = &r_data->sg[host->sg_pos];
302 else if (dma_len) {
303 if (r_data->flags & MMC_DATA_WRITE) {
304 local_irq_save(flags);
305 tifm_sd_bounce_block(host, r_data);
306 local_irq_restore(flags);
307 } else
308 host->cmd_flags |= DATA_CARRY;
309
310 sg = &host->bounce_buf;
311 dma_off = 0;
312 dma_blk_cnt = 1;
313 } else
314 return 1;
315
316 dev_dbg(&sock->dev, "setting dma for %d blocks\n", dma_blk_cnt);
317 writel(sg_dma_address(sg) + dma_off, sock->addr + SOCK_DMA_ADDRESS);
318 if (r_data->flags & MMC_DATA_WRITE)
319 writel((dma_blk_cnt << 8) | TIFM_DMA_TX | TIFM_DMA_EN,
320 sock->addr + SOCK_DMA_CONTROL);
321 else
322 writel((dma_blk_cnt << 8) | TIFM_DMA_EN,
323 sock->addr + SOCK_DMA_CONTROL);
324
325 return 0;
326}
327
328static unsigned int tifm_sd_op_flags(struct mmc_command *cmd)
329{
330 unsigned int rc = 0;
331
332 switch (mmc_resp_type(cmd)) {
333 case MMC_RSP_NONE:
334 rc |= TIFM_MMCSD_RSP_R0;
335 break;
336 case MMC_RSP_R1B:
337 rc |= TIFM_MMCSD_RSP_BUSY;
338 fallthrough;
339 case MMC_RSP_R1:
340 rc |= TIFM_MMCSD_RSP_R1;
341 break;
342 case MMC_RSP_R2:
343 rc |= TIFM_MMCSD_RSP_R2;
344 break;
345 case MMC_RSP_R3:
346 rc |= TIFM_MMCSD_RSP_R3;
347 break;
348 default:
349 BUG();
350 }
351
352 switch (mmc_cmd_type(cmd)) {
353 case MMC_CMD_BC:
354 rc |= TIFM_MMCSD_CMD_BC;
355 break;
356 case MMC_CMD_BCR:
357 rc |= TIFM_MMCSD_CMD_BCR;
358 break;
359 case MMC_CMD_AC:
360 rc |= TIFM_MMCSD_CMD_AC;
361 break;
362 case MMC_CMD_ADTC:
363 rc |= TIFM_MMCSD_CMD_ADTC;
364 break;
365 default:
366 BUG();
367 }
368 return rc;
369}
370
371static void tifm_sd_exec(struct tifm_sd *host, struct mmc_command *cmd)
372{
373 struct tifm_dev *sock = host->dev;
374 unsigned int cmd_mask = tifm_sd_op_flags(cmd);
375
376 if (host->open_drain)
377 cmd_mask |= TIFM_MMCSD_ODTO;
378
379 if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
380 cmd_mask |= TIFM_MMCSD_READ;
381
382 dev_dbg(&sock->dev, "executing opcode 0x%x, arg: 0x%x, mask: 0x%x\n",
383 cmd->opcode, cmd->arg, cmd_mask);
384
385 writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH);
386 writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW);
387 writel(cmd->opcode | cmd_mask, sock->addr + SOCK_MMCSD_COMMAND);
388}
389
390static void tifm_sd_fetch_resp(struct mmc_command *cmd, struct tifm_dev *sock)
391{
392 cmd->resp[0] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x1c) << 16)
393 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x18);
394 cmd->resp[1] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x14) << 16)
395 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x10);
396 cmd->resp[2] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x0c) << 16)
397 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x08);
398 cmd->resp[3] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x04) << 16)
399 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x00);
400}
401
402static void tifm_sd_check_status(struct tifm_sd *host)
403{
404 struct tifm_dev *sock = host->dev;
405 struct mmc_command *cmd = host->req->cmd;
406
407 if (cmd->error)
408 goto finish_request;
409
410 if (!(host->cmd_flags & CMD_READY))
411 return;
412
413 if (cmd->data) {
414 if (cmd->data->error) {
415 if ((host->cmd_flags & SCMD_ACTIVE)
416 && !(host->cmd_flags & SCMD_READY))
417 return;
418
419 goto finish_request;
420 }
421
422 if (!(host->cmd_flags & BRS_READY))
423 return;
424
425 if (!(host->no_dma || (host->cmd_flags & FIFO_READY)))
426 return;
427
428 if (cmd->data->flags & MMC_DATA_WRITE) {
429 if (host->req->stop) {
430 if (!(host->cmd_flags & SCMD_ACTIVE)) {
431 host->cmd_flags |= SCMD_ACTIVE;
432 writel(TIFM_MMCSD_EOFB
433 | readl(sock->addr
434 + SOCK_MMCSD_INT_ENABLE),
435 sock->addr
436 + SOCK_MMCSD_INT_ENABLE);
437 tifm_sd_exec(host, host->req->stop);
438 return;
439 } else {
440 if (!(host->cmd_flags & SCMD_READY)
441 || (host->cmd_flags & CARD_BUSY))
442 return;
443 writel((~TIFM_MMCSD_EOFB)
444 & readl(sock->addr
445 + SOCK_MMCSD_INT_ENABLE),
446 sock->addr
447 + SOCK_MMCSD_INT_ENABLE);
448 }
449 } else {
450 if (host->cmd_flags & CARD_BUSY)
451 return;
452 writel((~TIFM_MMCSD_EOFB)
453 & readl(sock->addr
454 + SOCK_MMCSD_INT_ENABLE),
455 sock->addr + SOCK_MMCSD_INT_ENABLE);
456 }
457 } else {
458 if (host->req->stop) {
459 if (!(host->cmd_flags & SCMD_ACTIVE)) {
460 host->cmd_flags |= SCMD_ACTIVE;
461 tifm_sd_exec(host, host->req->stop);
462 return;
463 } else {
464 if (!(host->cmd_flags & SCMD_READY))
465 return;
466 }
467 }
468 }
469 }
470finish_request:
471 tasklet_schedule(&host->finish_tasklet);
472}
473
474/* Called from interrupt handler */
475static void tifm_sd_data_event(struct tifm_dev *sock)
476{
477 struct tifm_sd *host;
478 unsigned int fifo_status = 0;
479 struct mmc_data *r_data = NULL;
480
481 spin_lock(&sock->lock);
482 host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
483 fifo_status = readl(sock->addr + SOCK_DMA_FIFO_STATUS);
484 dev_dbg(&sock->dev, "data event: fifo_status %x, flags %x\n",
485 fifo_status, host->cmd_flags);
486
487 if (host->req) {
488 r_data = host->req->cmd->data;
489
490 if (r_data && (fifo_status & TIFM_FIFO_READY)) {
491 if (tifm_sd_set_dma_data(host, r_data)) {
492 host->cmd_flags |= FIFO_READY;
493 tifm_sd_check_status(host);
494 }
495 }
496 }
497
498 writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS);
499 spin_unlock(&sock->lock);
500}
501
502/* Called from interrupt handler */
503static void tifm_sd_card_event(struct tifm_dev *sock)
504{
505 struct tifm_sd *host;
506 unsigned int host_status = 0;
507 int cmd_error = 0;
508 struct mmc_command *cmd = NULL;
509 unsigned long flags;
510
511 spin_lock(&sock->lock);
512 host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
513 host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
514 dev_dbg(&sock->dev, "host event: host_status %x, flags %x\n",
515 host_status, host->cmd_flags);
516
517 if (host->req) {
518 cmd = host->req->cmd;
519
520 if (host_status & TIFM_MMCSD_ERRMASK) {
521 writel(host_status & TIFM_MMCSD_ERRMASK,
522 sock->addr + SOCK_MMCSD_STATUS);
523 if (host_status & TIFM_MMCSD_CTO)
524 cmd_error = -ETIMEDOUT;
525 else if (host_status & TIFM_MMCSD_CCRC)
526 cmd_error = -EILSEQ;
527
528 if (cmd->data) {
529 if (host_status & TIFM_MMCSD_DTO)
530 cmd->data->error = -ETIMEDOUT;
531 else if (host_status & TIFM_MMCSD_DCRC)
532 cmd->data->error = -EILSEQ;
533 }
534
535 writel(TIFM_FIFO_INT_SETALL,
536 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
537 writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
538
539 if (host->req->stop) {
540 if (host->cmd_flags & SCMD_ACTIVE) {
541 host->req->stop->error = cmd_error;
542 host->cmd_flags |= SCMD_READY;
543 } else {
544 cmd->error = cmd_error;
545 host->cmd_flags |= SCMD_ACTIVE;
546 tifm_sd_exec(host, host->req->stop);
547 goto done;
548 }
549 } else
550 cmd->error = cmd_error;
551 } else {
552 if (host_status & (TIFM_MMCSD_EOC | TIFM_MMCSD_CERR)) {
553 if (!(host->cmd_flags & CMD_READY)) {
554 host->cmd_flags |= CMD_READY;
555 tifm_sd_fetch_resp(cmd, sock);
556 } else if (host->cmd_flags & SCMD_ACTIVE) {
557 host->cmd_flags |= SCMD_READY;
558 tifm_sd_fetch_resp(host->req->stop,
559 sock);
560 }
561 }
562 if (host_status & TIFM_MMCSD_BRS)
563 host->cmd_flags |= BRS_READY;
564 }
565
566 if (host->no_dma && cmd->data) {
567 if (host_status & TIFM_MMCSD_AE)
568 writel(host_status & TIFM_MMCSD_AE,
569 sock->addr + SOCK_MMCSD_STATUS);
570
571 if (host_status & (TIFM_MMCSD_AE | TIFM_MMCSD_AF
572 | TIFM_MMCSD_BRS)) {
573 local_irq_save(flags);
574 tifm_sd_transfer_data(host);
575 local_irq_restore(flags);
576 host_status &= ~TIFM_MMCSD_AE;
577 }
578 }
579
580 if (host_status & TIFM_MMCSD_EOFB)
581 host->cmd_flags &= ~CARD_BUSY;
582 else if (host_status & TIFM_MMCSD_CB)
583 host->cmd_flags |= CARD_BUSY;
584
585 tifm_sd_check_status(host);
586 }
587done:
588 writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
589 spin_unlock(&sock->lock);
590}
591
592static void tifm_sd_set_data_timeout(struct tifm_sd *host,
593 struct mmc_data *data)
594{
595 struct tifm_dev *sock = host->dev;
596 unsigned int data_timeout = data->timeout_clks;
597
598 if (fixed_timeout)
599 return;
600
601 data_timeout += data->timeout_ns /
602 ((1000000000UL / host->clk_freq) * host->clk_div);
603
604 if (data_timeout < 0xffff) {
605 writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
606 writel((~TIFM_MMCSD_DPE)
607 & readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
608 sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
609 } else {
610 data_timeout = (data_timeout >> 10) + 1;
611 if (data_timeout > 0xffff)
612 data_timeout = 0; /* set to unlimited */
613 writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
614 writel(TIFM_MMCSD_DPE
615 | readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
616 sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
617 }
618}
619
620static void tifm_sd_request(struct mmc_host *mmc, struct mmc_request *mrq)
621{
622 struct tifm_sd *host = mmc_priv(mmc);
623 struct tifm_dev *sock = host->dev;
624 unsigned long flags;
625 struct mmc_data *r_data = mrq->cmd->data;
626
627 spin_lock_irqsave(&sock->lock, flags);
628 if (host->eject) {
629 mrq->cmd->error = -ENOMEDIUM;
630 goto err_out;
631 }
632
633 if (host->req) {
634 pr_err("%s : unfinished request detected\n",
635 dev_name(&sock->dev));
636 mrq->cmd->error = -ETIMEDOUT;
637 goto err_out;
638 }
639
640 host->cmd_flags = 0;
641 host->block_pos = 0;
642 host->sg_pos = 0;
643
644 if (mrq->data && !is_power_of_2(mrq->data->blksz))
645 host->no_dma = 1;
646 else
647 host->no_dma = no_dma ? 1 : 0;
648
649 if (r_data) {
650 tifm_sd_set_data_timeout(host, r_data);
651
652 if ((r_data->flags & MMC_DATA_WRITE) && !mrq->stop)
653 writel(TIFM_MMCSD_EOFB
654 | readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
655 sock->addr + SOCK_MMCSD_INT_ENABLE);
656
657 if (host->no_dma) {
658 writel(TIFM_MMCSD_BUFINT
659 | readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
660 sock->addr + SOCK_MMCSD_INT_ENABLE);
661 writel(((TIFM_MMCSD_FIFO_SIZE - 1) << 8)
662 | (TIFM_MMCSD_FIFO_SIZE - 1),
663 sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
664
665 host->sg_len = r_data->sg_len;
666 } else {
667 sg_init_one(&host->bounce_buf, host->bounce_buf_data,
668 r_data->blksz);
669
670 if(1 != tifm_map_sg(sock, &host->bounce_buf, 1,
671 r_data->flags & MMC_DATA_WRITE
672 ? PCI_DMA_TODEVICE
673 : PCI_DMA_FROMDEVICE)) {
674 pr_err("%s : scatterlist map failed\n",
675 dev_name(&sock->dev));
676 mrq->cmd->error = -ENOMEM;
677 goto err_out;
678 }
679 host->sg_len = tifm_map_sg(sock, r_data->sg,
680 r_data->sg_len,
681 r_data->flags
682 & MMC_DATA_WRITE
683 ? PCI_DMA_TODEVICE
684 : PCI_DMA_FROMDEVICE);
685 if (host->sg_len < 1) {
686 pr_err("%s : scatterlist map failed\n",
687 dev_name(&sock->dev));
688 tifm_unmap_sg(sock, &host->bounce_buf, 1,
689 r_data->flags & MMC_DATA_WRITE
690 ? PCI_DMA_TODEVICE
691 : PCI_DMA_FROMDEVICE);
692 mrq->cmd->error = -ENOMEM;
693 goto err_out;
694 }
695
696 writel(TIFM_FIFO_INT_SETALL,
697 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
698 writel(ilog2(r_data->blksz) - 2,
699 sock->addr + SOCK_FIFO_PAGE_SIZE);
700 writel(TIFM_FIFO_ENABLE,
701 sock->addr + SOCK_FIFO_CONTROL);
702 writel(TIFM_FIFO_INTMASK,
703 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
704
705 if (r_data->flags & MMC_DATA_WRITE)
706 writel(TIFM_MMCSD_TXDE,
707 sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
708 else
709 writel(TIFM_MMCSD_RXDE,
710 sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
711
712 tifm_sd_set_dma_data(host, r_data);
713 }
714
715 writel(r_data->blocks - 1,
716 sock->addr + SOCK_MMCSD_NUM_BLOCKS);
717 writel(r_data->blksz - 1,
718 sock->addr + SOCK_MMCSD_BLOCK_LEN);
719 }
720
721 host->req = mrq;
722 mod_timer(&host->timer, jiffies + host->timeout_jiffies);
723 writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
724 sock->addr + SOCK_CONTROL);
725 tifm_sd_exec(host, mrq->cmd);
726 spin_unlock_irqrestore(&sock->lock, flags);
727 return;
728
729err_out:
730 spin_unlock_irqrestore(&sock->lock, flags);
731 mmc_request_done(mmc, mrq);
732}
733
734static void tifm_sd_end_cmd(struct tasklet_struct *t)
735{
736 struct tifm_sd *host = from_tasklet(host, t, finish_tasklet);
737 struct tifm_dev *sock = host->dev;
738 struct mmc_host *mmc = tifm_get_drvdata(sock);
739 struct mmc_request *mrq;
740 struct mmc_data *r_data = NULL;
741 unsigned long flags;
742
743 spin_lock_irqsave(&sock->lock, flags);
744
745 del_timer(&host->timer);
746 mrq = host->req;
747 host->req = NULL;
748
749 if (!mrq) {
750 pr_err(" %s : no request to complete?\n",
751 dev_name(&sock->dev));
752 spin_unlock_irqrestore(&sock->lock, flags);
753 return;
754 }
755
756 r_data = mrq->cmd->data;
757 if (r_data) {
758 if (host->no_dma) {
759 writel((~TIFM_MMCSD_BUFINT)
760 & readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
761 sock->addr + SOCK_MMCSD_INT_ENABLE);
762 } else {
763 tifm_unmap_sg(sock, &host->bounce_buf, 1,
764 (r_data->flags & MMC_DATA_WRITE)
765 ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
766 tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
767 (r_data->flags & MMC_DATA_WRITE)
768 ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
769 }
770
771 r_data->bytes_xfered = r_data->blocks
772 - readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
773 r_data->bytes_xfered *= r_data->blksz;
774 r_data->bytes_xfered += r_data->blksz
775 - readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
776 }
777
778 writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
779 sock->addr + SOCK_CONTROL);
780
781 spin_unlock_irqrestore(&sock->lock, flags);
782 mmc_request_done(mmc, mrq);
783}
784
785static void tifm_sd_abort(struct timer_list *t)
786{
787 struct tifm_sd *host = from_timer(host, t, timer);
788
789 pr_err("%s : card failed to respond for a long period of time "
790 "(%x, %x)\n",
791 dev_name(&host->dev->dev), host->req->cmd->opcode, host->cmd_flags);
792
793 tifm_eject(host->dev);
794}
795
796static void tifm_sd_ios(struct mmc_host *mmc, struct mmc_ios *ios)
797{
798 struct tifm_sd *host = mmc_priv(mmc);
799 struct tifm_dev *sock = host->dev;
800 unsigned int clk_div1, clk_div2;
801 unsigned long flags;
802
803 spin_lock_irqsave(&sock->lock, flags);
804
805 dev_dbg(&sock->dev, "ios: clock = %u, vdd = %x, bus_mode = %x, "
806 "chip_select = %x, power_mode = %x, bus_width = %x\n",
807 ios->clock, ios->vdd, ios->bus_mode, ios->chip_select,
808 ios->power_mode, ios->bus_width);
809
810 if (ios->bus_width == MMC_BUS_WIDTH_4) {
811 writel(TIFM_MMCSD_4BBUS | readl(sock->addr + SOCK_MMCSD_CONFIG),
812 sock->addr + SOCK_MMCSD_CONFIG);
813 } else {
814 writel((~TIFM_MMCSD_4BBUS)
815 & readl(sock->addr + SOCK_MMCSD_CONFIG),
816 sock->addr + SOCK_MMCSD_CONFIG);
817 }
818
819 if (ios->clock) {
820 clk_div1 = 20000000 / ios->clock;
821 if (!clk_div1)
822 clk_div1 = 1;
823
824 clk_div2 = 24000000 / ios->clock;
825 if (!clk_div2)
826 clk_div2 = 1;
827
828 if ((20000000 / clk_div1) > ios->clock)
829 clk_div1++;
830 if ((24000000 / clk_div2) > ios->clock)
831 clk_div2++;
832 if ((20000000 / clk_div1) > (24000000 / clk_div2)) {
833 host->clk_freq = 20000000;
834 host->clk_div = clk_div1;
835 writel((~TIFM_CTRL_FAST_CLK)
836 & readl(sock->addr + SOCK_CONTROL),
837 sock->addr + SOCK_CONTROL);
838 } else {
839 host->clk_freq = 24000000;
840 host->clk_div = clk_div2;
841 writel(TIFM_CTRL_FAST_CLK
842 | readl(sock->addr + SOCK_CONTROL),
843 sock->addr + SOCK_CONTROL);
844 }
845 } else {
846 host->clk_div = 0;
847 }
848 host->clk_div &= TIFM_MMCSD_CLKMASK;
849 writel(host->clk_div
850 | ((~TIFM_MMCSD_CLKMASK)
851 & readl(sock->addr + SOCK_MMCSD_CONFIG)),
852 sock->addr + SOCK_MMCSD_CONFIG);
853
854 host->open_drain = (ios->bus_mode == MMC_BUSMODE_OPENDRAIN);
855
856 /* chip_select : maybe later */
857 //vdd
858 //power is set before probe / after remove
859
860 spin_unlock_irqrestore(&sock->lock, flags);
861}
862
863static int tifm_sd_ro(struct mmc_host *mmc)
864{
865 int rc = 0;
866 struct tifm_sd *host = mmc_priv(mmc);
867 struct tifm_dev *sock = host->dev;
868 unsigned long flags;
869
870 spin_lock_irqsave(&sock->lock, flags);
871 if (TIFM_MMCSD_CARD_RO & readl(sock->addr + SOCK_PRESENT_STATE))
872 rc = 1;
873 spin_unlock_irqrestore(&sock->lock, flags);
874 return rc;
875}
876
877static const struct mmc_host_ops tifm_sd_ops = {
878 .request = tifm_sd_request,
879 .set_ios = tifm_sd_ios,
880 .get_ro = tifm_sd_ro
881};
882
883static int tifm_sd_initialize_host(struct tifm_sd *host)
884{
885 int rc;
886 unsigned int host_status = 0;
887 struct tifm_dev *sock = host->dev;
888
889 writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
890 host->clk_div = 61;
891 host->clk_freq = 20000000;
892 writel(TIFM_MMCSD_RESET, sock->addr + SOCK_MMCSD_SYSTEM_CONTROL);
893 writel(host->clk_div | TIFM_MMCSD_POWER,
894 sock->addr + SOCK_MMCSD_CONFIG);
895
896 /* wait up to 0.51 sec for reset */
897 for (rc = 32; rc <= 256; rc <<= 1) {
898 if (1 & readl(sock->addr + SOCK_MMCSD_SYSTEM_STATUS)) {
899 rc = 0;
900 break;
901 }
902 msleep(rc);
903 }
904
905 if (rc) {
906 pr_err("%s : controller failed to reset\n",
907 dev_name(&sock->dev));
908 return -ENODEV;
909 }
910
911 writel(0, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
912 writel(host->clk_div | TIFM_MMCSD_POWER,
913 sock->addr + SOCK_MMCSD_CONFIG);
914 writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
915
916 // command timeout fixed to 64 clocks for now
917 writel(64, sock->addr + SOCK_MMCSD_COMMAND_TO);
918 writel(TIFM_MMCSD_INAB, sock->addr + SOCK_MMCSD_COMMAND);
919
920 for (rc = 16; rc <= 64; rc <<= 1) {
921 host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
922 writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
923 if (!(host_status & TIFM_MMCSD_ERRMASK)
924 && (host_status & TIFM_MMCSD_EOC)) {
925 rc = 0;
926 break;
927 }
928 msleep(rc);
929 }
930
931 if (rc) {
932 pr_err("%s : card not ready - probe failed on initialization\n",
933 dev_name(&sock->dev));
934 return -ENODEV;
935 }
936
937 writel(TIFM_MMCSD_CERR | TIFM_MMCSD_BRS | TIFM_MMCSD_EOC
938 | TIFM_MMCSD_ERRMASK,
939 sock->addr + SOCK_MMCSD_INT_ENABLE);
940
941 return 0;
942}
943
944static int tifm_sd_probe(struct tifm_dev *sock)
945{
946 struct mmc_host *mmc;
947 struct tifm_sd *host;
948 int rc = -EIO;
949
950 if (!(TIFM_SOCK_STATE_OCCUPIED
951 & readl(sock->addr + SOCK_PRESENT_STATE))) {
952 pr_warn("%s : card gone, unexpectedly\n",
953 dev_name(&sock->dev));
954 return rc;
955 }
956
957 mmc = mmc_alloc_host(sizeof(struct tifm_sd), &sock->dev);
958 if (!mmc)
959 return -ENOMEM;
960
961 host = mmc_priv(mmc);
962 tifm_set_drvdata(sock, mmc);
963 host->dev = sock;
964 host->timeout_jiffies = msecs_to_jiffies(TIFM_MMCSD_REQ_TIMEOUT_MS);
965 /*
966 * We use a fixed request timeout of 1s, hence inform the core about it.
967 * A future improvement should instead respect the cmd->busy_timeout.
968 */
969 mmc->max_busy_timeout = TIFM_MMCSD_REQ_TIMEOUT_MS;
970
971 tasklet_setup(&host->finish_tasklet, tifm_sd_end_cmd);
972 timer_setup(&host->timer, tifm_sd_abort, 0);
973
974 mmc->ops = &tifm_sd_ops;
975 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
976 mmc->caps = MMC_CAP_4_BIT_DATA;
977 mmc->f_min = 20000000 / 60;
978 mmc->f_max = 24000000;
979
980 mmc->max_blk_count = 2048;
981 mmc->max_segs = mmc->max_blk_count;
982 mmc->max_blk_size = min(TIFM_MMCSD_MAX_BLOCK_SIZE, PAGE_SIZE);
983 mmc->max_seg_size = mmc->max_blk_count * mmc->max_blk_size;
984 mmc->max_req_size = mmc->max_seg_size;
985
986 sock->card_event = tifm_sd_card_event;
987 sock->data_event = tifm_sd_data_event;
988 rc = tifm_sd_initialize_host(host);
989
990 if (!rc)
991 rc = mmc_add_host(mmc);
992 if (!rc)
993 return 0;
994
995 mmc_free_host(mmc);
996 return rc;
997}
998
999static void tifm_sd_remove(struct tifm_dev *sock)
1000{
1001 struct mmc_host *mmc = tifm_get_drvdata(sock);
1002 struct tifm_sd *host = mmc_priv(mmc);
1003 unsigned long flags;
1004
1005 spin_lock_irqsave(&sock->lock, flags);
1006 host->eject = 1;
1007 writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
1008 spin_unlock_irqrestore(&sock->lock, flags);
1009
1010 tasklet_kill(&host->finish_tasklet);
1011
1012 spin_lock_irqsave(&sock->lock, flags);
1013 if (host->req) {
1014 writel(TIFM_FIFO_INT_SETALL,
1015 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
1016 writel(0, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
1017 host->req->cmd->error = -ENOMEDIUM;
1018 if (host->req->stop)
1019 host->req->stop->error = -ENOMEDIUM;
1020 tasklet_schedule(&host->finish_tasklet);
1021 }
1022 spin_unlock_irqrestore(&sock->lock, flags);
1023 mmc_remove_host(mmc);
1024 dev_dbg(&sock->dev, "after remove\n");
1025
1026 mmc_free_host(mmc);
1027}
1028
1029#ifdef CONFIG_PM
1030
1031static int tifm_sd_suspend(struct tifm_dev *sock, pm_message_t state)
1032{
1033 return 0;
1034}
1035
1036static int tifm_sd_resume(struct tifm_dev *sock)
1037{
1038 struct mmc_host *mmc = tifm_get_drvdata(sock);
1039 struct tifm_sd *host = mmc_priv(mmc);
1040 int rc;
1041
1042 rc = tifm_sd_initialize_host(host);
1043 dev_dbg(&sock->dev, "resume initialize %d\n", rc);
1044
1045 if (rc)
1046 host->eject = 1;
1047
1048 return rc;
1049}
1050
1051#else
1052
1053#define tifm_sd_suspend NULL
1054#define tifm_sd_resume NULL
1055
1056#endif /* CONFIG_PM */
1057
1058static struct tifm_device_id tifm_sd_id_tbl[] = {
1059 { TIFM_TYPE_SD }, { }
1060};
1061
1062static struct tifm_driver tifm_sd_driver = {
1063 .driver = {
1064 .name = DRIVER_NAME,
1065 .owner = THIS_MODULE
1066 },
1067 .id_table = tifm_sd_id_tbl,
1068 .probe = tifm_sd_probe,
1069 .remove = tifm_sd_remove,
1070 .suspend = tifm_sd_suspend,
1071 .resume = tifm_sd_resume
1072};
1073
1074static int __init tifm_sd_init(void)
1075{
1076 return tifm_register_driver(&tifm_sd_driver);
1077}
1078
1079static void __exit tifm_sd_exit(void)
1080{
1081 tifm_unregister_driver(&tifm_sd_driver);
1082}
1083
1084MODULE_AUTHOR("Alex Dubov");
1085MODULE_DESCRIPTION("TI FlashMedia SD driver");
1086MODULE_LICENSE("GPL");
1087MODULE_DEVICE_TABLE(tifm, tifm_sd_id_tbl);
1088MODULE_VERSION(DRIVER_VERSION);
1089
1090module_init(tifm_sd_init);
1091module_exit(tifm_sd_exit);