1// SPDX-License-Identifier: GPL-2.0
 2//
 3// Copyright (c) 2018 MediaTek Inc.
 4// Author: Weiyi Lu <weiyi.lu@mediatek.com>
 5
 6#include <linux/clk-provider.h>
 7#include <linux/platform_device.h>
 8
 9#include "clk-mtk.h"
10#include "clk-gate.h"
11
12#include <dt-bindings/clock/mt8183-clk.h>
13
14static const struct mtk_gate_regs ipu_core0_cg_regs = {
15	.set_ofs = 0x4,
16	.clr_ofs = 0x8,
17	.sta_ofs = 0x0,
18};
19
20#define GATE_IPU_CORE0(_id, _name, _parent, _shift)			\
21	GATE_MTK(_id, _name, _parent, &ipu_core0_cg_regs, _shift,	\
22		&mtk_clk_gate_ops_setclr)
23
24static const struct mtk_gate ipu_core0_clks[] = {
25	GATE_IPU_CORE0(CLK_IPU_CORE0_JTAG, "ipu_core0_jtag", "dsp_sel", 0),
26	GATE_IPU_CORE0(CLK_IPU_CORE0_AXI, "ipu_core0_axi", "dsp_sel", 1),
27	GATE_IPU_CORE0(CLK_IPU_CORE0_IPU, "ipu_core0_ipu", "dsp_sel", 2),
28};
29
30static int clk_mt8183_ipu_core0_probe(struct platform_device *pdev)
31{
32	struct clk_onecell_data *clk_data;
33	struct device_node *node = pdev->dev.of_node;
34
35	clk_data = mtk_alloc_clk_data(CLK_IPU_CORE0_NR_CLK);
36
37	mtk_clk_register_gates(node, ipu_core0_clks, ARRAY_SIZE(ipu_core0_clks),
38			clk_data);
39
40	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
41}
42
43static const struct of_device_id of_match_clk_mt8183_ipu_core0[] = {
44	{ .compatible = "mediatek,mt8183-ipu_core0", },
45	{}
46};
47
48static struct platform_driver clk_mt8183_ipu_core0_drv = {
49	.probe = clk_mt8183_ipu_core0_probe,
50	.driver = {
51		.name = "clk-mt8183-ipu_core0",
52		.of_match_table = of_match_clk_mt8183_ipu_core0,
53	},
54};
55
56builtin_platform_driver(clk_mt8183_ipu_core0_drv);