1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (c) 2018 MediaTek Inc.
  4 * Author: Ryder Lee <ryder.lee@mediatek.com>
  5 */
  6
  7#include <linux/clk-provider.h>
  8#include <linux/of.h>
  9#include <linux/of_address.h>
 10#include <linux/of_device.h>
 11#include <linux/platform_device.h>
 12
 13#include "clk-mtk.h"
 14#include "clk-gate.h"
 15
 16#include <dt-bindings/clock/mt2701-clk.h>
 17
 18#define GATE_AUDIO0(_id, _name, _parent, _shift) {	\
 19		.id = _id,				\
 20		.name = _name,				\
 21		.parent_name = _parent,			\
 22		.regs = &audio0_cg_regs,			\
 23		.shift = _shift,			\
 24		.ops = &mtk_clk_gate_ops_no_setclr,	\
 25	}
 26
 27#define GATE_AUDIO1(_id, _name, _parent, _shift) {	\
 28		.id = _id,				\
 29		.name = _name,				\
 30		.parent_name = _parent,			\
 31		.regs = &audio1_cg_regs,			\
 32		.shift = _shift,			\
 33		.ops = &mtk_clk_gate_ops_no_setclr,	\
 34	}
 35
 36#define GATE_AUDIO2(_id, _name, _parent, _shift) {	\
 37		.id = _id,				\
 38		.name = _name,				\
 39		.parent_name = _parent,			\
 40		.regs = &audio2_cg_regs,			\
 41		.shift = _shift,			\
 42		.ops = &mtk_clk_gate_ops_no_setclr,	\
 43	}
 44
 45#define GATE_AUDIO3(_id, _name, _parent, _shift) {	\
 46		.id = _id,				\
 47		.name = _name,				\
 48		.parent_name = _parent,			\
 49		.regs = &audio3_cg_regs,			\
 50		.shift = _shift,			\
 51		.ops = &mtk_clk_gate_ops_no_setclr,	\
 52	}
 53
 54static const struct mtk_gate_regs audio0_cg_regs = {
 55	.set_ofs = 0x0,
 56	.clr_ofs = 0x0,
 57	.sta_ofs = 0x0,
 58};
 59
 60static const struct mtk_gate_regs audio1_cg_regs = {
 61	.set_ofs = 0x10,
 62	.clr_ofs = 0x10,
 63	.sta_ofs = 0x10,
 64};
 65
 66static const struct mtk_gate_regs audio2_cg_regs = {
 67	.set_ofs = 0x14,
 68	.clr_ofs = 0x14,
 69	.sta_ofs = 0x14,
 70};
 71
 72static const struct mtk_gate_regs audio3_cg_regs = {
 73	.set_ofs = 0x634,
 74	.clr_ofs = 0x634,
 75	.sta_ofs = 0x634,
 76};
 77
 78static const struct mtk_gate audio_clks[] = {
 79	/* AUDIO0 */
 80	GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2),
 81	GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20),
 82	GATE_AUDIO0(CLK_AUD_SPDF, "audio_spdf", "audpll_sel", 21),
 83	GATE_AUDIO0(CLK_AUD_SPDF2, "audio_spdf2", "audpll_sel", 22),
 84	GATE_AUDIO0(CLK_AUD_APLL, "audio_apll", "audpll_sel", 23),
 85	/* AUDIO1 */
 86	GATE_AUDIO1(CLK_AUD_I2SIN1, "audio_i2sin1", "aud_mux1_sel", 0),
 87	GATE_AUDIO1(CLK_AUD_I2SIN2, "audio_i2sin2", "aud_mux1_sel", 1),
 88	GATE_AUDIO1(CLK_AUD_I2SIN3, "audio_i2sin3", "aud_mux1_sel", 2),
 89	GATE_AUDIO1(CLK_AUD_I2SIN4, "audio_i2sin4", "aud_mux1_sel", 3),
 90	GATE_AUDIO1(CLK_AUD_I2SIN5, "audio_i2sin5", "aud_mux1_sel", 4),
 91	GATE_AUDIO1(CLK_AUD_I2SIN6, "audio_i2sin6", "aud_mux1_sel", 5),
 92	GATE_AUDIO1(CLK_AUD_I2SO1, "audio_i2so1", "aud_mux1_sel", 6),
 93	GATE_AUDIO1(CLK_AUD_I2SO2, "audio_i2so2", "aud_mux1_sel", 7),
 94	GATE_AUDIO1(CLK_AUD_I2SO3, "audio_i2so3", "aud_mux1_sel", 8),
 95	GATE_AUDIO1(CLK_AUD_I2SO4, "audio_i2so4", "aud_mux1_sel", 9),
 96	GATE_AUDIO1(CLK_AUD_I2SO5, "audio_i2so5", "aud_mux1_sel", 10),
 97	GATE_AUDIO1(CLK_AUD_I2SO6, "audio_i2so6", "aud_mux1_sel", 11),
 98	GATE_AUDIO1(CLK_AUD_ASRCI1, "audio_asrci1", "asm_h_sel", 12),
 99	GATE_AUDIO1(CLK_AUD_ASRCI2, "audio_asrci2", "asm_h_sel", 13),
100	GATE_AUDIO1(CLK_AUD_ASRCO1, "audio_asrco1", "asm_h_sel", 14),
101	GATE_AUDIO1(CLK_AUD_ASRCO2, "audio_asrco2", "asm_h_sel", 15),
102	GATE_AUDIO1(CLK_AUD_INTDIR, "audio_intdir", "intdir_sel", 20),
103	GATE_AUDIO1(CLK_AUD_A1SYS, "audio_a1sys", "aud_mux1_sel", 21),
104	GATE_AUDIO1(CLK_AUD_A2SYS, "audio_a2sys", "aud_mux2_sel", 22),
105	GATE_AUDIO1(CLK_AUD_AFE_CONN, "audio_afe_conn", "aud_mux1_sel", 23),
106	GATE_AUDIO1(CLK_AUD_AFE_MRGIF, "audio_afe_mrgif", "aud_mux1_sel", 25),
107	/* AUDIO2 */
108	GATE_AUDIO2(CLK_AUD_MMIF_UL1, "audio_ul1", "aud_mux1_sel", 0),
109	GATE_AUDIO2(CLK_AUD_MMIF_UL2, "audio_ul2", "aud_mux1_sel", 1),
110	GATE_AUDIO2(CLK_AUD_MMIF_UL3, "audio_ul3", "aud_mux1_sel", 2),
111	GATE_AUDIO2(CLK_AUD_MMIF_UL4, "audio_ul4", "aud_mux1_sel", 3),
112	GATE_AUDIO2(CLK_AUD_MMIF_UL5, "audio_ul5", "aud_mux1_sel", 4),
113	GATE_AUDIO2(CLK_AUD_MMIF_UL6, "audio_ul6", "aud_mux1_sel", 5),
114	GATE_AUDIO2(CLK_AUD_MMIF_DL1, "audio_dl1", "aud_mux1_sel", 6),
115	GATE_AUDIO2(CLK_AUD_MMIF_DL2, "audio_dl2", "aud_mux1_sel", 7),
116	GATE_AUDIO2(CLK_AUD_MMIF_DL3, "audio_dl3", "aud_mux1_sel", 8),
117	GATE_AUDIO2(CLK_AUD_MMIF_DL4, "audio_dl4", "aud_mux1_sel", 9),
118	GATE_AUDIO2(CLK_AUD_MMIF_DL5, "audio_dl5", "aud_mux1_sel", 10),
119	GATE_AUDIO2(CLK_AUD_MMIF_DL6, "audio_dl6", "aud_mux1_sel", 11),
120	GATE_AUDIO2(CLK_AUD_MMIF_DLMCH, "audio_dlmch", "aud_mux1_sel", 12),
121	GATE_AUDIO2(CLK_AUD_MMIF_ARB1, "audio_arb1", "aud_mux1_sel", 13),
122	GATE_AUDIO2(CLK_AUD_MMIF_AWB1, "audio_awb", "aud_mux1_sel", 14),
123	GATE_AUDIO2(CLK_AUD_MMIF_AWB2, "audio_awb2", "aud_mux1_sel", 15),
124	GATE_AUDIO2(CLK_AUD_MMIF_DAI, "audio_dai", "aud_mux1_sel", 16),
125	/* AUDIO3 */
126	GATE_AUDIO3(CLK_AUD_ASRCI3, "audio_asrci3", "asm_h_sel", 2),
127	GATE_AUDIO3(CLK_AUD_ASRCI4, "audio_asrci4", "asm_h_sel", 3),
128	GATE_AUDIO3(CLK_AUD_ASRCI5, "audio_asrci5", "asm_h_sel", 4),
129	GATE_AUDIO3(CLK_AUD_ASRCI6, "audio_asrci6", "asm_h_sel", 5),
130	GATE_AUDIO3(CLK_AUD_ASRCO3, "audio_asrco3", "asm_h_sel", 6),
131	GATE_AUDIO3(CLK_AUD_ASRCO4, "audio_asrco4", "asm_h_sel", 7),
132	GATE_AUDIO3(CLK_AUD_ASRCO5, "audio_asrco5", "asm_h_sel", 8),
133	GATE_AUDIO3(CLK_AUD_ASRCO6, "audio_asrco6", "asm_h_sel", 9),
134	GATE_AUDIO3(CLK_AUD_MEM_ASRC1, "audio_mem_asrc1", "asm_h_sel", 10),
135	GATE_AUDIO3(CLK_AUD_MEM_ASRC2, "audio_mem_asrc2", "asm_h_sel", 11),
136	GATE_AUDIO3(CLK_AUD_MEM_ASRC3, "audio_mem_asrc3", "asm_h_sel", 12),
137	GATE_AUDIO3(CLK_AUD_MEM_ASRC4, "audio_mem_asrc4", "asm_h_sel", 13),
138	GATE_AUDIO3(CLK_AUD_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
139};
140
141static const struct of_device_id of_match_clk_mt2701_aud[] = {
142	{ .compatible = "mediatek,mt2701-audsys", },
143	{}
144};
145
146static int clk_mt2701_aud_probe(struct platform_device *pdev)
147{
148	struct clk_onecell_data *clk_data;
149	struct device_node *node = pdev->dev.of_node;
150	int r;
151
152	clk_data = mtk_alloc_clk_data(CLK_AUD_NR);
153
154	mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
155			       clk_data);
156
157	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
158	if (r) {
159		dev_err(&pdev->dev,
160			"could not register clock provider: %s: %d\n",
161			pdev->name, r);
162
163		goto err_clk_provider;
164	}
165
166	r = devm_of_platform_populate(&pdev->dev);
167	if (r)
168		goto err_plat_populate;
169
170	return 0;
171
172err_plat_populate:
173	of_clk_del_provider(node);
174err_clk_provider:
175	return r;
176}
177
178static struct platform_driver clk_mt2701_aud_drv = {
179	.probe = clk_mt2701_aud_probe,
180	.driver = {
181		.name = "clk-mt2701-aud",
182		.of_match_table = of_match_clk_mt2701_aud,
183	},
184};
185
186builtin_platform_driver(clk_mt2701_aud_drv);