1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (C) 2010 Broadcom
  4 * Copyright (C) 2012 Stephen Warren
  5 * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
  6 */
  7
  8#include <linux/clk-provider.h>
  9#include <linux/kernel.h>
 10#include <linux/init.h>
 11#include <linux/of.h>
 12#include <linux/of_device.h>
 13#include <linux/platform_device.h>
 14#include <linux/stringify.h>
 15#include <linux/regmap.h>
 16#include <linux/mfd/syscon.h>
 17
 18#include <dt-bindings/clock/oxsemi,ox810se.h>
 19#include <dt-bindings/clock/oxsemi,ox820.h>
 20
 21/* Standard regmap gate clocks */
 22struct clk_oxnas_gate {
 23	struct clk_hw hw;
 24	unsigned int bit;
 25	struct regmap *regmap;
 26};
 27
 28struct oxnas_stdclk_data {
 29	struct clk_hw_onecell_data *onecell_data;
 30	struct clk_oxnas_gate **gates;
 31	unsigned int ngates;
 32	struct clk_oxnas_pll **plls;
 33	unsigned int nplls;
 34};
 35
 36/* Regmap offsets */
 37#define CLK_STAT_REGOFFSET	0x24
 38#define CLK_SET_REGOFFSET	0x2c
 39#define CLK_CLR_REGOFFSET	0x30
 40
 41static inline struct clk_oxnas_gate *to_clk_oxnas_gate(struct clk_hw *hw)
 42{
 43	return container_of(hw, struct clk_oxnas_gate, hw);
 44}
 45
 46static int oxnas_clk_gate_is_enabled(struct clk_hw *hw)
 47{
 48	struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw);
 49	int ret;
 50	unsigned int val;
 51
 52	ret = regmap_read(std->regmap, CLK_STAT_REGOFFSET, &val);
 53	if (ret < 0)
 54		return ret;
 55
 56	return val & BIT(std->bit);
 57}
 58
 59static int oxnas_clk_gate_enable(struct clk_hw *hw)
 60{
 61	struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw);
 62
 63	regmap_write(std->regmap, CLK_SET_REGOFFSET, BIT(std->bit));
 64
 65	return 0;
 66}
 67
 68static void oxnas_clk_gate_disable(struct clk_hw *hw)
 69{
 70	struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw);
 71
 72	regmap_write(std->regmap, CLK_CLR_REGOFFSET, BIT(std->bit));
 73}
 74
 75static const struct clk_ops oxnas_clk_gate_ops = {
 76	.enable = oxnas_clk_gate_enable,
 77	.disable = oxnas_clk_gate_disable,
 78	.is_enabled = oxnas_clk_gate_is_enabled,
 79};
 80
 81static const char *const osc_parents[] = {
 82	"oscillator",
 83};
 84
 85static const char *const eth_parents[] = {
 86	"gmacclk",
 87};
 88
 89#define OXNAS_GATE(_name, _bit, _parents)				\
 90struct clk_oxnas_gate _name = {						\
 91	.bit = (_bit),							\
 92	.hw.init = &(struct clk_init_data) {				\
 93		.name = #_name,						\
 94		.ops = &oxnas_clk_gate_ops,				\
 95		.parent_names = _parents,				\
 96		.num_parents = ARRAY_SIZE(_parents),			\
 97		.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),	\
 98	},								\
 99}
100
101static OXNAS_GATE(ox810se_leon, 0, osc_parents);
102static OXNAS_GATE(ox810se_dma_sgdma, 1, osc_parents);
103static OXNAS_GATE(ox810se_cipher, 2, osc_parents);
104static OXNAS_GATE(ox810se_sata, 4, osc_parents);
105static OXNAS_GATE(ox810se_audio, 5, osc_parents);
106static OXNAS_GATE(ox810se_usbmph, 6, osc_parents);
107static OXNAS_GATE(ox810se_etha, 7, eth_parents);
108static OXNAS_GATE(ox810se_pciea, 8, osc_parents);
109static OXNAS_GATE(ox810se_nand, 9, osc_parents);
110
111static struct clk_oxnas_gate *ox810se_gates[] = {
112	&ox810se_leon,
113	&ox810se_dma_sgdma,
114	&ox810se_cipher,
115	&ox810se_sata,
116	&ox810se_audio,
117	&ox810se_usbmph,
118	&ox810se_etha,
119	&ox810se_pciea,
120	&ox810se_nand,
121};
122
123static OXNAS_GATE(ox820_leon, 0, osc_parents);
124static OXNAS_GATE(ox820_dma_sgdma, 1, osc_parents);
125static OXNAS_GATE(ox820_cipher, 2, osc_parents);
126static OXNAS_GATE(ox820_sd, 3, osc_parents);
127static OXNAS_GATE(ox820_sata, 4, osc_parents);
128static OXNAS_GATE(ox820_audio, 5, osc_parents);
129static OXNAS_GATE(ox820_usbmph, 6, osc_parents);
130static OXNAS_GATE(ox820_etha, 7, eth_parents);
131static OXNAS_GATE(ox820_pciea, 8, osc_parents);
132static OXNAS_GATE(ox820_nand, 9, osc_parents);
133static OXNAS_GATE(ox820_ethb, 10, eth_parents);
134static OXNAS_GATE(ox820_pcieb, 11, osc_parents);
135static OXNAS_GATE(ox820_ref600, 12, osc_parents);
136static OXNAS_GATE(ox820_usbdev, 13, osc_parents);
137
138static struct clk_oxnas_gate *ox820_gates[] = {
139	&ox820_leon,
140	&ox820_dma_sgdma,
141	&ox820_cipher,
142	&ox820_sd,
143	&ox820_sata,
144	&ox820_audio,
145	&ox820_usbmph,
146	&ox820_etha,
147	&ox820_pciea,
148	&ox820_nand,
149	&ox820_etha,
150	&ox820_pciea,
151	&ox820_ref600,
152	&ox820_usbdev,
153};
154
155static struct clk_hw_onecell_data ox810se_hw_onecell_data = {
156	.hws = {
157		[CLK_810_LEON]	= &ox810se_leon.hw,
158		[CLK_810_DMA_SGDMA]	= &ox810se_dma_sgdma.hw,
159		[CLK_810_CIPHER]	= &ox810se_cipher.hw,
160		[CLK_810_SATA]	= &ox810se_sata.hw,
161		[CLK_810_AUDIO]	= &ox810se_audio.hw,
162		[CLK_810_USBMPH]	= &ox810se_usbmph.hw,
163		[CLK_810_ETHA]	= &ox810se_etha.hw,
164		[CLK_810_PCIEA]	= &ox810se_pciea.hw,
165		[CLK_810_NAND]	= &ox810se_nand.hw,
166	},
167	.num = ARRAY_SIZE(ox810se_gates),
168};
169
170static struct clk_hw_onecell_data ox820_hw_onecell_data = {
171	.hws = {
172		[CLK_820_LEON]	= &ox820_leon.hw,
173		[CLK_820_DMA_SGDMA]	= &ox820_dma_sgdma.hw,
174		[CLK_820_CIPHER]	= &ox820_cipher.hw,
175		[CLK_820_SD]	= &ox820_sd.hw,
176		[CLK_820_SATA]	= &ox820_sata.hw,
177		[CLK_820_AUDIO]	= &ox820_audio.hw,
178		[CLK_820_USBMPH]	= &ox820_usbmph.hw,
179		[CLK_820_ETHA]	= &ox820_etha.hw,
180		[CLK_820_PCIEA]	= &ox820_pciea.hw,
181		[CLK_820_NAND]	= &ox820_nand.hw,
182		[CLK_820_ETHB]	= &ox820_ethb.hw,
183		[CLK_820_PCIEB]	= &ox820_pcieb.hw,
184		[CLK_820_REF600]	= &ox820_ref600.hw,
185		[CLK_820_USBDEV]	= &ox820_usbdev.hw,
186	},
187	.num = ARRAY_SIZE(ox820_gates),
188};
189
190static struct oxnas_stdclk_data ox810se_stdclk_data = {
191	.onecell_data = &ox810se_hw_onecell_data,
192	.gates = ox810se_gates,
193	.ngates = ARRAY_SIZE(ox810se_gates),
194};
195
196static struct oxnas_stdclk_data ox820_stdclk_data = {
197	.onecell_data = &ox820_hw_onecell_data,
198	.gates = ox820_gates,
199	.ngates = ARRAY_SIZE(ox820_gates),
200};
201
202static const struct of_device_id oxnas_stdclk_dt_ids[] = {
203	{ .compatible = "oxsemi,ox810se-stdclk", &ox810se_stdclk_data },
204	{ .compatible = "oxsemi,ox820-stdclk", &ox820_stdclk_data },
205	{ }
206};
207
208static int oxnas_stdclk_probe(struct platform_device *pdev)
209{
210	struct device_node *np = pdev->dev.of_node;
211	const struct oxnas_stdclk_data *data;
212	const struct of_device_id *id;
213	struct regmap *regmap;
214	int ret;
215	int i;
216
217	id = of_match_device(oxnas_stdclk_dt_ids, &pdev->dev);
218	if (!id)
219		return -ENODEV;
220	data = id->data;
221
222	regmap = syscon_node_to_regmap(of_get_parent(np));
223	if (IS_ERR(regmap)) {
224		dev_err(&pdev->dev, "failed to have parent regmap\n");
225		return PTR_ERR(regmap);
226	}
227
228	for (i = 0 ; i < data->ngates ; ++i)
229		data->gates[i]->regmap = regmap;
230
231	for (i = 0; i < data->onecell_data->num; i++) {
232		if (!data->onecell_data->hws[i])
233			continue;
234
235		ret = devm_clk_hw_register(&pdev->dev,
236					   data->onecell_data->hws[i]);
237		if (ret)
238			return ret;
239	}
240
241	return of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
242				      data->onecell_data);
243}
244
245static struct platform_driver oxnas_stdclk_driver = {
246	.probe = oxnas_stdclk_probe,
247	.driver	= {
248		.name = "oxnas-stdclk",
249		.suppress_bind_attrs = true,
250		.of_match_table = oxnas_stdclk_dt_ids,
251	},
252};
253builtin_platform_driver(oxnas_stdclk_driver);