1/*
  2 * arch/arch/mach-tegra/timer.c
  3 *
  4 * Copyright (C) 2010 Google, Inc.
  5 *
  6 * Author:
  7 *	Colin Cross <ccross@google.com>
  8 *
  9 * This software is licensed under the terms of the GNU General Public
 10 * License version 2, as published by the Free Software Foundation, and
 11 * may be copied, distributed, and modified under those terms.
 12 *
 13 * This program is distributed in the hope that it will be useful,
 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16 * GNU General Public License for more details.
 17 *
 18 */
 19
 20#include <linux/init.h>
 21#include <linux/err.h>
 22#include <linux/time.h>
 23#include <linux/interrupt.h>
 24#include <linux/irq.h>
 25#include <linux/clockchips.h>
 26#include <linux/clocksource.h>
 27#include <linux/clk.h>
 28#include <linux/io.h>
 29
 30#include <asm/mach/time.h>
 31#include <asm/smp_twd.h>
 32#include <asm/sched_clock.h>
 33
 34#include <mach/iomap.h>
 35#include <mach/irqs.h>
 36#include <mach/suspend.h>
 37
 38#include "board.h"
 39#include "clock.h"
 40
 41#define RTC_SECONDS            0x08
 42#define RTC_SHADOW_SECONDS     0x0c
 43#define RTC_MILLISECONDS       0x10
 44
 45#define TIMERUS_CNTR_1US 0x10
 46#define TIMERUS_USEC_CFG 0x14
 47#define TIMERUS_CNTR_FREEZE 0x4c
 48
 49#define TIMER1_BASE 0x0
 50#define TIMER2_BASE 0x8
 51#define TIMER3_BASE 0x50
 52#define TIMER4_BASE 0x58
 53
 54#define TIMER_PTV 0x0
 55#define TIMER_PCR 0x4
 56
 57static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE);
 58static void __iomem *rtc_base = IO_ADDRESS(TEGRA_RTC_BASE);
 59
 60static struct timespec persistent_ts;
 61static u64 persistent_ms, last_persistent_ms;
 62
 63#define timer_writel(value, reg) \
 64	__raw_writel(value, timer_reg_base + (reg))
 65#define timer_readl(reg) \
 66	__raw_readl(timer_reg_base + (reg))
 67
 68static int tegra_timer_set_next_event(unsigned long cycles,
 69					 struct clock_event_device *evt)
 70{
 71	u32 reg;
 72
 73	reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
 74	timer_writel(reg, TIMER3_BASE + TIMER_PTV);
 75
 76	return 0;
 77}
 78
 79static void tegra_timer_set_mode(enum clock_event_mode mode,
 80				    struct clock_event_device *evt)
 81{
 82	u32 reg;
 83
 84	timer_writel(0, TIMER3_BASE + TIMER_PTV);
 85
 86	switch (mode) {
 87	case CLOCK_EVT_MODE_PERIODIC:
 88		reg = 0xC0000000 | ((1000000/HZ)-1);
 89		timer_writel(reg, TIMER3_BASE + TIMER_PTV);
 90		break;
 91	case CLOCK_EVT_MODE_ONESHOT:
 92		break;
 93	case CLOCK_EVT_MODE_UNUSED:
 94	case CLOCK_EVT_MODE_SHUTDOWN:
 95	case CLOCK_EVT_MODE_RESUME:
 96		break;
 97	}
 98}
 99
100static struct clock_event_device tegra_clockevent = {
101	.name		= "timer0",
102	.rating		= 300,
103	.features	= CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
104	.set_next_event	= tegra_timer_set_next_event,
105	.set_mode	= tegra_timer_set_mode,
106};
107
108static u32 notrace tegra_read_sched_clock(void)
109{
110	return timer_readl(TIMERUS_CNTR_1US);
111}
112
113/*
114 * tegra_rtc_read - Reads the Tegra RTC registers
115 * Care must be taken that this funciton is not called while the
116 * tegra_rtc driver could be executing to avoid race conditions
117 * on the RTC shadow register
118 */
119static u64 tegra_rtc_read_ms(void)
120{
121	u32 ms = readl(rtc_base + RTC_MILLISECONDS);
122	u32 s = readl(rtc_base + RTC_SHADOW_SECONDS);
123	return (u64)s * MSEC_PER_SEC + ms;
124}
125
126/*
127 * tegra_read_persistent_clock -  Return time from a persistent clock.
128 *
129 * Reads the time from a source which isn't disabled during PM, the
130 * 32k sync timer.  Convert the cycles elapsed since last read into
131 * nsecs and adds to a monotonically increasing timespec.
132 * Care must be taken that this funciton is not called while the
133 * tegra_rtc driver could be executing to avoid race conditions
134 * on the RTC shadow register
135 */
136static void tegra_read_persistent_clock(struct timespec *ts)
137{
138	u64 delta;
139	struct timespec *tsp = &persistent_ts;
140
141	last_persistent_ms = persistent_ms;
142	persistent_ms = tegra_rtc_read_ms();
143	delta = persistent_ms - last_persistent_ms;
144
145	timespec_add_ns(tsp, delta * NSEC_PER_MSEC);
146	*ts = *tsp;
147}
148
149static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
150{
151	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
152	timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
153	evt->event_handler(evt);
154	return IRQ_HANDLED;
155}
156
157static struct irqaction tegra_timer_irq = {
158	.name		= "timer0",
159	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH,
160	.handler	= tegra_timer_interrupt,
161	.dev_id		= &tegra_clockevent,
162	.irq		= INT_TMR3,
163};
164
165#ifdef CONFIG_HAVE_ARM_TWD
166static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
167			      TEGRA_ARM_PERIF_BASE + 0x600,
168			      IRQ_LOCALTIMER);
169
170static void __init tegra_twd_init(void)
171{
172	int err = twd_local_timer_register(&twd_local_timer);
173	if (err)
174		pr_err("twd_local_timer_register failed %d\n", err);
175}
176#else
177#define tegra_twd_init()	do {} while(0)
178#endif
179
180static void __init tegra_init_timer(void)
181{
182	struct clk *clk;
183	unsigned long rate;
184	int ret;
185
186	clk = clk_get_sys("timer", NULL);
187	if (IS_ERR(clk)) {
188		pr_warn("Unable to get timer clock."
189			" Assuming 12Mhz input clock.\n");
190		rate = 12000000;
191	} else {
192		clk_enable(clk);
193		rate = clk_get_rate(clk);
194	}
195
196	/*
197	 * rtc registers are used by read_persistent_clock, keep the rtc clock
198	 * enabled
199	 */
200	clk = clk_get_sys("rtc-tegra", NULL);
201	if (IS_ERR(clk))
202		pr_warn("Unable to get rtc-tegra clock\n");
203	else
204		clk_enable(clk);
205
206	switch (rate) {
207	case 12000000:
208		timer_writel(0x000b, TIMERUS_USEC_CFG);
209		break;
210	case 13000000:
211		timer_writel(0x000c, TIMERUS_USEC_CFG);
212		break;
213	case 19200000:
214		timer_writel(0x045f, TIMERUS_USEC_CFG);
215		break;
216	case 26000000:
217		timer_writel(0x0019, TIMERUS_USEC_CFG);
218		break;
219	default:
220		WARN(1, "Unknown clock rate");
221	}
222
223	setup_sched_clock(tegra_read_sched_clock, 32, 1000000);
224
225	if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
226		"timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) {
227		printk(KERN_ERR "Failed to register clocksource\n");
228		BUG();
229	}
230
231	ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
232	if (ret) {
233		printk(KERN_ERR "Failed to register timer IRQ: %d\n", ret);
234		BUG();
235	}
236
237	clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5);
238	tegra_clockevent.max_delta_ns =
239		clockevent_delta2ns(0x1fffffff, &tegra_clockevent);
240	tegra_clockevent.min_delta_ns =
241		clockevent_delta2ns(0x1, &tegra_clockevent);
242	tegra_clockevent.cpumask = cpu_all_mask;
243	tegra_clockevent.irq = tegra_timer_irq.irq;
244	clockevents_register_device(&tegra_clockevent);
245	tegra_twd_init();
246	register_persistent_clock(NULL, tegra_read_persistent_clock);
247}
248
249struct sys_timer tegra_timer = {
250	.init = tegra_init_timer,
251};
252
253#ifdef CONFIG_PM
254static u32 usec_config;
255
256void tegra_timer_suspend(void)
257{
258	usec_config = timer_readl(TIMERUS_USEC_CFG);
259}
260
261void tegra_timer_resume(void)
262{
263	timer_writel(usec_config, TIMERUS_USEC_CFG);
264}
265#endif