1/*
  2 * OMAP2plus display device setup / initialization.
  3 *
  4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
  5 *	Senthilvadivu Guruswamy
  6 *	Sumit Semwal
  7 *
  8 * This program is free software; you can redistribute it and/or modify
  9 * it under the terms of the GNU General Public License version 2 as
 10 * published by the Free Software Foundation.
 11 *
 12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 13 * kind, whether express or implied; without even the implied warranty
 14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 15 * GNU General Public License for more details.
 16 */
 17
 18#include <linux/string.h>
 19#include <linux/kernel.h>
 20#include <linux/init.h>
 21#include <linux/platform_device.h>
 22#include <linux/io.h>
 23#include <linux/clk.h>
 24#include <linux/err.h>
 25#include <linux/delay.h>
 26
 27#include <video/omapdss.h>
 28#include <plat/omap_hwmod.h>
 29#include <plat/omap_device.h>
 30#include <plat/omap-pm.h>
 
 
 
 
 31#include "common.h"
 32
 
 33#include "iomap.h"
 34#include "mux.h"
 35#include "control.h"
 36#include "display.h"
 
 37
 38#define DISPC_CONTROL		0x0040
 39#define DISPC_CONTROL2		0x0238
 
 40#define DISPC_IRQSTATUS		0x0018
 41
 42#define DSS_SYSCONFIG		0x10
 43#define DSS_SYSSTATUS		0x14
 44#define DSS_CONTROL		0x40
 45#define DSS_SDI_CONTROL		0x44
 46#define DSS_PLL_CONTROL		0x48
 47
 48#define LCD_EN_MASK		(0x1 << 0)
 49#define DIGIT_EN_MASK		(0x1 << 1)
 50
 51#define FRAMEDONE_IRQ_SHIFT	0
 52#define EVSYNC_EVEN_IRQ_SHIFT	2
 53#define EVSYNC_ODD_IRQ_SHIFT	3
 54#define FRAMEDONE2_IRQ_SHIFT	22
 
 55#define FRAMEDONETV_IRQ_SHIFT	24
 56
 57/*
 58 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
 59 *     reset before deciding that something has gone wrong
 60 */
 61#define FRAMEDONE_IRQ_TIMEOUT		100
 62
 
 63static struct platform_device omap_display_device = {
 64	.name          = "omapdss",
 65	.id            = -1,
 66	.dev            = {
 67		.platform_data = NULL,
 68	},
 69};
 70
 71struct omap_dss_hwmod_data {
 72	const char *oh_name;
 73	const char *dev_name;
 74	const int id;
 75};
 76
 77static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initdata = {
 78	{ "dss_core", "omapdss_dss", -1 },
 79	{ "dss_dispc", "omapdss_dispc", -1 },
 80	{ "dss_rfbi", "omapdss_rfbi", -1 },
 81	{ "dss_venc", "omapdss_venc", -1 },
 82};
 83
 84static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
 85	{ "dss_core", "omapdss_dss", -1 },
 86	{ "dss_dispc", "omapdss_dispc", -1 },
 87	{ "dss_rfbi", "omapdss_rfbi", -1 },
 88	{ "dss_venc", "omapdss_venc", -1 },
 89	{ "dss_dsi1", "omapdss_dsi", 0 },
 90};
 91
 92static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
 93	{ "dss_core", "omapdss_dss", -1 },
 94	{ "dss_dispc", "omapdss_dispc", -1 },
 95	{ "dss_rfbi", "omapdss_rfbi", -1 },
 96	{ "dss_venc", "omapdss_venc", -1 },
 97	{ "dss_dsi1", "omapdss_dsi", 0 },
 98	{ "dss_dsi2", "omapdss_dsi", 1 },
 99	{ "dss_hdmi", "omapdss_hdmi", -1 },
100};
101
102static void __init omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
103{
104	u32 reg;
105	u16 control_i2c_1;
106
107	omap_mux_init_signal("hdmi_cec",
108			OMAP_PIN_INPUT_PULLUP);
109	omap_mux_init_signal("hdmi_ddc_scl",
110			OMAP_PIN_INPUT_PULLUP);
111	omap_mux_init_signal("hdmi_ddc_sda",
112			OMAP_PIN_INPUT_PULLUP);
113
114	/*
115	 * CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and
116	 * HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable
117	 * internal pull up resistor.
118	 */
119	if (flags & OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP) {
120		control_i2c_1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1;
121		reg = omap4_ctrl_pad_readl(control_i2c_1);
122		reg |= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK |
123			OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK);
124			omap4_ctrl_pad_writel(reg, control_i2c_1);
125	}
126}
127
128static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
129{
130	u32 enable_mask, enable_shift;
131	u32 pipd_mask, pipd_shift;
132	u32 reg;
 
133
134	if (dsi_id == 0) {
135		enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
136		enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
137		pipd_mask = OMAP4_DSI1_PIPD_MASK;
138		pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
139	} else if (dsi_id == 1) {
140		enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
141		enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
142		pipd_mask = OMAP4_DSI2_PIPD_MASK;
143		pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
144	} else {
145		return -ENODEV;
146	}
147
148	reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
 
 
 
 
149
150	reg &= ~enable_mask;
151	reg &= ~pipd_mask;
152
153	reg |= (lanes << enable_shift) & enable_mask;
154	reg |= (lanes << pipd_shift) & pipd_mask;
155
156	omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
157
158	return 0;
159}
160
161int __init omap_hdmi_init(enum omap_hdmi_flags flags)
162{
163	if (cpu_is_omap44xx())
164		omap4_hdmi_mux_pads(flags);
165
166	return 0;
167}
168
169static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
170{
171	if (cpu_is_omap44xx())
172		return omap4_dsi_mux_pads(dsi_id, lane_mask);
173
174	return 0;
175}
176
177static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
178{
179	if (cpu_is_omap44xx())
180		omap4_dsi_mux_pads(dsi_id, 0);
181}
182
183static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
184{
185	return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
186}
187
188static struct platform_device *create_dss_pdev(const char *pdev_name,
189		int pdev_id, const char *oh_name, void *pdata, int pdata_len,
190		struct platform_device *parent)
191{
192	struct platform_device *pdev;
193	struct omap_device *od;
194	struct omap_hwmod *ohs[1];
195	struct omap_hwmod *oh;
 
196	int r;
197
198	oh = omap_hwmod_lookup(oh_name);
199	if (!oh) {
200		pr_err("Could not look up %s\n", oh_name);
201		r = -ENODEV;
202		goto err;
203	}
204
205	pdev = platform_device_alloc(pdev_name, pdev_id);
206	if (!pdev) {
207		pr_err("Could not create pdev for %s\n", pdev_name);
208		r = -ENOMEM;
209		goto err;
210	}
211
212	if (parent != NULL)
213		pdev->dev.parent = &parent->dev;
214
215	if (pdev->id != -1)
216		dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
217	else
218		dev_set_name(&pdev->dev, "%s", pdev->name);
 
219
220	ohs[0] = oh;
221	od = omap_device_alloc(pdev, ohs, 1, NULL, 0);
222	if (!od) {
223		pr_err("Could not alloc omap_device for %s\n", pdev_name);
224		r = -ENOMEM;
225		goto err;
226	}
227
228	r = platform_device_add_data(pdev, pdata, pdata_len);
229	if (r) {
230		pr_err("Could not set pdata for %s\n", pdev_name);
231		goto err;
 
232	}
233
234	r = omap_device_register(pdev);
235	if (r) {
236		pr_err("Could not register omap_device for %s\n", pdev_name);
237		goto err;
 
238	}
239
240	return pdev;
 
 
 
241
242err:
243	return ERR_PTR(r);
244}
245
246static struct platform_device *create_simple_dss_pdev(const char *pdev_name,
247		int pdev_id, void *pdata, int pdata_len,
248		struct platform_device *parent)
249{
250	struct platform_device *pdev;
251	int r;
252
253	pdev = platform_device_alloc(pdev_name, pdev_id);
254	if (!pdev) {
255		pr_err("Could not create pdev for %s\n", pdev_name);
256		r = -ENOMEM;
257		goto err;
258	}
259
260	if (parent != NULL)
261		pdev->dev.parent = &parent->dev;
262
263	if (pdev->id != -1)
264		dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
265	else
266		dev_set_name(&pdev->dev, "%s", pdev->name);
267
268	r = platform_device_add_data(pdev, pdata, pdata_len);
269	if (r) {
270		pr_err("Could not set pdata for %s\n", pdev_name);
271		goto err;
272	}
273
274	r = platform_device_add(pdev);
275	if (r) {
276		pr_err("Could not register platform_device for %s\n", pdev_name);
277		goto err;
 
278	}
279
280	return pdev;
281
282err:
283	return ERR_PTR(r);
284}
285
286int __init omap_display_init(struct omap_dss_board_info *board_data)
287{
288	int r = 0;
 
289	struct platform_device *pdev;
290	int i, oh_count;
291	const struct omap_dss_hwmod_data *curr_dss_hwmod;
292	struct platform_device *dss_pdev;
293
294	/* create omapdss device */
295
296	board_data->dsi_enable_pads = omap_dsi_enable_pads;
297	board_data->dsi_disable_pads = omap_dsi_disable_pads;
298	board_data->get_context_loss_count = omap_pm_get_dev_context_loss_count;
299	board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;
300
301	omap_display_device.dev.platform_data = board_data;
302
303	r = platform_device_register(&omap_display_device);
304	if (r < 0) {
305		pr_err("Unable to register omapdss device\n");
306		return r;
307	}
308
309	/* create devices for dss hwmods */
310
311	if (cpu_is_omap24xx()) {
312		curr_dss_hwmod = omap2_dss_hwmod_data;
313		oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
314	} else if (cpu_is_omap34xx()) {
315		curr_dss_hwmod = omap3_dss_hwmod_data;
316		oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
317	} else {
318		curr_dss_hwmod = omap4_dss_hwmod_data;
319		oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
320	}
321
322	/*
323	 * First create the pdev for dss_core, which is used as a parent device
324	 * by the other dss pdevs. Note: dss_core has to be the first item in
325	 * the hwmod list.
326	 */
327	dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name,
328			curr_dss_hwmod[0].id,
329			curr_dss_hwmod[0].oh_name,
330			board_data, sizeof(*board_data),
331			NULL);
332
333	if (IS_ERR(dss_pdev)) {
334		pr_err("Could not build omap_device for %s\n",
335				curr_dss_hwmod[0].oh_name);
336
337		return PTR_ERR(dss_pdev);
338	}
339
340	for (i = 1; i < oh_count; i++) {
341		pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name,
342				curr_dss_hwmod[i].id,
343				curr_dss_hwmod[i].oh_name,
344				board_data, sizeof(*board_data),
345				dss_pdev);
346
347		if (IS_ERR(pdev)) {
348			pr_err("Could not build omap_device for %s\n",
349					curr_dss_hwmod[i].oh_name);
350
351			return PTR_ERR(pdev);
352		}
353	}
354
355	/* Create devices for DPI and SDI */
356
357	pdev = create_simple_dss_pdev("omapdss_dpi", -1,
358			board_data, sizeof(*board_data), dss_pdev);
359	if (IS_ERR(pdev)) {
360		pr_err("Could not build platform_device for omapdss_dpi\n");
361		return PTR_ERR(pdev);
362	}
363
364	if (cpu_is_omap34xx()) {
365		pdev = create_simple_dss_pdev("omapdss_sdi", -1,
366				board_data, sizeof(*board_data), dss_pdev);
367		if (IS_ERR(pdev)) {
368			pr_err("Could not build platform_device for omapdss_sdi\n");
369			return PTR_ERR(pdev);
370		}
371	}
372
373	return 0;
374}
 
 
375
376static void dispc_disable_outputs(void)
377{
378	u32 v, irq_mask = 0;
379	bool lcd_en, digit_en, lcd2_en = false;
380	int i;
381	struct omap_dss_dispc_dev_attr *da;
382	struct omap_hwmod *oh;
383
384	oh = omap_hwmod_lookup("dss_dispc");
385	if (!oh) {
386		WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
387		return;
388	}
389
390	if (!oh->dev_attr) {
391		pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
392		return;
393	}
394
395	da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
396
397	/* store value of LCDENABLE and DIGITENABLE bits */
398	v = omap_hwmod_read(oh, DISPC_CONTROL);
399	lcd_en = v & LCD_EN_MASK;
400	digit_en = v & DIGIT_EN_MASK;
401
402	/* store value of LCDENABLE for LCD2 */
403	if (da->manager_count > 2) {
404		v = omap_hwmod_read(oh, DISPC_CONTROL2);
405		lcd2_en = v & LCD_EN_MASK;
406	}
407
408	if (!(lcd_en | digit_en | lcd2_en))
 
 
 
 
 
 
409		return; /* no managers currently enabled */
410
411	/*
412	 * If any manager was enabled, we need to disable it before
413	 * DSS clocks are disabled or DISPC module is reset
414	 */
415	if (lcd_en)
416		irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
417
418	if (digit_en) {
419		if (da->has_framedonetv_irq) {
420			irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
421		} else {
422			irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
423				1 << EVSYNC_ODD_IRQ_SHIFT;
424		}
425	}
426
427	if (lcd2_en)
428		irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
 
 
429
430	/*
431	 * clear any previous FRAMEDONE, FRAMEDONETV,
432	 * EVSYNC_EVEN/ODD or FRAMEDONE2 interrupts
433	 */
434	omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
435
436	/* disable LCD and TV managers */
437	v = omap_hwmod_read(oh, DISPC_CONTROL);
438	v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
439	omap_hwmod_write(v, oh, DISPC_CONTROL);
440
441	/* disable LCD2 manager */
442	if (da->manager_count > 2) {
443		v = omap_hwmod_read(oh, DISPC_CONTROL2);
444		v &= ~LCD_EN_MASK;
445		omap_hwmod_write(v, oh, DISPC_CONTROL2);
446	}
447
 
 
 
 
 
 
 
448	i = 0;
449	while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
450	       irq_mask) {
451		i++;
452		if (i > FRAMEDONE_IRQ_TIMEOUT) {
453			pr_err("didn't get FRAMEDONE1/2 or TV interrupt\n");
454			break;
455		}
456		mdelay(1);
457	}
458}
459
460#define MAX_MODULE_SOFTRESET_WAIT	10000
461int omap_dss_reset(struct omap_hwmod *oh)
462{
463	struct omap_hwmod_opt_clk *oc;
464	int c = 0;
465	int i, r;
466
467	if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
468		pr_err("dss_core: hwmod data doesn't contain reset data\n");
469		return -EINVAL;
470	}
471
472	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
473		if (oc->_clk)
474			clk_enable(oc->_clk);
475
476	dispc_disable_outputs();
477
478	/* clear SDI registers */
479	if (cpu_is_omap3430()) {
480		omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
481		omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
482	}
483
484	/*
485	 * clear DSS_CONTROL register to switch DSS clock sources to
486	 * PRCM clock, if any
487	 */
488	omap_hwmod_write(0x0, oh, DSS_CONTROL);
489
490	omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
491				& SYSS_RESETDONE_MASK),
492			MAX_MODULE_SOFTRESET_WAIT, c);
493
494	if (c == MAX_MODULE_SOFTRESET_WAIT)
495		pr_warning("dss_core: waiting for reset to finish failed\n");
496	else
497		pr_debug("dss_core: softreset done\n");
498
499	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
500		if (oc->_clk)
501			clk_disable(oc->_clk);
502
503	r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
504
505	return r;
506}

  1/*
  2 * OMAP2plus display device setup / initialization.
  3 *
  4 * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
  5 *	Senthilvadivu Guruswamy
  6 *	Sumit Semwal
  7 *
  8 * This program is free software; you can redistribute it and/or modify
  9 * it under the terms of the GNU General Public License version 2 as
 10 * published by the Free Software Foundation.
 11 *
 12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 13 * kind, whether express or implied; without even the implied warranty
 14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 15 * GNU General Public License for more details.
 16 */
 17
 18#include <linux/string.h>
 19#include <linux/kernel.h>
 20#include <linux/init.h>
 21#include <linux/platform_device.h>
 22#include <linux/io.h>
 23#include <linux/clk.h>
 24#include <linux/err.h>
 25#include <linux/delay.h>
 26#include <linux/of.h>
 27#include <linux/of_platform.h>
 28#include <linux/slab.h>
 29#include <linux/mfd/syscon.h>
 30#include <linux/regmap.h>
 31
 32#include <linux/platform_data/omapdss.h>
 33#include "omap_hwmod.h"
 34#include "omap_device.h"
 35#include "common.h"
 36
 37#include "soc.h"
 38#include "iomap.h"
 
 39#include "control.h"
 40#include "display.h"
 41#include "prm.h"
 42
 43#define DISPC_CONTROL		0x0040
 44#define DISPC_CONTROL2		0x0238
 45#define DISPC_CONTROL3		0x0848
 46#define DISPC_IRQSTATUS		0x0018
 47
 
 
 48#define DSS_CONTROL		0x40
 49#define DSS_SDI_CONTROL		0x44
 50#define DSS_PLL_CONTROL		0x48
 51
 52#define LCD_EN_MASK		(0x1 << 0)
 53#define DIGIT_EN_MASK		(0x1 << 1)
 54
 55#define FRAMEDONE_IRQ_SHIFT	0
 56#define EVSYNC_EVEN_IRQ_SHIFT	2
 57#define EVSYNC_ODD_IRQ_SHIFT	3
 58#define FRAMEDONE2_IRQ_SHIFT	22
 59#define FRAMEDONE3_IRQ_SHIFT	30
 60#define FRAMEDONETV_IRQ_SHIFT	24
 61
 62/*
 63 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
 64 *     reset before deciding that something has gone wrong
 65 */
 66#define FRAMEDONE_IRQ_TIMEOUT		100
 67
 68#if defined(CONFIG_FB_OMAP2)
 69static struct platform_device omap_display_device = {
 70	.name          = "omapdss",
 71	.id            = -1,
 72	.dev            = {
 73		.platform_data = NULL,
 74	},
 75};
 76
 77#define OMAP4_DSIPHY_SYSCON_OFFSET		0x78
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 78
 79static struct regmap *omap4_dsi_mux_syscon;
 
 
 
 
 
 
 
 
 
 
 
 
 80
 81static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
 82{
 83	u32 enable_mask, enable_shift;
 84	u32 pipd_mask, pipd_shift;
 85	u32 reg;
 86	int ret;
 87
 88	if (dsi_id == 0) {
 89		enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
 90		enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
 91		pipd_mask = OMAP4_DSI1_PIPD_MASK;
 92		pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
 93	} else if (dsi_id == 1) {
 94		enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
 95		enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
 96		pipd_mask = OMAP4_DSI2_PIPD_MASK;
 97		pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
 98	} else {
 99		return -ENODEV;
100	}
101
102	ret = regmap_read(omap4_dsi_mux_syscon,
103					  OMAP4_DSIPHY_SYSCON_OFFSET,
104					  &reg);
105	if (ret)
106		return ret;
107
108	reg &= ~enable_mask;
109	reg &= ~pipd_mask;
110
111	reg |= (lanes << enable_shift) & enable_mask;
112	reg |= (lanes << pipd_shift) & pipd_mask;
113
114	regmap_write(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, reg);
 
 
 
 
 
 
 
 
115
116	return 0;
117}
118
119static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
120{
121	if (cpu_is_omap44xx())
122		return omap4_dsi_mux_pads(dsi_id, lane_mask);
123
124	return 0;
125}
126
127static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
128{
129	if (cpu_is_omap44xx())
130		omap4_dsi_mux_pads(dsi_id, 0);
131}
132
133static enum omapdss_version __init omap_display_get_version(void)
134{
135	if (cpu_is_omap24xx())
136		return OMAPDSS_VER_OMAP24xx;
137	else if (cpu_is_omap3630())
138		return OMAPDSS_VER_OMAP3630;
139	else if (cpu_is_omap34xx()) {
140		if (soc_is_am35xx()) {
141			return OMAPDSS_VER_AM35xx;
142		} else {
143			if (omap_rev() < OMAP3430_REV_ES3_0)
144				return OMAPDSS_VER_OMAP34xx_ES1;
145			else
146				return OMAPDSS_VER_OMAP34xx_ES3;
147		}
148	} else if (omap_rev() == OMAP4430_REV_ES1_0)
149		return OMAPDSS_VER_OMAP4430_ES1;
150	else if (omap_rev() == OMAP4430_REV_ES2_0 ||
151			omap_rev() == OMAP4430_REV_ES2_1 ||
152			omap_rev() == OMAP4430_REV_ES2_2)
153		return OMAPDSS_VER_OMAP4430_ES2;
154	else if (cpu_is_omap44xx())
155		return OMAPDSS_VER_OMAP4;
156	else if (soc_is_omap54xx())
157		return OMAPDSS_VER_OMAP5;
158	else if (soc_is_am43xx())
159		return OMAPDSS_VER_AM43xx;
160	else if (soc_is_dra7xx())
161		return OMAPDSS_VER_DRA7xx;
162	else
163		return OMAPDSS_VER_UNKNOWN;
164}
165
166static int __init omapdss_init_fbdev(void)
 
 
167{
168	static struct omap_dss_board_info board_data = {
169		.dsi_enable_pads = omap_dsi_enable_pads,
170		.dsi_disable_pads = omap_dsi_disable_pads,
171	};
172	struct device_node *node;
173	int r;
174
175	board_data.version = omap_display_get_version();
176	if (board_data.version == OMAPDSS_VER_UNKNOWN) {
177		pr_err("DSS not supported on this SoC\n");
178		return -ENODEV;
 
 
 
 
 
 
 
 
179	}
180
181	omap_display_device.dev.platform_data = &board_data;
 
182
183	r = platform_device_register(&omap_display_device);
184	if (r < 0) {
185		pr_err("Unable to register omapdss device\n");
186		return r;
187	}
188
189	/* create vrfb device */
190	r = omap_init_vrfb();
191	if (r < 0) {
192		pr_err("Unable to register omapvrfb device\n");
193		return r;
 
194	}
195
196	/* create FB device */
197	r = omap_init_fb();
198	if (r < 0) {
199		pr_err("Unable to register omapfb device\n");
200		return r;
201	}
202
203	/* create V4L2 display device */
204	r = omap_init_vout();
205	if (r < 0) {
206		pr_err("Unable to register omap_vout device\n");
207		return r;
208	}
209
210	/* add DSI info for omap4 */
211	node = of_find_node_by_name(NULL, "omap4_padconf_global");
212	if (node)
213		omap4_dsi_mux_syscon = syscon_node_to_regmap(node);
214
215	return 0;
 
216}
217
218static const char * const omapdss_compat_names[] __initconst = {
219	"ti,omap2-dss",
220	"ti,omap3-dss",
221	"ti,omap4-dss",
222	"ti,omap5-dss",
223	"ti,dra7-dss",
224};
 
 
 
 
 
 
 
 
 
 
 
 
 
 
225
226static struct device_node * __init omapdss_find_dss_of_node(void)
227{
228	struct device_node *node;
229	int i;
 
230
231	for (i = 0; i < ARRAY_SIZE(omapdss_compat_names); ++i) {
232		node = of_find_compatible_node(NULL, NULL,
233			omapdss_compat_names[i]);
234		if (node)
235			return node;
236	}
237
238	return NULL;
 
 
 
239}
240
241static int __init omapdss_init_of(void)
242{
243	int r;
244	struct device_node *node;
245	struct platform_device *pdev;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
246
247	/* only create dss helper devices if dss is enabled in the .dts */
248
249	node = omapdss_find_dss_of_node();
250	if (!node)
251		return 0;
 
 
 
 
 
 
 
252
253	if (!of_device_is_available(node)) {
254		of_node_put(node);
255		return 0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
256	}
257
258	pdev = of_find_device_by_node(node);
259
260	if (!pdev) {
261		pr_err("Unable to find DSS platform device\n");
262		return -ENODEV;
 
 
263	}
264
265	r = of_platform_populate(node, NULL, NULL, &pdev->dev);
266	if (r) {
267		pr_err("Unable to populate DSS submodule devices\n");
268		put_device(&pdev->dev);
269		return r;
 
 
270	}
271
272	return omapdss_init_fbdev();
273}
274omap_device_initcall(omapdss_init_of);
275#endif /* CONFIG_FB_OMAP2 */
276
277static void dispc_disable_outputs(void)
278{
279	u32 v, irq_mask = 0;
280	bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
281	int i;
282	struct omap_dss_dispc_dev_attr *da;
283	struct omap_hwmod *oh;
284
285	oh = omap_hwmod_lookup("dss_dispc");
286	if (!oh) {
287		WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
288		return;
289	}
290
291	if (!oh->dev_attr) {
292		pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
293		return;
294	}
295
296	da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
297
298	/* store value of LCDENABLE and DIGITENABLE bits */
299	v = omap_hwmod_read(oh, DISPC_CONTROL);
300	lcd_en = v & LCD_EN_MASK;
301	digit_en = v & DIGIT_EN_MASK;
302
303	/* store value of LCDENABLE for LCD2 */
304	if (da->manager_count > 2) {
305		v = omap_hwmod_read(oh, DISPC_CONTROL2);
306		lcd2_en = v & LCD_EN_MASK;
307	}
308
309	/* store value of LCDENABLE for LCD3 */
310	if (da->manager_count > 3) {
311		v = omap_hwmod_read(oh, DISPC_CONTROL3);
312		lcd3_en = v & LCD_EN_MASK;
313	}
314
315	if (!(lcd_en | digit_en | lcd2_en | lcd3_en))
316		return; /* no managers currently enabled */
317
318	/*
319	 * If any manager was enabled, we need to disable it before
320	 * DSS clocks are disabled or DISPC module is reset
321	 */
322	if (lcd_en)
323		irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
324
325	if (digit_en) {
326		if (da->has_framedonetv_irq) {
327			irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
328		} else {
329			irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
330				1 << EVSYNC_ODD_IRQ_SHIFT;
331		}
332	}
333
334	if (lcd2_en)
335		irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
336	if (lcd3_en)
337		irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT;
338
339	/*
340	 * clear any previous FRAMEDONE, FRAMEDONETV,
341	 * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
342	 */
343	omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
344
345	/* disable LCD and TV managers */
346	v = omap_hwmod_read(oh, DISPC_CONTROL);
347	v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
348	omap_hwmod_write(v, oh, DISPC_CONTROL);
349
350	/* disable LCD2 manager */
351	if (da->manager_count > 2) {
352		v = omap_hwmod_read(oh, DISPC_CONTROL2);
353		v &= ~LCD_EN_MASK;
354		omap_hwmod_write(v, oh, DISPC_CONTROL2);
355	}
356
357	/* disable LCD3 manager */
358	if (da->manager_count > 3) {
359		v = omap_hwmod_read(oh, DISPC_CONTROL3);
360		v &= ~LCD_EN_MASK;
361		omap_hwmod_write(v, oh, DISPC_CONTROL3);
362	}
363
364	i = 0;
365	while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
366	       irq_mask) {
367		i++;
368		if (i > FRAMEDONE_IRQ_TIMEOUT) {
369			pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
370			break;
371		}
372		mdelay(1);
373	}
374}
375
 
376int omap_dss_reset(struct omap_hwmod *oh)
377{
378	struct omap_hwmod_opt_clk *oc;
379	int c = 0;
380	int i, r;
381
382	if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
383		pr_err("dss_core: hwmod data doesn't contain reset data\n");
384		return -EINVAL;
385	}
386
387	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
388		clk_prepare_enable(oc->_clk);
 
389
390	dispc_disable_outputs();
391
392	/* clear SDI registers */
393	if (cpu_is_omap3430()) {
394		omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
395		omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
396	}
397
398	/*
399	 * clear DSS_CONTROL register to switch DSS clock sources to
400	 * PRCM clock, if any
401	 */
402	omap_hwmod_write(0x0, oh, DSS_CONTROL);
403
404	omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
405				& SYSS_RESETDONE_MASK),
406			MAX_MODULE_SOFTRESET_WAIT, c);
407
408	if (c == MAX_MODULE_SOFTRESET_WAIT)
409		pr_warn("dss_core: waiting for reset to finish failed\n");
410	else
411		pr_debug("dss_core: softreset done\n");
412
413	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
414		clk_disable_unprepare(oc->_clk);
 
415
416	r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
417
418	return r;
419}