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1/*
2 * Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
3 * Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#ifndef __AR7_H__
21#define __AR7_H__
22
23#include <linux/delay.h>
24#include <linux/io.h>
25#include <linux/errno.h>
26
27#include <asm/addrspace.h>
28
29#define AR7_SDRAM_BASE 0x14000000
30
31#define AR7_REGS_BASE 0x08610000
32
33#define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000)
34#define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900)
35/* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */
36#define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00)
37#define AR7_REGS_CLOCKS (AR7_REGS_POWER + 0x80)
38#define UR8_REGS_CLOCKS (AR7_REGS_POWER + 0x20)
39#define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
40#define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
41#define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600)
42#define AR7_REGS_PINSEL (AR7_REGS_BASE + 0x160C)
43#define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
44#define AR7_REGS_DCL (AR7_REGS_BASE + 0x1a00)
45#define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00)
46#define AR7_REGS_MDIO (AR7_REGS_BASE + 0x1e00)
47#define AR7_REGS_IRQ (AR7_REGS_BASE + 0x2400)
48#define AR7_REGS_MAC1 (AR7_REGS_BASE + 0x2800)
49
50#define AR7_REGS_WDT (AR7_REGS_BASE + 0x1f00)
51#define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00)
52#define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
53
54/* Titan registers */
55#define TITAN_REGS_ESWITCH_BASE (0x08640000)
56#define TITAN_REGS_MAC0 (TITAN_REGS_ESWITCH_BASE)
57#define TITAN_REGS_MAC1 (TITAN_REGS_ESWITCH_BASE + 0x0800)
58#define TITAN_REGS_MDIO (TITAN_REGS_ESWITCH_BASE + 0x02000)
59#define TITAN_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1c00)
60#define TITAN_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1300)
61
62#define AR7_RESET_PERIPHERAL 0x0
63#define AR7_RESET_SOFTWARE 0x4
64#define AR7_RESET_STATUS 0x8
65
66#define AR7_RESET_BIT_CPMAC_LO 17
67#define AR7_RESET_BIT_CPMAC_HI 21
68#define AR7_RESET_BIT_MDIO 22
69#define AR7_RESET_BIT_EPHY 26
70
71#define TITAN_RESET_BIT_EPHY1 28
72
73/* GPIO control registers */
74#define AR7_GPIO_INPUT 0x0
75#define AR7_GPIO_OUTPUT 0x4
76#define AR7_GPIO_DIR 0x8
77#define AR7_GPIO_ENABLE 0xc
78#define TITAN_GPIO_INPUT_0 0x0
79#define TITAN_GPIO_INPUT_1 0x4
80#define TITAN_GPIO_OUTPUT_0 0x8
81#define TITAN_GPIO_OUTPUT_1 0xc
82#define TITAN_GPIO_DIR_0 0x10
83#define TITAN_GPIO_DIR_1 0x14
84#define TITAN_GPIO_ENBL_0 0x18
85#define TITAN_GPIO_ENBL_1 0x1c
86
87#define AR7_CHIP_7100 0x18
88#define AR7_CHIP_7200 0x2b
89#define AR7_CHIP_7300 0x05
90#define AR7_CHIP_TITAN 0x07
91#define TITAN_CHIP_1050 0x0f
92#define TITAN_CHIP_1055 0x0e
93#define TITAN_CHIP_1056 0x0d
94#define TITAN_CHIP_1060 0x07
95
96/* Interrupts */
97#define AR7_IRQ_UART0 15
98#define AR7_IRQ_UART1 16
99
100/* Clocks */
101#define AR7_AFE_CLOCK 35328000
102#define AR7_REF_CLOCK 25000000
103#define AR7_XTAL_CLOCK 24000000
104
105/* DCL */
106#define AR7_WDT_HW_ENA 0x10
107
108struct plat_cpmac_data {
109 int reset_bit;
110 int power_bit;
111 u32 phy_mask;
112 char dev_addr[6];
113};
114
115struct plat_dsl_data {
116 int reset_bit_dsl;
117 int reset_bit_sar;
118};
119
120extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
121
122static inline int ar7_is_titan(void)
123{
124 return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x24)) & 0xffff) ==
125 AR7_CHIP_TITAN;
126}
127
128static inline u16 ar7_chip_id(void)
129{
130 return ar7_is_titan() ? AR7_CHIP_TITAN : (readl((void *)
131 KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff);
132}
133
134static inline u16 titan_chip_id(void)
135{
136 unsigned int val = readl((void *)KSEG1ADDR(AR7_REGS_GPIO +
137 TITAN_GPIO_INPUT_1));
138 return ((val >> 12) & 0x0f);
139}
140
141static inline u8 ar7_chip_rev(void)
142{
143 return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + (ar7_is_titan() ? 0x24 :
144 0x14))) >> 16) & 0xff;
145}
146
147struct clk {
148 unsigned int rate;
149};
150
151static inline int ar7_has_high_cpmac(void)
152{
153 u16 chip_id = ar7_chip_id();
154 switch (chip_id) {
155 case AR7_CHIP_7100:
156 case AR7_CHIP_7200:
157 return 0;
158 case AR7_CHIP_7300:
159 return 1;
160 default:
161 return -ENXIO;
162 }
163}
164#define ar7_has_high_vlynq ar7_has_high_cpmac
165#define ar7_has_second_uart ar7_has_high_cpmac
166
167static inline void ar7_device_enable(u32 bit)
168{
169 void *reset_reg =
170 (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PERIPHERAL);
171 writel(readl(reset_reg) | (1 << bit), reset_reg);
172 msleep(20);
173}
174
175static inline void ar7_device_disable(u32 bit)
176{
177 void *reset_reg =
178 (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PERIPHERAL);
179 writel(readl(reset_reg) & ~(1 << bit), reset_reg);
180 msleep(20);
181}
182
183static inline void ar7_device_reset(u32 bit)
184{
185 ar7_device_disable(bit);
186 ar7_device_enable(bit);
187}
188
189static inline void ar7_device_on(u32 bit)
190{
191 void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
192 writel(readl(power_reg) | (1 << bit), power_reg);
193 msleep(20);
194}
195
196static inline void ar7_device_off(u32 bit)
197{
198 void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
199 writel(readl(power_reg) & ~(1 << bit), power_reg);
200 msleep(20);
201}
202
203int __init ar7_gpio_init(void);
204void __init ar7_init_clocks(void);
205
206#endif /* __AR7_H__ */
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
4 * Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
5 */
6
7#ifndef __AR7_H__
8#define __AR7_H__
9
10#include <linux/delay.h>
11#include <linux/io.h>
12#include <linux/errno.h>
13
14#include <asm/addrspace.h>
15
16#define AR7_SDRAM_BASE 0x14000000
17
18#define AR7_REGS_BASE 0x08610000
19
20#define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000)
21#define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900)
22/* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */
23#define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00)
24#define AR7_REGS_CLOCKS (AR7_REGS_POWER + 0x80)
25#define UR8_REGS_CLOCKS (AR7_REGS_POWER + 0x20)
26#define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
27#define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
28#define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600)
29#define AR7_REGS_PINSEL (AR7_REGS_BASE + 0x160C)
30#define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
31#define AR7_REGS_DCL (AR7_REGS_BASE + 0x1a00)
32#define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00)
33#define AR7_REGS_MDIO (AR7_REGS_BASE + 0x1e00)
34#define AR7_REGS_IRQ (AR7_REGS_BASE + 0x2400)
35#define AR7_REGS_MAC1 (AR7_REGS_BASE + 0x2800)
36
37#define AR7_REGS_WDT (AR7_REGS_BASE + 0x1f00)
38#define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00)
39#define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
40
41/* Titan registers */
42#define TITAN_REGS_ESWITCH_BASE (0x08640000)
43#define TITAN_REGS_MAC0 (TITAN_REGS_ESWITCH_BASE)
44#define TITAN_REGS_MAC1 (TITAN_REGS_ESWITCH_BASE + 0x0800)
45#define TITAN_REGS_MDIO (TITAN_REGS_ESWITCH_BASE + 0x02000)
46#define TITAN_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1c00)
47#define TITAN_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1300)
48
49#define AR7_RESET_PERIPHERAL 0x0
50#define AR7_RESET_SOFTWARE 0x4
51#define AR7_RESET_STATUS 0x8
52
53#define AR7_RESET_BIT_CPMAC_LO 17
54#define AR7_RESET_BIT_CPMAC_HI 21
55#define AR7_RESET_BIT_MDIO 22
56#define AR7_RESET_BIT_EPHY 26
57
58#define TITAN_RESET_BIT_EPHY1 28
59
60/* GPIO control registers */
61#define AR7_GPIO_INPUT 0x0
62#define AR7_GPIO_OUTPUT 0x4
63#define AR7_GPIO_DIR 0x8
64#define AR7_GPIO_ENABLE 0xc
65#define TITAN_GPIO_INPUT_0 0x0
66#define TITAN_GPIO_INPUT_1 0x4
67#define TITAN_GPIO_OUTPUT_0 0x8
68#define TITAN_GPIO_OUTPUT_1 0xc
69#define TITAN_GPIO_DIR_0 0x10
70#define TITAN_GPIO_DIR_1 0x14
71#define TITAN_GPIO_ENBL_0 0x18
72#define TITAN_GPIO_ENBL_1 0x1c
73
74#define AR7_CHIP_7100 0x18
75#define AR7_CHIP_7200 0x2b
76#define AR7_CHIP_7300 0x05
77#define AR7_CHIP_TITAN 0x07
78#define TITAN_CHIP_1050 0x0f
79#define TITAN_CHIP_1055 0x0e
80#define TITAN_CHIP_1056 0x0d
81#define TITAN_CHIP_1060 0x07
82
83/* Interrupts */
84#define AR7_IRQ_UART0 15
85#define AR7_IRQ_UART1 16
86
87/* Clocks */
88#define AR7_AFE_CLOCK 35328000
89#define AR7_REF_CLOCK 25000000
90#define AR7_XTAL_CLOCK 24000000
91
92/* DCL */
93#define AR7_WDT_HW_ENA 0x10
94
95struct plat_cpmac_data {
96 int reset_bit;
97 int power_bit;
98 u32 phy_mask;
99 char dev_addr[6];
100};
101
102struct plat_dsl_data {
103 int reset_bit_dsl;
104 int reset_bit_sar;
105};
106
107extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
108
109static inline int ar7_is_titan(void)
110{
111 return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x24)) & 0xffff) ==
112 AR7_CHIP_TITAN;
113}
114
115static inline u16 ar7_chip_id(void)
116{
117 return ar7_is_titan() ? AR7_CHIP_TITAN : (readl((void *)
118 KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff);
119}
120
121static inline u16 titan_chip_id(void)
122{
123 unsigned int val = readl((void *)KSEG1ADDR(AR7_REGS_GPIO +
124 TITAN_GPIO_INPUT_1));
125 return ((val >> 12) & 0x0f);
126}
127
128static inline u8 ar7_chip_rev(void)
129{
130 return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + (ar7_is_titan() ? 0x24 :
131 0x14))) >> 16) & 0xff;
132}
133
134static inline int ar7_has_high_cpmac(void)
135{
136 u16 chip_id = ar7_chip_id();
137 switch (chip_id) {
138 case AR7_CHIP_7100:
139 case AR7_CHIP_7200:
140 return 0;
141 case AR7_CHIP_7300:
142 return 1;
143 default:
144 return -ENXIO;
145 }
146}
147#define ar7_has_high_vlynq ar7_has_high_cpmac
148#define ar7_has_second_uart ar7_has_high_cpmac
149
150static inline void ar7_device_enable(u32 bit)
151{
152 void *reset_reg =
153 (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PERIPHERAL);
154 writel(readl(reset_reg) | (1 << bit), reset_reg);
155 msleep(20);
156}
157
158static inline void ar7_device_disable(u32 bit)
159{
160 void *reset_reg =
161 (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PERIPHERAL);
162 writel(readl(reset_reg) & ~(1 << bit), reset_reg);
163 msleep(20);
164}
165
166static inline void ar7_device_reset(u32 bit)
167{
168 ar7_device_disable(bit);
169 ar7_device_enable(bit);
170}
171
172static inline void ar7_device_on(u32 bit)
173{
174 void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
175 writel(readl(power_reg) | (1 << bit), power_reg);
176 msleep(20);
177}
178
179static inline void ar7_device_off(u32 bit)
180{
181 void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
182 writel(readl(power_reg) & ~(1 << bit), power_reg);
183 msleep(20);
184}
185
186int __init ar7_gpio_init(void);
187void __init ar7_init_clocks(void);
188
189/* Board specific GPIO functions */
190int ar7_gpio_enable(unsigned gpio);
191int ar7_gpio_disable(unsigned gpio);
192
193#endif /* __AR7_H__ */