1/*
 2 * AT91 Power Management
 3 *
 4 * Copyright (C) 2005 David Brownell
 5 *
 6 * This program is free software; you can redistribute it and/or modify
 7 * it under the terms of the GNU General Public License as published by
 8 * the Free Software Foundation; either version 2 of the License, or
 9 * (at your option) any later version.
10 */
11#ifndef __ARCH_ARM_MACH_AT91_PM
12#define __ARCH_ARM_MACH_AT91_PM
13
14#include <mach/at91_ramc.h>
15#include <mach/at91rm9200_sdramc.h>
16
17/*
18 * The AT91RM9200 goes into self-refresh mode with this command, and will
19 * terminate self-refresh automatically on the next SDRAM access.
20 *
21 * Self-refresh mode is exited as soon as a memory access is made, but we don't
22 * know for sure when that happens. However, we need to restore the low-power
23 * mode if it was enabled before going idle. Restoring low-power mode while
24 * still in self-refresh is "not recommended", but seems to work.
25 */
26
27static inline void at91rm9200_standby(void)
28{
29	u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
30
31	asm volatile(
32		"b    1f\n\t"
33		".align    5\n\t"
34		"1:  mcr    p15, 0, %0, c7, c10, 4\n\t"
35		"    str    %0, [%1, %2]\n\t"
36		"    str    %3, [%1, %4]\n\t"
37		"    mcr    p15, 0, %0, c7, c0, 4\n\t"
38		"    str    %5, [%1, %2]"
39		:
40		: "r" (0), "r" (AT91_BASE_SYS), "r" (AT91RM9200_SDRAMC_LPR),
41		  "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
42		  "r" (lpr));
43}
44
45/* We manage both DDRAM/SDRAM controllers, we need more than one value to
46 * remember.
47 */
48static inline void at91sam9g45_standby(void)
49{
50	/* Those two values allow us to delay self-refresh activation
51	 * to the maximum. */
52	u32 lpr0, lpr1;
53	u32 saved_lpr0, saved_lpr1;
54
55	saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
56	lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
57	lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
58
59	saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
60	lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
61	lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
62
63	/* self-refresh mode now */
64	at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
65	at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
66
67	cpu_do_idle();
68
69	at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
70	at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
71}
72
73#ifdef CONFIG_SOC_AT91SAM9263
74/*
75 * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
76 * handle those cases both here and in the Suspend-To-RAM support.
77 */
78#warning Assuming EB1 SDRAM controller is *NOT* used
 
 
 
 
 
 
 
 
 
 
 
 
79#endif
80
81static inline void at91sam9_standby(void)
82{
83	u32 saved_lpr, lpr;
84
85	saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
86
87	lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
88	at91_ramc_write(0, AT91_SDRAMC_LPR, lpr |
89			AT91_SDRAMC_LPCB_SELF_REFRESH);
90
91	cpu_do_idle();
92
93	at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr);
94}
95
96#endif

 1/* SPDX-License-Identifier: GPL-2.0-or-later */
 2/*
 3 * AT91 Power Management
 4 *
 5 * Copyright (C) 2005 David Brownell
 
 
 
 
 
 6 */
 7#ifndef __ARCH_ARM_MACH_AT91_PM
 8#define __ARCH_ARM_MACH_AT91_PM
 9
10#include <asm/proc-fns.h>
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
11
12#include <linux/mfd/syscon/atmel-mc.h>
13#include <soc/at91/at91sam9_ddrsdr.h>
14#include <soc/at91/at91sam9_sdramc.h>
15
16#define AT91_MEMCTRL_MC		0
17#define AT91_MEMCTRL_SDRAMC	1
18#define AT91_MEMCTRL_DDRSDR	2
19
20#define	AT91_PM_STANDBY		0x00
21#define AT91_PM_ULP0		0x01
22#define AT91_PM_ULP0_FAST	0x02
23#define AT91_PM_ULP1		0x03
24#define	AT91_PM_BACKUP		0x04
25
26#ifndef __ASSEMBLY__
27struct at91_pm_data {
28	void __iomem *pmc;
29	void __iomem *ramc[2];
30	unsigned long uhp_udp_mask;
31	unsigned int memctrl;
32	unsigned int mode;
33	void __iomem *shdwc;
34	void __iomem *sfrbu;
35	unsigned int standby_mode;
36	unsigned int suspend_mode;
37	unsigned int pmc_mckr_offset;
38	unsigned int pmc_version;
39};
40#endif
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
41
42#endif