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1/*
2 * PCI Express PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/signal.h>
34#include <linux/jiffies.h>
35#include <linux/timer.h>
36#include <linux/pci.h>
37#include <linux/interrupt.h>
38#include <linux/time.h>
39#include <linux/slab.h>
40
41#include "../pci.h"
42#include "pciehp.h"
43
44static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
45{
46 struct pci_dev *dev = ctrl->pcie->port;
47 return pci_read_config_word(dev, pci_pcie_cap(dev) + reg, value);
48}
49
50static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
51{
52 struct pci_dev *dev = ctrl->pcie->port;
53 return pci_read_config_dword(dev, pci_pcie_cap(dev) + reg, value);
54}
55
56static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
57{
58 struct pci_dev *dev = ctrl->pcie->port;
59 return pci_write_config_word(dev, pci_pcie_cap(dev) + reg, value);
60}
61
62static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
63{
64 struct pci_dev *dev = ctrl->pcie->port;
65 return pci_write_config_dword(dev, pci_pcie_cap(dev) + reg, value);
66}
67
68/* Power Control Command */
69#define POWER_ON 0
70#define POWER_OFF PCI_EXP_SLTCTL_PCC
71
72static irqreturn_t pcie_isr(int irq, void *dev_id);
73static void start_int_poll_timer(struct controller *ctrl, int sec);
74
75/* This is the interrupt polling timeout function. */
76static void int_poll_timeout(unsigned long data)
77{
78 struct controller *ctrl = (struct controller *)data;
79
80 /* Poll for interrupt events. regs == NULL => polling */
81 pcie_isr(0, ctrl);
82
83 init_timer(&ctrl->poll_timer);
84 if (!pciehp_poll_time)
85 pciehp_poll_time = 2; /* default polling interval is 2 sec */
86
87 start_int_poll_timer(ctrl, pciehp_poll_time);
88}
89
90/* This function starts the interrupt polling timer. */
91static void start_int_poll_timer(struct controller *ctrl, int sec)
92{
93 /* Clamp to sane value */
94 if ((sec <= 0) || (sec > 60))
95 sec = 2;
96
97 ctrl->poll_timer.function = &int_poll_timeout;
98 ctrl->poll_timer.data = (unsigned long)ctrl;
99 ctrl->poll_timer.expires = jiffies + sec * HZ;
100 add_timer(&ctrl->poll_timer);
101}
102
103static inline int pciehp_request_irq(struct controller *ctrl)
104{
105 int retval, irq = ctrl->pcie->irq;
106
107 /* Install interrupt polling timer. Start with 10 sec delay */
108 if (pciehp_poll_mode) {
109 init_timer(&ctrl->poll_timer);
110 start_int_poll_timer(ctrl, 10);
111 return 0;
112 }
113
114 /* Installs the interrupt handler */
115 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
116 if (retval)
117 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
118 irq);
119 return retval;
120}
121
122static inline void pciehp_free_irq(struct controller *ctrl)
123{
124 if (pciehp_poll_mode)
125 del_timer_sync(&ctrl->poll_timer);
126 else
127 free_irq(ctrl->pcie->irq, ctrl);
128}
129
130static int pcie_poll_cmd(struct controller *ctrl)
131{
132 u16 slot_status;
133 int err, timeout = 1000;
134
135 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
136 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
137 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
138 return 1;
139 }
140 while (timeout > 0) {
141 msleep(10);
142 timeout -= 10;
143 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
144 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
145 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
146 return 1;
147 }
148 }
149 return 0; /* timeout */
150}
151
152static void pcie_wait_cmd(struct controller *ctrl, int poll)
153{
154 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
155 unsigned long timeout = msecs_to_jiffies(msecs);
156 int rc;
157
158 if (poll)
159 rc = pcie_poll_cmd(ctrl);
160 else
161 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
162 if (!rc)
163 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n");
164}
165
166/**
167 * pcie_write_cmd - Issue controller command
168 * @ctrl: controller to which the command is issued
169 * @cmd: command value written to slot control register
170 * @mask: bitmask of slot control register to be modified
171 */
172static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
173{
174 int retval = 0;
175 u16 slot_status;
176 u16 slot_ctrl;
177
178 mutex_lock(&ctrl->ctrl_lock);
179
180 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
181 if (retval) {
182 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
183 __func__);
184 goto out;
185 }
186
187 if (slot_status & PCI_EXP_SLTSTA_CC) {
188 if (!ctrl->no_cmd_complete) {
189 /*
190 * After 1 sec and CMD_COMPLETED still not set, just
191 * proceed forward to issue the next command according
192 * to spec. Just print out the error message.
193 */
194 ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
195 } else if (!NO_CMD_CMPL(ctrl)) {
196 /*
197 * This controller semms to notify of command completed
198 * event even though it supports none of power
199 * controller, attention led, power led and EMI.
200 */
201 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to "
202 "wait for command completed event.\n");
203 ctrl->no_cmd_complete = 0;
204 } else {
205 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe "
206 "the controller is broken.\n");
207 }
208 }
209
210 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
211 if (retval) {
212 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
213 goto out;
214 }
215
216 slot_ctrl &= ~mask;
217 slot_ctrl |= (cmd & mask);
218 ctrl->cmd_busy = 1;
219 smp_mb();
220 retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl);
221 if (retval)
222 ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n");
223
224 /*
225 * Wait for command completion.
226 */
227 if (!retval && !ctrl->no_cmd_complete) {
228 int poll = 0;
229 /*
230 * if hotplug interrupt is not enabled or command
231 * completed interrupt is not enabled, we need to poll
232 * command completed event.
233 */
234 if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) ||
235 !(slot_ctrl & PCI_EXP_SLTCTL_CCIE))
236 poll = 1;
237 pcie_wait_cmd(ctrl, poll);
238 }
239 out:
240 mutex_unlock(&ctrl->ctrl_lock);
241 return retval;
242}
243
244static bool check_link_active(struct controller *ctrl)
245{
246 bool ret = false;
247 u16 lnk_status;
248
249 if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status))
250 return ret;
251
252 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
253
254 if (ret)
255 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
256
257 return ret;
258}
259
260static void __pcie_wait_link_active(struct controller *ctrl, bool active)
261{
262 int timeout = 1000;
263
264 if (check_link_active(ctrl) == active)
265 return;
266 while (timeout > 0) {
267 msleep(10);
268 timeout -= 10;
269 if (check_link_active(ctrl) == active)
270 return;
271 }
272 ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n",
273 active ? "set" : "cleared");
274}
275
276static void pcie_wait_link_active(struct controller *ctrl)
277{
278 __pcie_wait_link_active(ctrl, true);
279}
280
281static void pcie_wait_link_not_active(struct controller *ctrl)
282{
283 __pcie_wait_link_active(ctrl, false);
284}
285
286static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
287{
288 u32 l;
289 int count = 0;
290 int delay = 1000, step = 20;
291 bool found = false;
292
293 do {
294 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
295 count++;
296
297 if (found)
298 break;
299
300 msleep(step);
301 delay -= step;
302 } while (delay > 0);
303
304 if (count > 1 && pciehp_debug)
305 printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
306 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
307 PCI_FUNC(devfn), count, step, l);
308
309 return found;
310}
311
312int pciehp_check_link_status(struct controller *ctrl)
313{
314 u16 lnk_status;
315 int retval = 0;
316 bool found = false;
317
318 /*
319 * Data Link Layer Link Active Reporting must be capable for
320 * hot-plug capable downstream port. But old controller might
321 * not implement it. In this case, we wait for 1000 ms.
322 */
323 if (ctrl->link_active_reporting)
324 pcie_wait_link_active(ctrl);
325 else
326 msleep(1000);
327
328 /* wait 100ms before read pci conf, and try in 1s */
329 msleep(100);
330 found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
331 PCI_DEVFN(0, 0));
332
333 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
334 if (retval) {
335 ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");
336 return retval;
337 }
338
339 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
340 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
341 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
342 ctrl_err(ctrl, "Link Training Error occurs \n");
343 retval = -1;
344 return retval;
345 }
346
347 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
348
349 if (!found && !retval)
350 retval = -1;
351
352 return retval;
353}
354
355static int __pciehp_link_set(struct controller *ctrl, bool enable)
356{
357 u16 lnk_ctrl;
358 int retval = 0;
359
360 retval = pciehp_readw(ctrl, PCI_EXP_LNKCTL, &lnk_ctrl);
361 if (retval) {
362 ctrl_err(ctrl, "Cannot read LNKCTRL register\n");
363 return retval;
364 }
365
366 if (enable)
367 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
368 else
369 lnk_ctrl |= PCI_EXP_LNKCTL_LD;
370
371 retval = pciehp_writew(ctrl, PCI_EXP_LNKCTL, lnk_ctrl);
372 if (retval) {
373 ctrl_err(ctrl, "Cannot write LNKCTRL register\n");
374 return retval;
375 }
376 ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
377
378 return retval;
379}
380
381static int pciehp_link_enable(struct controller *ctrl)
382{
383 return __pciehp_link_set(ctrl, true);
384}
385
386static int pciehp_link_disable(struct controller *ctrl)
387{
388 return __pciehp_link_set(ctrl, false);
389}
390
391int pciehp_get_attention_status(struct slot *slot, u8 *status)
392{
393 struct controller *ctrl = slot->ctrl;
394 u16 slot_ctrl;
395 u8 atten_led_state;
396 int retval = 0;
397
398 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
399 if (retval) {
400 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
401 return retval;
402 }
403
404 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
405 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
406
407 atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6;
408
409 switch (atten_led_state) {
410 case 0:
411 *status = 0xFF; /* Reserved */
412 break;
413 case 1:
414 *status = 1; /* On */
415 break;
416 case 2:
417 *status = 2; /* Blink */
418 break;
419 case 3:
420 *status = 0; /* Off */
421 break;
422 default:
423 *status = 0xFF;
424 break;
425 }
426
427 return 0;
428}
429
430int pciehp_get_power_status(struct slot *slot, u8 *status)
431{
432 struct controller *ctrl = slot->ctrl;
433 u16 slot_ctrl;
434 u8 pwr_state;
435 int retval = 0;
436
437 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
438 if (retval) {
439 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
440 return retval;
441 }
442 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
443 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
444
445 pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10;
446
447 switch (pwr_state) {
448 case 0:
449 *status = 1;
450 break;
451 case 1:
452 *status = 0;
453 break;
454 default:
455 *status = 0xFF;
456 break;
457 }
458
459 return retval;
460}
461
462int pciehp_get_latch_status(struct slot *slot, u8 *status)
463{
464 struct controller *ctrl = slot->ctrl;
465 u16 slot_status;
466 int retval;
467
468 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
469 if (retval) {
470 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
471 __func__);
472 return retval;
473 }
474 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
475 return 0;
476}
477
478int pciehp_get_adapter_status(struct slot *slot, u8 *status)
479{
480 struct controller *ctrl = slot->ctrl;
481 u16 slot_status;
482 int retval;
483
484 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
485 if (retval) {
486 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
487 __func__);
488 return retval;
489 }
490 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
491 return 0;
492}
493
494int pciehp_query_power_fault(struct slot *slot)
495{
496 struct controller *ctrl = slot->ctrl;
497 u16 slot_status;
498 int retval;
499
500 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
501 if (retval) {
502 ctrl_err(ctrl, "Cannot check for power fault\n");
503 return retval;
504 }
505 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
506}
507
508int pciehp_set_attention_status(struct slot *slot, u8 value)
509{
510 struct controller *ctrl = slot->ctrl;
511 u16 slot_cmd;
512 u16 cmd_mask;
513
514 cmd_mask = PCI_EXP_SLTCTL_AIC;
515 switch (value) {
516 case 0 : /* turn off */
517 slot_cmd = 0x00C0;
518 break;
519 case 1: /* turn on */
520 slot_cmd = 0x0040;
521 break;
522 case 2: /* turn blink */
523 slot_cmd = 0x0080;
524 break;
525 default:
526 return -EINVAL;
527 }
528 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
529 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
530 return pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
531}
532
533void pciehp_green_led_on(struct slot *slot)
534{
535 struct controller *ctrl = slot->ctrl;
536 u16 slot_cmd;
537 u16 cmd_mask;
538
539 slot_cmd = 0x0100;
540 cmd_mask = PCI_EXP_SLTCTL_PIC;
541 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
542 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
543 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
544}
545
546void pciehp_green_led_off(struct slot *slot)
547{
548 struct controller *ctrl = slot->ctrl;
549 u16 slot_cmd;
550 u16 cmd_mask;
551
552 slot_cmd = 0x0300;
553 cmd_mask = PCI_EXP_SLTCTL_PIC;
554 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
555 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
556 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
557}
558
559void pciehp_green_led_blink(struct slot *slot)
560{
561 struct controller *ctrl = slot->ctrl;
562 u16 slot_cmd;
563 u16 cmd_mask;
564
565 slot_cmd = 0x0200;
566 cmd_mask = PCI_EXP_SLTCTL_PIC;
567 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
568 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
569 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
570}
571
572int pciehp_power_on_slot(struct slot * slot)
573{
574 struct controller *ctrl = slot->ctrl;
575 u16 slot_cmd;
576 u16 cmd_mask;
577 u16 slot_status;
578 int retval = 0;
579
580 /* Clear sticky power-fault bit from previous power failures */
581 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
582 if (retval) {
583 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
584 __func__);
585 return retval;
586 }
587 slot_status &= PCI_EXP_SLTSTA_PFD;
588 if (slot_status) {
589 retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status);
590 if (retval) {
591 ctrl_err(ctrl,
592 "%s: Cannot write to SLOTSTATUS register\n",
593 __func__);
594 return retval;
595 }
596 }
597 ctrl->power_fault_detected = 0;
598
599 slot_cmd = POWER_ON;
600 cmd_mask = PCI_EXP_SLTCTL_PCC;
601 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
602 if (retval) {
603 ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd);
604 return retval;
605 }
606 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
607 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
608
609 retval = pciehp_link_enable(ctrl);
610 if (retval)
611 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
612
613 return retval;
614}
615
616int pciehp_power_off_slot(struct slot * slot)
617{
618 struct controller *ctrl = slot->ctrl;
619 u16 slot_cmd;
620 u16 cmd_mask;
621 int retval;
622
623 /* Disable the link at first */
624 pciehp_link_disable(ctrl);
625 /* wait the link is down */
626 if (ctrl->link_active_reporting)
627 pcie_wait_link_not_active(ctrl);
628 else
629 msleep(1000);
630
631 slot_cmd = POWER_OFF;
632 cmd_mask = PCI_EXP_SLTCTL_PCC;
633 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
634 if (retval) {
635 ctrl_err(ctrl, "Write command failed!\n");
636 return retval;
637 }
638 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
639 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
640 return 0;
641}
642
643static irqreturn_t pcie_isr(int irq, void *dev_id)
644{
645 struct controller *ctrl = (struct controller *)dev_id;
646 struct slot *slot = ctrl->slot;
647 u16 detected, intr_loc;
648
649 /*
650 * In order to guarantee that all interrupt events are
651 * serviced, we need to re-inspect Slot Status register after
652 * clearing what is presumed to be the last pending interrupt.
653 */
654 intr_loc = 0;
655 do {
656 if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) {
657 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n",
658 __func__);
659 return IRQ_NONE;
660 }
661
662 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
663 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
664 PCI_EXP_SLTSTA_CC);
665 detected &= ~intr_loc;
666 intr_loc |= detected;
667 if (!intr_loc)
668 return IRQ_NONE;
669 if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) {
670 ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n",
671 __func__);
672 return IRQ_NONE;
673 }
674 } while (detected);
675
676 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
677
678 /* Check Command Complete Interrupt Pending */
679 if (intr_loc & PCI_EXP_SLTSTA_CC) {
680 ctrl->cmd_busy = 0;
681 smp_mb();
682 wake_up(&ctrl->queue);
683 }
684
685 if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
686 return IRQ_HANDLED;
687
688 /* Check MRL Sensor Changed */
689 if (intr_loc & PCI_EXP_SLTSTA_MRLSC)
690 pciehp_handle_switch_change(slot);
691
692 /* Check Attention Button Pressed */
693 if (intr_loc & PCI_EXP_SLTSTA_ABP)
694 pciehp_handle_attention_button(slot);
695
696 /* Check Presence Detect Changed */
697 if (intr_loc & PCI_EXP_SLTSTA_PDC)
698 pciehp_handle_presence_change(slot);
699
700 /* Check Power Fault Detected */
701 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
702 ctrl->power_fault_detected = 1;
703 pciehp_handle_power_fault(slot);
704 }
705 return IRQ_HANDLED;
706}
707
708int pciehp_get_max_lnk_width(struct slot *slot,
709 enum pcie_link_width *value)
710{
711 struct controller *ctrl = slot->ctrl;
712 enum pcie_link_width lnk_wdth;
713 u32 lnk_cap;
714 int retval = 0;
715
716 retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap);
717 if (retval) {
718 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
719 return retval;
720 }
721
722 switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){
723 case 0:
724 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
725 break;
726 case 1:
727 lnk_wdth = PCIE_LNK_X1;
728 break;
729 case 2:
730 lnk_wdth = PCIE_LNK_X2;
731 break;
732 case 4:
733 lnk_wdth = PCIE_LNK_X4;
734 break;
735 case 8:
736 lnk_wdth = PCIE_LNK_X8;
737 break;
738 case 12:
739 lnk_wdth = PCIE_LNK_X12;
740 break;
741 case 16:
742 lnk_wdth = PCIE_LNK_X16;
743 break;
744 case 32:
745 lnk_wdth = PCIE_LNK_X32;
746 break;
747 default:
748 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
749 break;
750 }
751
752 *value = lnk_wdth;
753 ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth);
754
755 return retval;
756}
757
758int pciehp_get_cur_lnk_width(struct slot *slot,
759 enum pcie_link_width *value)
760{
761 struct controller *ctrl = slot->ctrl;
762 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
763 int retval = 0;
764 u16 lnk_status;
765
766 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
767 if (retval) {
768 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
769 __func__);
770 return retval;
771 }
772
773 switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){
774 case 0:
775 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
776 break;
777 case 1:
778 lnk_wdth = PCIE_LNK_X1;
779 break;
780 case 2:
781 lnk_wdth = PCIE_LNK_X2;
782 break;
783 case 4:
784 lnk_wdth = PCIE_LNK_X4;
785 break;
786 case 8:
787 lnk_wdth = PCIE_LNK_X8;
788 break;
789 case 12:
790 lnk_wdth = PCIE_LNK_X12;
791 break;
792 case 16:
793 lnk_wdth = PCIE_LNK_X16;
794 break;
795 case 32:
796 lnk_wdth = PCIE_LNK_X32;
797 break;
798 default:
799 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
800 break;
801 }
802
803 *value = lnk_wdth;
804 ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth);
805
806 return retval;
807}
808
809int pcie_enable_notification(struct controller *ctrl)
810{
811 u16 cmd, mask;
812
813 /*
814 * TBD: Power fault detected software notification support.
815 *
816 * Power fault detected software notification is not enabled
817 * now, because it caused power fault detected interrupt storm
818 * on some machines. On those machines, power fault detected
819 * bit in the slot status register was set again immediately
820 * when it is cleared in the interrupt service routine, and
821 * next power fault detected interrupt was notified again.
822 */
823 cmd = PCI_EXP_SLTCTL_PDCE;
824 if (ATTN_BUTTN(ctrl))
825 cmd |= PCI_EXP_SLTCTL_ABPE;
826 if (MRL_SENS(ctrl))
827 cmd |= PCI_EXP_SLTCTL_MRLSCE;
828 if (!pciehp_poll_mode)
829 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
830
831 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
832 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
833 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE);
834
835 if (pcie_write_cmd(ctrl, cmd, mask)) {
836 ctrl_err(ctrl, "Cannot enable software notification\n");
837 return -1;
838 }
839 return 0;
840}
841
842static void pcie_disable_notification(struct controller *ctrl)
843{
844 u16 mask;
845 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
846 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
847 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
848 PCI_EXP_SLTCTL_DLLSCE);
849 if (pcie_write_cmd(ctrl, 0, mask))
850 ctrl_warn(ctrl, "Cannot disable software notification\n");
851}
852
853int pcie_init_notification(struct controller *ctrl)
854{
855 if (pciehp_request_irq(ctrl))
856 return -1;
857 if (pcie_enable_notification(ctrl)) {
858 pciehp_free_irq(ctrl);
859 return -1;
860 }
861 ctrl->notification_enabled = 1;
862 return 0;
863}
864
865static void pcie_shutdown_notification(struct controller *ctrl)
866{
867 if (ctrl->notification_enabled) {
868 pcie_disable_notification(ctrl);
869 pciehp_free_irq(ctrl);
870 ctrl->notification_enabled = 0;
871 }
872}
873
874static int pcie_init_slot(struct controller *ctrl)
875{
876 struct slot *slot;
877
878 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
879 if (!slot)
880 return -ENOMEM;
881
882 slot->ctrl = ctrl;
883 mutex_init(&slot->lock);
884 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
885 ctrl->slot = slot;
886 return 0;
887}
888
889static void pcie_cleanup_slot(struct controller *ctrl)
890{
891 struct slot *slot = ctrl->slot;
892 cancel_delayed_work(&slot->work);
893 flush_workqueue(pciehp_wq);
894 kfree(slot);
895}
896
897static inline void dbg_ctrl(struct controller *ctrl)
898{
899 int i;
900 u16 reg16;
901 struct pci_dev *pdev = ctrl->pcie->port;
902
903 if (!pciehp_debug)
904 return;
905
906 ctrl_info(ctrl, "Hotplug Controller:\n");
907 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
908 pci_name(pdev), pdev->irq);
909 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor);
910 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device);
911 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n",
912 pdev->subsystem_device);
913 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n",
914 pdev->subsystem_vendor);
915 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n",
916 pci_pcie_cap(pdev));
917 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
918 if (!pci_resource_len(pdev, i))
919 continue;
920 ctrl_info(ctrl, " PCI resource [%d] : %pR\n",
921 i, &pdev->resource[i]);
922 }
923 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
924 ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl));
925 ctrl_info(ctrl, " Attention Button : %3s\n",
926 ATTN_BUTTN(ctrl) ? "yes" : "no");
927 ctrl_info(ctrl, " Power Controller : %3s\n",
928 POWER_CTRL(ctrl) ? "yes" : "no");
929 ctrl_info(ctrl, " MRL Sensor : %3s\n",
930 MRL_SENS(ctrl) ? "yes" : "no");
931 ctrl_info(ctrl, " Attention Indicator : %3s\n",
932 ATTN_LED(ctrl) ? "yes" : "no");
933 ctrl_info(ctrl, " Power Indicator : %3s\n",
934 PWR_LED(ctrl) ? "yes" : "no");
935 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n",
936 HP_SUPR_RM(ctrl) ? "yes" : "no");
937 ctrl_info(ctrl, " EMI Present : %3s\n",
938 EMI(ctrl) ? "yes" : "no");
939 ctrl_info(ctrl, " Command Completed : %3s\n",
940 NO_CMD_CMPL(ctrl) ? "no" : "yes");
941 pciehp_readw(ctrl, PCI_EXP_SLTSTA, ®16);
942 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
943 pciehp_readw(ctrl, PCI_EXP_SLTCTL, ®16);
944 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
945}
946
947struct controller *pcie_init(struct pcie_device *dev)
948{
949 struct controller *ctrl;
950 u32 slot_cap, link_cap;
951 struct pci_dev *pdev = dev->port;
952
953 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
954 if (!ctrl) {
955 dev_err(&dev->device, "%s: Out of memory\n", __func__);
956 goto abort;
957 }
958 ctrl->pcie = dev;
959 if (!pci_pcie_cap(pdev)) {
960 ctrl_err(ctrl, "Cannot find PCI Express capability\n");
961 goto abort_ctrl;
962 }
963 if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) {
964 ctrl_err(ctrl, "Cannot read SLOTCAP register\n");
965 goto abort_ctrl;
966 }
967
968 ctrl->slot_cap = slot_cap;
969 mutex_init(&ctrl->ctrl_lock);
970 init_waitqueue_head(&ctrl->queue);
971 dbg_ctrl(ctrl);
972 /*
973 * Controller doesn't notify of command completion if the "No
974 * Command Completed Support" bit is set in Slot Capability
975 * register or the controller supports none of power
976 * controller, attention led, power led and EMI.
977 */
978 if (NO_CMD_CMPL(ctrl) ||
979 !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
980 ctrl->no_cmd_complete = 1;
981
982 /* Check if Data Link Layer Link Active Reporting is implemented */
983 if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) {
984 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
985 goto abort_ctrl;
986 }
987 if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {
988 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
989 ctrl->link_active_reporting = 1;
990 }
991
992 /* Clear all remaining event bits in Slot Status register */
993 if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f))
994 goto abort_ctrl;
995
996 /* Disable sotfware notification */
997 pcie_disable_notification(ctrl);
998
999 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
1000 pdev->vendor, pdev->device, pdev->subsystem_vendor,
1001 pdev->subsystem_device);
1002
1003 if (pcie_init_slot(ctrl))
1004 goto abort_ctrl;
1005
1006 return ctrl;
1007
1008abort_ctrl:
1009 kfree(ctrl);
1010abort:
1011 return NULL;
1012}
1013
1014void pciehp_release_ctrl(struct controller *ctrl)
1015{
1016 pcie_shutdown_notification(ctrl);
1017 pcie_cleanup_slot(ctrl);
1018 kfree(ctrl);
1019}
1/*
2 * PCI Express PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/signal.h>
34#include <linux/jiffies.h>
35#include <linux/timer.h>
36#include <linux/pci.h>
37#include <linux/interrupt.h>
38#include <linux/time.h>
39#include <linux/slab.h>
40
41#include "../pci.h"
42#include "pciehp.h"
43
44static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
45{
46 return ctrl->pcie->port;
47}
48
49static irqreturn_t pcie_isr(int irq, void *dev_id);
50static void start_int_poll_timer(struct controller *ctrl, int sec);
51
52/* This is the interrupt polling timeout function. */
53static void int_poll_timeout(unsigned long data)
54{
55 struct controller *ctrl = (struct controller *)data;
56
57 /* Poll for interrupt events. regs == NULL => polling */
58 pcie_isr(0, ctrl);
59
60 init_timer(&ctrl->poll_timer);
61 if (!pciehp_poll_time)
62 pciehp_poll_time = 2; /* default polling interval is 2 sec */
63
64 start_int_poll_timer(ctrl, pciehp_poll_time);
65}
66
67/* This function starts the interrupt polling timer. */
68static void start_int_poll_timer(struct controller *ctrl, int sec)
69{
70 /* Clamp to sane value */
71 if ((sec <= 0) || (sec > 60))
72 sec = 2;
73
74 ctrl->poll_timer.function = &int_poll_timeout;
75 ctrl->poll_timer.data = (unsigned long)ctrl;
76 ctrl->poll_timer.expires = jiffies + sec * HZ;
77 add_timer(&ctrl->poll_timer);
78}
79
80static inline int pciehp_request_irq(struct controller *ctrl)
81{
82 int retval, irq = ctrl->pcie->irq;
83
84 /* Install interrupt polling timer. Start with 10 sec delay */
85 if (pciehp_poll_mode) {
86 init_timer(&ctrl->poll_timer);
87 start_int_poll_timer(ctrl, 10);
88 return 0;
89 }
90
91 /* Installs the interrupt handler */
92 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
93 if (retval)
94 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
95 irq);
96 return retval;
97}
98
99static inline void pciehp_free_irq(struct controller *ctrl)
100{
101 if (pciehp_poll_mode)
102 del_timer_sync(&ctrl->poll_timer);
103 else
104 free_irq(ctrl->pcie->irq, ctrl);
105}
106
107static int pcie_poll_cmd(struct controller *ctrl, int timeout)
108{
109 struct pci_dev *pdev = ctrl_dev(ctrl);
110 u16 slot_status;
111
112 while (true) {
113 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
114 if (slot_status == (u16) ~0) {
115 ctrl_info(ctrl, "%s: no response from device\n",
116 __func__);
117 return 0;
118 }
119
120 if (slot_status & PCI_EXP_SLTSTA_CC) {
121 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
122 PCI_EXP_SLTSTA_CC);
123 return 1;
124 }
125 if (timeout < 0)
126 break;
127 msleep(10);
128 timeout -= 10;
129 }
130 return 0; /* timeout */
131}
132
133static void pcie_wait_cmd(struct controller *ctrl)
134{
135 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
136 unsigned long duration = msecs_to_jiffies(msecs);
137 unsigned long cmd_timeout = ctrl->cmd_started + duration;
138 unsigned long now, timeout;
139 int rc;
140
141 /*
142 * If the controller does not generate notifications for command
143 * completions, we never need to wait between writes.
144 */
145 if (NO_CMD_CMPL(ctrl))
146 return;
147
148 if (!ctrl->cmd_busy)
149 return;
150
151 /*
152 * Even if the command has already timed out, we want to call
153 * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
154 */
155 now = jiffies;
156 if (time_before_eq(cmd_timeout, now))
157 timeout = 1;
158 else
159 timeout = cmd_timeout - now;
160
161 if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
162 ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
163 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
164 else
165 rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout));
166
167 /*
168 * Controllers with errata like Intel CF118 don't generate
169 * completion notifications unless the power/indicator/interlock
170 * control bits are changed. On such controllers, we'll emit this
171 * timeout message when we wait for completion of commands that
172 * don't change those bits, e.g., commands that merely enable
173 * interrupts.
174 */
175 if (!rc)
176 ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
177 ctrl->slot_ctrl,
178 jiffies_to_msecs(jiffies - ctrl->cmd_started));
179}
180
181static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
182 u16 mask, bool wait)
183{
184 struct pci_dev *pdev = ctrl_dev(ctrl);
185 u16 slot_ctrl;
186
187 mutex_lock(&ctrl->ctrl_lock);
188
189 /*
190 * Always wait for any previous command that might still be in progress
191 */
192 pcie_wait_cmd(ctrl);
193
194 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
195 if (slot_ctrl == (u16) ~0) {
196 ctrl_info(ctrl, "%s: no response from device\n", __func__);
197 goto out;
198 }
199
200 slot_ctrl &= ~mask;
201 slot_ctrl |= (cmd & mask);
202 ctrl->cmd_busy = 1;
203 smp_mb();
204 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
205 ctrl->cmd_started = jiffies;
206 ctrl->slot_ctrl = slot_ctrl;
207
208 /*
209 * Optionally wait for the hardware to be ready for a new command,
210 * indicating completion of the above issued command.
211 */
212 if (wait)
213 pcie_wait_cmd(ctrl);
214
215out:
216 mutex_unlock(&ctrl->ctrl_lock);
217}
218
219/**
220 * pcie_write_cmd - Issue controller command
221 * @ctrl: controller to which the command is issued
222 * @cmd: command value written to slot control register
223 * @mask: bitmask of slot control register to be modified
224 */
225static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
226{
227 pcie_do_write_cmd(ctrl, cmd, mask, true);
228}
229
230/* Same as above without waiting for the hardware to latch */
231static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask)
232{
233 pcie_do_write_cmd(ctrl, cmd, mask, false);
234}
235
236bool pciehp_check_link_active(struct controller *ctrl)
237{
238 struct pci_dev *pdev = ctrl_dev(ctrl);
239 u16 lnk_status;
240 bool ret;
241
242 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
243 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
244
245 if (ret)
246 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
247
248 return ret;
249}
250
251static void __pcie_wait_link_active(struct controller *ctrl, bool active)
252{
253 int timeout = 1000;
254
255 if (pciehp_check_link_active(ctrl) == active)
256 return;
257 while (timeout > 0) {
258 msleep(10);
259 timeout -= 10;
260 if (pciehp_check_link_active(ctrl) == active)
261 return;
262 }
263 ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n",
264 active ? "set" : "cleared");
265}
266
267static void pcie_wait_link_active(struct controller *ctrl)
268{
269 __pcie_wait_link_active(ctrl, true);
270}
271
272static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
273{
274 u32 l;
275 int count = 0;
276 int delay = 1000, step = 20;
277 bool found = false;
278
279 do {
280 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
281 count++;
282
283 if (found)
284 break;
285
286 msleep(step);
287 delay -= step;
288 } while (delay > 0);
289
290 if (count > 1 && pciehp_debug)
291 printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
292 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
293 PCI_FUNC(devfn), count, step, l);
294
295 return found;
296}
297
298int pciehp_check_link_status(struct controller *ctrl)
299{
300 struct pci_dev *pdev = ctrl_dev(ctrl);
301 bool found;
302 u16 lnk_status;
303
304 /*
305 * Data Link Layer Link Active Reporting must be capable for
306 * hot-plug capable downstream port. But old controller might
307 * not implement it. In this case, we wait for 1000 ms.
308 */
309 if (ctrl->link_active_reporting)
310 pcie_wait_link_active(ctrl);
311 else
312 msleep(1000);
313
314 /* wait 100ms before read pci conf, and try in 1s */
315 msleep(100);
316 found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
317 PCI_DEVFN(0, 0));
318
319 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
320 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
321 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
322 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
323 ctrl_err(ctrl, "link training error: status %#06x\n",
324 lnk_status);
325 return -1;
326 }
327
328 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
329
330 if (!found)
331 return -1;
332
333 return 0;
334}
335
336static int __pciehp_link_set(struct controller *ctrl, bool enable)
337{
338 struct pci_dev *pdev = ctrl_dev(ctrl);
339 u16 lnk_ctrl;
340
341 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
342
343 if (enable)
344 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
345 else
346 lnk_ctrl |= PCI_EXP_LNKCTL_LD;
347
348 pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
349 ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
350 return 0;
351}
352
353static int pciehp_link_enable(struct controller *ctrl)
354{
355 return __pciehp_link_set(ctrl, true);
356}
357
358void pciehp_get_attention_status(struct slot *slot, u8 *status)
359{
360 struct controller *ctrl = slot->ctrl;
361 struct pci_dev *pdev = ctrl_dev(ctrl);
362 u16 slot_ctrl;
363
364 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
365 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
366 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
367
368 switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
369 case PCI_EXP_SLTCTL_ATTN_IND_ON:
370 *status = 1; /* On */
371 break;
372 case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
373 *status = 2; /* Blink */
374 break;
375 case PCI_EXP_SLTCTL_ATTN_IND_OFF:
376 *status = 0; /* Off */
377 break;
378 default:
379 *status = 0xFF;
380 break;
381 }
382}
383
384void pciehp_get_power_status(struct slot *slot, u8 *status)
385{
386 struct controller *ctrl = slot->ctrl;
387 struct pci_dev *pdev = ctrl_dev(ctrl);
388 u16 slot_ctrl;
389
390 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
391 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
392 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
393
394 switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
395 case PCI_EXP_SLTCTL_PWR_ON:
396 *status = 1; /* On */
397 break;
398 case PCI_EXP_SLTCTL_PWR_OFF:
399 *status = 0; /* Off */
400 break;
401 default:
402 *status = 0xFF;
403 break;
404 }
405}
406
407void pciehp_get_latch_status(struct slot *slot, u8 *status)
408{
409 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
410 u16 slot_status;
411
412 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
413 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
414}
415
416void pciehp_get_adapter_status(struct slot *slot, u8 *status)
417{
418 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
419 u16 slot_status;
420
421 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
422 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
423}
424
425int pciehp_query_power_fault(struct slot *slot)
426{
427 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
428 u16 slot_status;
429
430 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
431 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
432}
433
434void pciehp_set_attention_status(struct slot *slot, u8 value)
435{
436 struct controller *ctrl = slot->ctrl;
437 u16 slot_cmd;
438
439 if (!ATTN_LED(ctrl))
440 return;
441
442 switch (value) {
443 case 0: /* turn off */
444 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF;
445 break;
446 case 1: /* turn on */
447 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON;
448 break;
449 case 2: /* turn blink */
450 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK;
451 break;
452 default:
453 return;
454 }
455 pcie_write_cmd_nowait(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
456 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
457 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
458}
459
460void pciehp_green_led_on(struct slot *slot)
461{
462 struct controller *ctrl = slot->ctrl;
463
464 if (!PWR_LED(ctrl))
465 return;
466
467 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON,
468 PCI_EXP_SLTCTL_PIC);
469 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
470 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
471 PCI_EXP_SLTCTL_PWR_IND_ON);
472}
473
474void pciehp_green_led_off(struct slot *slot)
475{
476 struct controller *ctrl = slot->ctrl;
477
478 if (!PWR_LED(ctrl))
479 return;
480
481 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
482 PCI_EXP_SLTCTL_PIC);
483 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
484 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
485 PCI_EXP_SLTCTL_PWR_IND_OFF);
486}
487
488void pciehp_green_led_blink(struct slot *slot)
489{
490 struct controller *ctrl = slot->ctrl;
491
492 if (!PWR_LED(ctrl))
493 return;
494
495 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK,
496 PCI_EXP_SLTCTL_PIC);
497 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
498 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
499 PCI_EXP_SLTCTL_PWR_IND_BLINK);
500}
501
502int pciehp_power_on_slot(struct slot *slot)
503{
504 struct controller *ctrl = slot->ctrl;
505 struct pci_dev *pdev = ctrl_dev(ctrl);
506 u16 slot_status;
507 int retval;
508
509 /* Clear sticky power-fault bit from previous power failures */
510 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
511 if (slot_status & PCI_EXP_SLTSTA_PFD)
512 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
513 PCI_EXP_SLTSTA_PFD);
514 ctrl->power_fault_detected = 0;
515
516 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
517 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
518 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
519 PCI_EXP_SLTCTL_PWR_ON);
520
521 retval = pciehp_link_enable(ctrl);
522 if (retval)
523 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
524
525 return retval;
526}
527
528void pciehp_power_off_slot(struct slot *slot)
529{
530 struct controller *ctrl = slot->ctrl;
531
532 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
533 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
534 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
535 PCI_EXP_SLTCTL_PWR_OFF);
536}
537
538static irqreturn_t pcie_isr(int irq, void *dev_id)
539{
540 struct controller *ctrl = (struct controller *)dev_id;
541 struct pci_dev *pdev = ctrl_dev(ctrl);
542 struct pci_bus *subordinate = pdev->subordinate;
543 struct pci_dev *dev;
544 struct slot *slot = ctrl->slot;
545 u16 detected, intr_loc;
546 u8 present;
547 bool link;
548
549 /*
550 * In order to guarantee that all interrupt events are
551 * serviced, we need to re-inspect Slot Status register after
552 * clearing what is presumed to be the last pending interrupt.
553 */
554 intr_loc = 0;
555 do {
556 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &detected);
557 if (detected == (u16) ~0) {
558 ctrl_info(ctrl, "%s: no response from device\n",
559 __func__);
560 return IRQ_HANDLED;
561 }
562
563 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
564 PCI_EXP_SLTSTA_PDC |
565 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC);
566 detected &= ~intr_loc;
567 intr_loc |= detected;
568 if (!intr_loc)
569 return IRQ_NONE;
570 if (detected)
571 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
572 intr_loc);
573 } while (detected);
574
575 ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", intr_loc);
576
577 /* Check Command Complete Interrupt Pending */
578 if (intr_loc & PCI_EXP_SLTSTA_CC) {
579 ctrl->cmd_busy = 0;
580 smp_mb();
581 wake_up(&ctrl->queue);
582 }
583
584 if (subordinate) {
585 list_for_each_entry(dev, &subordinate->devices, bus_list) {
586 if (dev->ignore_hotplug) {
587 ctrl_dbg(ctrl, "ignoring hotplug event %#06x (%s requested no hotplug)\n",
588 intr_loc, pci_name(dev));
589 return IRQ_HANDLED;
590 }
591 }
592 }
593
594 if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
595 return IRQ_HANDLED;
596
597 /* Check Attention Button Pressed */
598 if (intr_loc & PCI_EXP_SLTSTA_ABP) {
599 ctrl_info(ctrl, "Button pressed on Slot(%s)\n",
600 slot_name(slot));
601 pciehp_queue_interrupt_event(slot, INT_BUTTON_PRESS);
602 }
603
604 /* Check Presence Detect Changed */
605 if (intr_loc & PCI_EXP_SLTSTA_PDC) {
606 pciehp_get_adapter_status(slot, &present);
607 ctrl_info(ctrl, "Card %spresent on Slot(%s)\n",
608 present ? "" : "not ", slot_name(slot));
609 pciehp_queue_interrupt_event(slot, present ? INT_PRESENCE_ON :
610 INT_PRESENCE_OFF);
611 }
612
613 /* Check Power Fault Detected */
614 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
615 ctrl->power_fault_detected = 1;
616 ctrl_err(ctrl, "Power fault on slot %s\n", slot_name(slot));
617 pciehp_queue_interrupt_event(slot, INT_POWER_FAULT);
618 }
619
620 if (intr_loc & PCI_EXP_SLTSTA_DLLSC) {
621 link = pciehp_check_link_active(ctrl);
622 ctrl_info(ctrl, "slot(%s): Link %s event\n",
623 slot_name(slot), link ? "Up" : "Down");
624 pciehp_queue_interrupt_event(slot, link ? INT_LINK_UP :
625 INT_LINK_DOWN);
626 }
627
628 return IRQ_HANDLED;
629}
630
631void pcie_enable_notification(struct controller *ctrl)
632{
633 u16 cmd, mask;
634
635 /*
636 * TBD: Power fault detected software notification support.
637 *
638 * Power fault detected software notification is not enabled
639 * now, because it caused power fault detected interrupt storm
640 * on some machines. On those machines, power fault detected
641 * bit in the slot status register was set again immediately
642 * when it is cleared in the interrupt service routine, and
643 * next power fault detected interrupt was notified again.
644 */
645
646 /*
647 * Always enable link events: thus link-up and link-down shall
648 * always be treated as hotplug and unplug respectively. Enable
649 * presence detect only if Attention Button is not present.
650 */
651 cmd = PCI_EXP_SLTCTL_DLLSCE;
652 if (ATTN_BUTTN(ctrl))
653 cmd |= PCI_EXP_SLTCTL_ABPE;
654 else
655 cmd |= PCI_EXP_SLTCTL_PDCE;
656 if (!pciehp_poll_mode)
657 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
658
659 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
660 PCI_EXP_SLTCTL_PFDE |
661 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
662 PCI_EXP_SLTCTL_DLLSCE);
663
664 pcie_write_cmd_nowait(ctrl, cmd, mask);
665 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
666 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
667}
668
669static void pcie_disable_notification(struct controller *ctrl)
670{
671 u16 mask;
672
673 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
674 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
675 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
676 PCI_EXP_SLTCTL_DLLSCE);
677 pcie_write_cmd(ctrl, 0, mask);
678 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
679 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
680}
681
682/*
683 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
684 * bus reset of the bridge, but at the same time we want to ensure that it is
685 * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
686 * disable link state notification and presence detection change notification
687 * momentarily, if we see that they could interfere. Also, clear any spurious
688 * events after.
689 */
690int pciehp_reset_slot(struct slot *slot, int probe)
691{
692 struct controller *ctrl = slot->ctrl;
693 struct pci_dev *pdev = ctrl_dev(ctrl);
694 u16 stat_mask = 0, ctrl_mask = 0;
695
696 if (probe)
697 return 0;
698
699 if (!ATTN_BUTTN(ctrl)) {
700 ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
701 stat_mask |= PCI_EXP_SLTSTA_PDC;
702 }
703 ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
704 stat_mask |= PCI_EXP_SLTSTA_DLLSC;
705
706 pcie_write_cmd(ctrl, 0, ctrl_mask);
707 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
708 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
709 if (pciehp_poll_mode)
710 del_timer_sync(&ctrl->poll_timer);
711
712 pci_reset_bridge_secondary_bus(ctrl->pcie->port);
713
714 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
715 pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
716 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
717 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
718 if (pciehp_poll_mode)
719 int_poll_timeout(ctrl->poll_timer.data);
720
721 return 0;
722}
723
724int pcie_init_notification(struct controller *ctrl)
725{
726 if (pciehp_request_irq(ctrl))
727 return -1;
728 pcie_enable_notification(ctrl);
729 ctrl->notification_enabled = 1;
730 return 0;
731}
732
733static void pcie_shutdown_notification(struct controller *ctrl)
734{
735 if (ctrl->notification_enabled) {
736 pcie_disable_notification(ctrl);
737 pciehp_free_irq(ctrl);
738 ctrl->notification_enabled = 0;
739 }
740}
741
742static int pcie_init_slot(struct controller *ctrl)
743{
744 struct slot *slot;
745
746 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
747 if (!slot)
748 return -ENOMEM;
749
750 slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl));
751 if (!slot->wq)
752 goto abort;
753
754 slot->ctrl = ctrl;
755 mutex_init(&slot->lock);
756 mutex_init(&slot->hotplug_lock);
757 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
758 ctrl->slot = slot;
759 return 0;
760abort:
761 kfree(slot);
762 return -ENOMEM;
763}
764
765static void pcie_cleanup_slot(struct controller *ctrl)
766{
767 struct slot *slot = ctrl->slot;
768 cancel_delayed_work(&slot->work);
769 destroy_workqueue(slot->wq);
770 kfree(slot);
771}
772
773static inline void dbg_ctrl(struct controller *ctrl)
774{
775 struct pci_dev *pdev = ctrl->pcie->port;
776 u16 reg16;
777
778 if (!pciehp_debug)
779 return;
780
781 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
782 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16);
783 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
784 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16);
785 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
786}
787
788#define FLAG(x, y) (((x) & (y)) ? '+' : '-')
789
790struct controller *pcie_init(struct pcie_device *dev)
791{
792 struct controller *ctrl;
793 u32 slot_cap, link_cap;
794 struct pci_dev *pdev = dev->port;
795
796 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
797 if (!ctrl) {
798 dev_err(&dev->device, "%s: Out of memory\n", __func__);
799 goto abort;
800 }
801 ctrl->pcie = dev;
802 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
803 ctrl->slot_cap = slot_cap;
804 mutex_init(&ctrl->ctrl_lock);
805 init_waitqueue_head(&ctrl->queue);
806 dbg_ctrl(ctrl);
807
808 /* Check if Data Link Layer Link Active Reporting is implemented */
809 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
810 if (link_cap & PCI_EXP_LNKCAP_DLLLARC)
811 ctrl->link_active_reporting = 1;
812
813 /* Clear all remaining event bits in Slot Status register */
814 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
815 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
816 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
817 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC);
818
819 ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c LLActRep%c\n",
820 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
821 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
822 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
823 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
824 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
825 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
826 FLAG(slot_cap, PCI_EXP_SLTCAP_HPC),
827 FLAG(slot_cap, PCI_EXP_SLTCAP_HPS),
828 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
829 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
830 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC));
831
832 if (pcie_init_slot(ctrl))
833 goto abort_ctrl;
834
835 return ctrl;
836
837abort_ctrl:
838 kfree(ctrl);
839abort:
840 return NULL;
841}
842
843void pciehp_release_ctrl(struct controller *ctrl)
844{
845 pcie_shutdown_notification(ctrl);
846 pcie_cleanup_slot(ctrl);
847 kfree(ctrl);
848}