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1#include <linux/kernel.h>
2#include <linux/sched.h>
3#include <linux/init.h>
4#include <linux/module.h>
5#include <linux/timer.h>
6#include <linux/acpi_pmtmr.h>
7#include <linux/cpufreq.h>
8#include <linux/delay.h>
9#include <linux/clocksource.h>
10#include <linux/percpu.h>
11#include <linux/timex.h>
12
13#include <asm/hpet.h>
14#include <asm/timer.h>
15#include <asm/vgtod.h>
16#include <asm/time.h>
17#include <asm/delay.h>
18#include <asm/hypervisor.h>
19#include <asm/nmi.h>
20#include <asm/x86_init.h>
21
22unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
23EXPORT_SYMBOL(cpu_khz);
24
25unsigned int __read_mostly tsc_khz;
26EXPORT_SYMBOL(tsc_khz);
27
28/*
29 * TSC can be unstable due to cpufreq or due to unsynced TSCs
30 */
31static int __read_mostly tsc_unstable;
32
33/* native_sched_clock() is called before tsc_init(), so
34 we must start with the TSC soft disabled to prevent
35 erroneous rdtsc usage on !cpu_has_tsc processors */
36static int __read_mostly tsc_disabled = -1;
37
38int tsc_clocksource_reliable;
39/*
40 * Scheduler clock - returns current time in nanosec units.
41 */
42u64 native_sched_clock(void)
43{
44 u64 this_offset;
45
46 /*
47 * Fall back to jiffies if there's no TSC available:
48 * ( But note that we still use it if the TSC is marked
49 * unstable. We do this because unlike Time Of Day,
50 * the scheduler clock tolerates small errors and it's
51 * very important for it to be as fast as the platform
52 * can achieve it. )
53 */
54 if (unlikely(tsc_disabled)) {
55 /* No locking but a rare wrong value is not a big deal: */
56 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
57 }
58
59 /* read the Time Stamp Counter: */
60 rdtscll(this_offset);
61
62 /* return the value in ns */
63 return __cycles_2_ns(this_offset);
64}
65
66/* We need to define a real function for sched_clock, to override the
67 weak default version */
68#ifdef CONFIG_PARAVIRT
69unsigned long long sched_clock(void)
70{
71 return paravirt_sched_clock();
72}
73#else
74unsigned long long
75sched_clock(void) __attribute__((alias("native_sched_clock")));
76#endif
77
78int check_tsc_unstable(void)
79{
80 return tsc_unstable;
81}
82EXPORT_SYMBOL_GPL(check_tsc_unstable);
83
84#ifdef CONFIG_X86_TSC
85int __init notsc_setup(char *str)
86{
87 printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, "
88 "cannot disable TSC completely.\n");
89 tsc_disabled = 1;
90 return 1;
91}
92#else
93/*
94 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
95 * in cpu/common.c
96 */
97int __init notsc_setup(char *str)
98{
99 setup_clear_cpu_cap(X86_FEATURE_TSC);
100 return 1;
101}
102#endif
103
104__setup("notsc", notsc_setup);
105
106static int no_sched_irq_time;
107
108static int __init tsc_setup(char *str)
109{
110 if (!strcmp(str, "reliable"))
111 tsc_clocksource_reliable = 1;
112 if (!strncmp(str, "noirqtime", 9))
113 no_sched_irq_time = 1;
114 return 1;
115}
116
117__setup("tsc=", tsc_setup);
118
119#define MAX_RETRIES 5
120#define SMI_TRESHOLD 50000
121
122/*
123 * Read TSC and the reference counters. Take care of SMI disturbance
124 */
125static u64 tsc_read_refs(u64 *p, int hpet)
126{
127 u64 t1, t2;
128 int i;
129
130 for (i = 0; i < MAX_RETRIES; i++) {
131 t1 = get_cycles();
132 if (hpet)
133 *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
134 else
135 *p = acpi_pm_read_early();
136 t2 = get_cycles();
137 if ((t2 - t1) < SMI_TRESHOLD)
138 return t2;
139 }
140 return ULLONG_MAX;
141}
142
143/*
144 * Calculate the TSC frequency from HPET reference
145 */
146static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
147{
148 u64 tmp;
149
150 if (hpet2 < hpet1)
151 hpet2 += 0x100000000ULL;
152 hpet2 -= hpet1;
153 tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
154 do_div(tmp, 1000000);
155 do_div(deltatsc, tmp);
156
157 return (unsigned long) deltatsc;
158}
159
160/*
161 * Calculate the TSC frequency from PMTimer reference
162 */
163static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
164{
165 u64 tmp;
166
167 if (!pm1 && !pm2)
168 return ULONG_MAX;
169
170 if (pm2 < pm1)
171 pm2 += (u64)ACPI_PM_OVRRUN;
172 pm2 -= pm1;
173 tmp = pm2 * 1000000000LL;
174 do_div(tmp, PMTMR_TICKS_PER_SEC);
175 do_div(deltatsc, tmp);
176
177 return (unsigned long) deltatsc;
178}
179
180#define CAL_MS 10
181#define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS))
182#define CAL_PIT_LOOPS 1000
183
184#define CAL2_MS 50
185#define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS))
186#define CAL2_PIT_LOOPS 5000
187
188
189/*
190 * Try to calibrate the TSC against the Programmable
191 * Interrupt Timer and return the frequency of the TSC
192 * in kHz.
193 *
194 * Return ULONG_MAX on failure to calibrate.
195 */
196static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
197{
198 u64 tsc, t1, t2, delta;
199 unsigned long tscmin, tscmax;
200 int pitcnt;
201
202 /* Set the Gate high, disable speaker */
203 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
204
205 /*
206 * Setup CTC channel 2* for mode 0, (interrupt on terminal
207 * count mode), binary count. Set the latch register to 50ms
208 * (LSB then MSB) to begin countdown.
209 */
210 outb(0xb0, 0x43);
211 outb(latch & 0xff, 0x42);
212 outb(latch >> 8, 0x42);
213
214 tsc = t1 = t2 = get_cycles();
215
216 pitcnt = 0;
217 tscmax = 0;
218 tscmin = ULONG_MAX;
219 while ((inb(0x61) & 0x20) == 0) {
220 t2 = get_cycles();
221 delta = t2 - tsc;
222 tsc = t2;
223 if ((unsigned long) delta < tscmin)
224 tscmin = (unsigned int) delta;
225 if ((unsigned long) delta > tscmax)
226 tscmax = (unsigned int) delta;
227 pitcnt++;
228 }
229
230 /*
231 * Sanity checks:
232 *
233 * If we were not able to read the PIT more than loopmin
234 * times, then we have been hit by a massive SMI
235 *
236 * If the maximum is 10 times larger than the minimum,
237 * then we got hit by an SMI as well.
238 */
239 if (pitcnt < loopmin || tscmax > 10 * tscmin)
240 return ULONG_MAX;
241
242 /* Calculate the PIT value */
243 delta = t2 - t1;
244 do_div(delta, ms);
245 return delta;
246}
247
248/*
249 * This reads the current MSB of the PIT counter, and
250 * checks if we are running on sufficiently fast and
251 * non-virtualized hardware.
252 *
253 * Our expectations are:
254 *
255 * - the PIT is running at roughly 1.19MHz
256 *
257 * - each IO is going to take about 1us on real hardware,
258 * but we allow it to be much faster (by a factor of 10) or
259 * _slightly_ slower (ie we allow up to a 2us read+counter
260 * update - anything else implies a unacceptably slow CPU
261 * or PIT for the fast calibration to work.
262 *
263 * - with 256 PIT ticks to read the value, we have 214us to
264 * see the same MSB (and overhead like doing a single TSC
265 * read per MSB value etc).
266 *
267 * - We're doing 2 reads per loop (LSB, MSB), and we expect
268 * them each to take about a microsecond on real hardware.
269 * So we expect a count value of around 100. But we'll be
270 * generous, and accept anything over 50.
271 *
272 * - if the PIT is stuck, and we see *many* more reads, we
273 * return early (and the next caller of pit_expect_msb()
274 * then consider it a failure when they don't see the
275 * next expected value).
276 *
277 * These expectations mean that we know that we have seen the
278 * transition from one expected value to another with a fairly
279 * high accuracy, and we didn't miss any events. We can thus
280 * use the TSC value at the transitions to calculate a pretty
281 * good value for the TSC frequencty.
282 */
283static inline int pit_verify_msb(unsigned char val)
284{
285 /* Ignore LSB */
286 inb(0x42);
287 return inb(0x42) == val;
288}
289
290static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
291{
292 int count;
293 u64 tsc = 0, prev_tsc = 0;
294
295 for (count = 0; count < 50000; count++) {
296 if (!pit_verify_msb(val))
297 break;
298 prev_tsc = tsc;
299 tsc = get_cycles();
300 }
301 *deltap = get_cycles() - prev_tsc;
302 *tscp = tsc;
303
304 /*
305 * We require _some_ success, but the quality control
306 * will be based on the error terms on the TSC values.
307 */
308 return count > 5;
309}
310
311/*
312 * How many MSB values do we want to see? We aim for
313 * a maximum error rate of 500ppm (in practice the
314 * real error is much smaller), but refuse to spend
315 * more than 50ms on it.
316 */
317#define MAX_QUICK_PIT_MS 50
318#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
319
320static unsigned long quick_pit_calibrate(void)
321{
322 int i;
323 u64 tsc, delta;
324 unsigned long d1, d2;
325
326 /* Set the Gate high, disable speaker */
327 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
328
329 /*
330 * Counter 2, mode 0 (one-shot), binary count
331 *
332 * NOTE! Mode 2 decrements by two (and then the
333 * output is flipped each time, giving the same
334 * final output frequency as a decrement-by-one),
335 * so mode 0 is much better when looking at the
336 * individual counts.
337 */
338 outb(0xb0, 0x43);
339
340 /* Start at 0xffff */
341 outb(0xff, 0x42);
342 outb(0xff, 0x42);
343
344 /*
345 * The PIT starts counting at the next edge, so we
346 * need to delay for a microsecond. The easiest way
347 * to do that is to just read back the 16-bit counter
348 * once from the PIT.
349 */
350 pit_verify_msb(0);
351
352 if (pit_expect_msb(0xff, &tsc, &d1)) {
353 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
354 if (!pit_expect_msb(0xff-i, &delta, &d2))
355 break;
356
357 /*
358 * Iterate until the error is less than 500 ppm
359 */
360 delta -= tsc;
361 if (d1+d2 >= delta >> 11)
362 continue;
363
364 /*
365 * Check the PIT one more time to verify that
366 * all TSC reads were stable wrt the PIT.
367 *
368 * This also guarantees serialization of the
369 * last cycle read ('d2') in pit_expect_msb.
370 */
371 if (!pit_verify_msb(0xfe - i))
372 break;
373 goto success;
374 }
375 }
376 printk("Fast TSC calibration failed\n");
377 return 0;
378
379success:
380 /*
381 * Ok, if we get here, then we've seen the
382 * MSB of the PIT decrement 'i' times, and the
383 * error has shrunk to less than 500 ppm.
384 *
385 * As a result, we can depend on there not being
386 * any odd delays anywhere, and the TSC reads are
387 * reliable (within the error).
388 *
389 * kHz = ticks / time-in-seconds / 1000;
390 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
391 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
392 */
393 delta *= PIT_TICK_RATE;
394 do_div(delta, i*256*1000);
395 printk("Fast TSC calibration using PIT\n");
396 return delta;
397}
398
399/**
400 * native_calibrate_tsc - calibrate the tsc on boot
401 */
402unsigned long native_calibrate_tsc(void)
403{
404 u64 tsc1, tsc2, delta, ref1, ref2;
405 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
406 unsigned long flags, latch, ms, fast_calibrate;
407 int hpet = is_hpet_enabled(), i, loopmin;
408
409 local_irq_save(flags);
410 fast_calibrate = quick_pit_calibrate();
411 local_irq_restore(flags);
412 if (fast_calibrate)
413 return fast_calibrate;
414
415 /*
416 * Run 5 calibration loops to get the lowest frequency value
417 * (the best estimate). We use two different calibration modes
418 * here:
419 *
420 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
421 * load a timeout of 50ms. We read the time right after we
422 * started the timer and wait until the PIT count down reaches
423 * zero. In each wait loop iteration we read the TSC and check
424 * the delta to the previous read. We keep track of the min
425 * and max values of that delta. The delta is mostly defined
426 * by the IO time of the PIT access, so we can detect when a
427 * SMI/SMM disturbance happened between the two reads. If the
428 * maximum time is significantly larger than the minimum time,
429 * then we discard the result and have another try.
430 *
431 * 2) Reference counter. If available we use the HPET or the
432 * PMTIMER as a reference to check the sanity of that value.
433 * We use separate TSC readouts and check inside of the
434 * reference read for a SMI/SMM disturbance. We dicard
435 * disturbed values here as well. We do that around the PIT
436 * calibration delay loop as we have to wait for a certain
437 * amount of time anyway.
438 */
439
440 /* Preset PIT loop values */
441 latch = CAL_LATCH;
442 ms = CAL_MS;
443 loopmin = CAL_PIT_LOOPS;
444
445 for (i = 0; i < 3; i++) {
446 unsigned long tsc_pit_khz;
447
448 /*
449 * Read the start value and the reference count of
450 * hpet/pmtimer when available. Then do the PIT
451 * calibration, which will take at least 50ms, and
452 * read the end value.
453 */
454 local_irq_save(flags);
455 tsc1 = tsc_read_refs(&ref1, hpet);
456 tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
457 tsc2 = tsc_read_refs(&ref2, hpet);
458 local_irq_restore(flags);
459
460 /* Pick the lowest PIT TSC calibration so far */
461 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
462
463 /* hpet or pmtimer available ? */
464 if (ref1 == ref2)
465 continue;
466
467 /* Check, whether the sampling was disturbed by an SMI */
468 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
469 continue;
470
471 tsc2 = (tsc2 - tsc1) * 1000000LL;
472 if (hpet)
473 tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
474 else
475 tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
476
477 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
478
479 /* Check the reference deviation */
480 delta = ((u64) tsc_pit_min) * 100;
481 do_div(delta, tsc_ref_min);
482
483 /*
484 * If both calibration results are inside a 10% window
485 * then we can be sure, that the calibration
486 * succeeded. We break out of the loop right away. We
487 * use the reference value, as it is more precise.
488 */
489 if (delta >= 90 && delta <= 110) {
490 printk(KERN_INFO
491 "TSC: PIT calibration matches %s. %d loops\n",
492 hpet ? "HPET" : "PMTIMER", i + 1);
493 return tsc_ref_min;
494 }
495
496 /*
497 * Check whether PIT failed more than once. This
498 * happens in virtualized environments. We need to
499 * give the virtual PC a slightly longer timeframe for
500 * the HPET/PMTIMER to make the result precise.
501 */
502 if (i == 1 && tsc_pit_min == ULONG_MAX) {
503 latch = CAL2_LATCH;
504 ms = CAL2_MS;
505 loopmin = CAL2_PIT_LOOPS;
506 }
507 }
508
509 /*
510 * Now check the results.
511 */
512 if (tsc_pit_min == ULONG_MAX) {
513 /* PIT gave no useful value */
514 printk(KERN_WARNING "TSC: Unable to calibrate against PIT\n");
515
516 /* We don't have an alternative source, disable TSC */
517 if (!hpet && !ref1 && !ref2) {
518 printk("TSC: No reference (HPET/PMTIMER) available\n");
519 return 0;
520 }
521
522 /* The alternative source failed as well, disable TSC */
523 if (tsc_ref_min == ULONG_MAX) {
524 printk(KERN_WARNING "TSC: HPET/PMTIMER calibration "
525 "failed.\n");
526 return 0;
527 }
528
529 /* Use the alternative source */
530 printk(KERN_INFO "TSC: using %s reference calibration\n",
531 hpet ? "HPET" : "PMTIMER");
532
533 return tsc_ref_min;
534 }
535
536 /* We don't have an alternative source, use the PIT calibration value */
537 if (!hpet && !ref1 && !ref2) {
538 printk(KERN_INFO "TSC: Using PIT calibration value\n");
539 return tsc_pit_min;
540 }
541
542 /* The alternative source failed, use the PIT calibration value */
543 if (tsc_ref_min == ULONG_MAX) {
544 printk(KERN_WARNING "TSC: HPET/PMTIMER calibration failed. "
545 "Using PIT calibration\n");
546 return tsc_pit_min;
547 }
548
549 /*
550 * The calibration values differ too much. In doubt, we use
551 * the PIT value as we know that there are PMTIMERs around
552 * running at double speed. At least we let the user know:
553 */
554 printk(KERN_WARNING "TSC: PIT calibration deviates from %s: %lu %lu.\n",
555 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
556 printk(KERN_INFO "TSC: Using PIT calibration value\n");
557 return tsc_pit_min;
558}
559
560int recalibrate_cpu_khz(void)
561{
562#ifndef CONFIG_SMP
563 unsigned long cpu_khz_old = cpu_khz;
564
565 if (cpu_has_tsc) {
566 tsc_khz = x86_platform.calibrate_tsc();
567 cpu_khz = tsc_khz;
568 cpu_data(0).loops_per_jiffy =
569 cpufreq_scale(cpu_data(0).loops_per_jiffy,
570 cpu_khz_old, cpu_khz);
571 return 0;
572 } else
573 return -ENODEV;
574#else
575 return -ENODEV;
576#endif
577}
578
579EXPORT_SYMBOL(recalibrate_cpu_khz);
580
581
582/* Accelerators for sched_clock()
583 * convert from cycles(64bits) => nanoseconds (64bits)
584 * basic equation:
585 * ns = cycles / (freq / ns_per_sec)
586 * ns = cycles * (ns_per_sec / freq)
587 * ns = cycles * (10^9 / (cpu_khz * 10^3))
588 * ns = cycles * (10^6 / cpu_khz)
589 *
590 * Then we use scaling math (suggested by george@mvista.com) to get:
591 * ns = cycles * (10^6 * SC / cpu_khz) / SC
592 * ns = cycles * cyc2ns_scale / SC
593 *
594 * And since SC is a constant power of two, we can convert the div
595 * into a shift.
596 *
597 * We can use khz divisor instead of mhz to keep a better precision, since
598 * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
599 * (mathieu.desnoyers@polymtl.ca)
600 *
601 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
602 */
603
604DEFINE_PER_CPU(unsigned long, cyc2ns);
605DEFINE_PER_CPU(unsigned long long, cyc2ns_offset);
606
607static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
608{
609 unsigned long long tsc_now, ns_now, *offset;
610 unsigned long flags, *scale;
611
612 local_irq_save(flags);
613 sched_clock_idle_sleep_event();
614
615 scale = &per_cpu(cyc2ns, cpu);
616 offset = &per_cpu(cyc2ns_offset, cpu);
617
618 rdtscll(tsc_now);
619 ns_now = __cycles_2_ns(tsc_now);
620
621 if (cpu_khz) {
622 *scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz;
623 *offset = ns_now - mult_frac(tsc_now, *scale,
624 (1UL << CYC2NS_SCALE_FACTOR));
625 }
626
627 sched_clock_idle_wakeup_event(0);
628 local_irq_restore(flags);
629}
630
631static unsigned long long cyc2ns_suspend;
632
633void tsc_save_sched_clock_state(void)
634{
635 if (!sched_clock_stable)
636 return;
637
638 cyc2ns_suspend = sched_clock();
639}
640
641/*
642 * Even on processors with invariant TSC, TSC gets reset in some the
643 * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
644 * arbitrary value (still sync'd across cpu's) during resume from such sleep
645 * states. To cope up with this, recompute the cyc2ns_offset for each cpu so
646 * that sched_clock() continues from the point where it was left off during
647 * suspend.
648 */
649void tsc_restore_sched_clock_state(void)
650{
651 unsigned long long offset;
652 unsigned long flags;
653 int cpu;
654
655 if (!sched_clock_stable)
656 return;
657
658 local_irq_save(flags);
659
660 __this_cpu_write(cyc2ns_offset, 0);
661 offset = cyc2ns_suspend - sched_clock();
662
663 for_each_possible_cpu(cpu)
664 per_cpu(cyc2ns_offset, cpu) = offset;
665
666 local_irq_restore(flags);
667}
668
669#ifdef CONFIG_CPU_FREQ
670
671/* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
672 * changes.
673 *
674 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
675 * not that important because current Opteron setups do not support
676 * scaling on SMP anyroads.
677 *
678 * Should fix up last_tsc too. Currently gettimeofday in the
679 * first tick after the change will be slightly wrong.
680 */
681
682static unsigned int ref_freq;
683static unsigned long loops_per_jiffy_ref;
684static unsigned long tsc_khz_ref;
685
686static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
687 void *data)
688{
689 struct cpufreq_freqs *freq = data;
690 unsigned long *lpj;
691
692 if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
693 return 0;
694
695 lpj = &boot_cpu_data.loops_per_jiffy;
696#ifdef CONFIG_SMP
697 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
698 lpj = &cpu_data(freq->cpu).loops_per_jiffy;
699#endif
700
701 if (!ref_freq) {
702 ref_freq = freq->old;
703 loops_per_jiffy_ref = *lpj;
704 tsc_khz_ref = tsc_khz;
705 }
706 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
707 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
708 (val == CPUFREQ_RESUMECHANGE)) {
709 *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
710
711 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
712 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
713 mark_tsc_unstable("cpufreq changes");
714 }
715
716 set_cyc2ns_scale(tsc_khz, freq->cpu);
717
718 return 0;
719}
720
721static struct notifier_block time_cpufreq_notifier_block = {
722 .notifier_call = time_cpufreq_notifier
723};
724
725static int __init cpufreq_tsc(void)
726{
727 if (!cpu_has_tsc)
728 return 0;
729 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
730 return 0;
731 cpufreq_register_notifier(&time_cpufreq_notifier_block,
732 CPUFREQ_TRANSITION_NOTIFIER);
733 return 0;
734}
735
736core_initcall(cpufreq_tsc);
737
738#endif /* CONFIG_CPU_FREQ */
739
740/* clocksource code */
741
742static struct clocksource clocksource_tsc;
743
744/*
745 * We compare the TSC to the cycle_last value in the clocksource
746 * structure to avoid a nasty time-warp. This can be observed in a
747 * very small window right after one CPU updated cycle_last under
748 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
749 * is smaller than the cycle_last reference value due to a TSC which
750 * is slighty behind. This delta is nowhere else observable, but in
751 * that case it results in a forward time jump in the range of hours
752 * due to the unsigned delta calculation of the time keeping core
753 * code, which is necessary to support wrapping clocksources like pm
754 * timer.
755 */
756static cycle_t read_tsc(struct clocksource *cs)
757{
758 cycle_t ret = (cycle_t)get_cycles();
759
760 return ret >= clocksource_tsc.cycle_last ?
761 ret : clocksource_tsc.cycle_last;
762}
763
764static void resume_tsc(struct clocksource *cs)
765{
766 clocksource_tsc.cycle_last = 0;
767}
768
769static struct clocksource clocksource_tsc = {
770 .name = "tsc",
771 .rating = 300,
772 .read = read_tsc,
773 .resume = resume_tsc,
774 .mask = CLOCKSOURCE_MASK(64),
775 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
776 CLOCK_SOURCE_MUST_VERIFY,
777#ifdef CONFIG_X86_64
778 .archdata = { .vclock_mode = VCLOCK_TSC },
779#endif
780};
781
782void mark_tsc_unstable(char *reason)
783{
784 if (!tsc_unstable) {
785 tsc_unstable = 1;
786 sched_clock_stable = 0;
787 disable_sched_clock_irqtime();
788 printk(KERN_INFO "Marking TSC unstable due to %s\n", reason);
789 /* Change only the rating, when not registered */
790 if (clocksource_tsc.mult)
791 clocksource_mark_unstable(&clocksource_tsc);
792 else {
793 clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE;
794 clocksource_tsc.rating = 0;
795 }
796 }
797}
798
799EXPORT_SYMBOL_GPL(mark_tsc_unstable);
800
801static void __init check_system_tsc_reliable(void)
802{
803#ifdef CONFIG_MGEODE_LX
804 /* RTSC counts during suspend */
805#define RTSC_SUSP 0x100
806 unsigned long res_low, res_high;
807
808 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
809 /* Geode_LX - the OLPC CPU has a very reliable TSC */
810 if (res_low & RTSC_SUSP)
811 tsc_clocksource_reliable = 1;
812#endif
813 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
814 tsc_clocksource_reliable = 1;
815}
816
817/*
818 * Make an educated guess if the TSC is trustworthy and synchronized
819 * over all CPUs.
820 */
821__cpuinit int unsynchronized_tsc(void)
822{
823 if (!cpu_has_tsc || tsc_unstable)
824 return 1;
825
826#ifdef CONFIG_SMP
827 if (apic_is_clustered_box())
828 return 1;
829#endif
830
831 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
832 return 0;
833
834 if (tsc_clocksource_reliable)
835 return 0;
836 /*
837 * Intel systems are normally all synchronized.
838 * Exceptions must mark TSC as unstable:
839 */
840 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
841 /* assume multi socket systems are not synchronized: */
842 if (num_possible_cpus() > 1)
843 return 1;
844 }
845
846 return 0;
847}
848
849
850static void tsc_refine_calibration_work(struct work_struct *work);
851static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work);
852/**
853 * tsc_refine_calibration_work - Further refine tsc freq calibration
854 * @work - ignored.
855 *
856 * This functions uses delayed work over a period of a
857 * second to further refine the TSC freq value. Since this is
858 * timer based, instead of loop based, we don't block the boot
859 * process while this longer calibration is done.
860 *
861 * If there are any calibration anomalies (too many SMIs, etc),
862 * or the refined calibration is off by 1% of the fast early
863 * calibration, we throw out the new calibration and use the
864 * early calibration.
865 */
866static void tsc_refine_calibration_work(struct work_struct *work)
867{
868 static u64 tsc_start = -1, ref_start;
869 static int hpet;
870 u64 tsc_stop, ref_stop, delta;
871 unsigned long freq;
872
873 /* Don't bother refining TSC on unstable systems */
874 if (check_tsc_unstable())
875 goto out;
876
877 /*
878 * Since the work is started early in boot, we may be
879 * delayed the first time we expire. So set the workqueue
880 * again once we know timers are working.
881 */
882 if (tsc_start == -1) {
883 /*
884 * Only set hpet once, to avoid mixing hardware
885 * if the hpet becomes enabled later.
886 */
887 hpet = is_hpet_enabled();
888 schedule_delayed_work(&tsc_irqwork, HZ);
889 tsc_start = tsc_read_refs(&ref_start, hpet);
890 return;
891 }
892
893 tsc_stop = tsc_read_refs(&ref_stop, hpet);
894
895 /* hpet or pmtimer available ? */
896 if (ref_start == ref_stop)
897 goto out;
898
899 /* Check, whether the sampling was disturbed by an SMI */
900 if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX)
901 goto out;
902
903 delta = tsc_stop - tsc_start;
904 delta *= 1000000LL;
905 if (hpet)
906 freq = calc_hpet_ref(delta, ref_start, ref_stop);
907 else
908 freq = calc_pmtimer_ref(delta, ref_start, ref_stop);
909
910 /* Make sure we're within 1% */
911 if (abs(tsc_khz - freq) > tsc_khz/100)
912 goto out;
913
914 tsc_khz = freq;
915 printk(KERN_INFO "Refined TSC clocksource calibration: "
916 "%lu.%03lu MHz.\n", (unsigned long)tsc_khz / 1000,
917 (unsigned long)tsc_khz % 1000);
918
919out:
920 clocksource_register_khz(&clocksource_tsc, tsc_khz);
921}
922
923
924static int __init init_tsc_clocksource(void)
925{
926 if (!cpu_has_tsc || tsc_disabled > 0 || !tsc_khz)
927 return 0;
928
929 if (tsc_clocksource_reliable)
930 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
931 /* lower the rating if we already know its unstable: */
932 if (check_tsc_unstable()) {
933 clocksource_tsc.rating = 0;
934 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
935 }
936
937 /*
938 * Trust the results of the earlier calibration on systems
939 * exporting a reliable TSC.
940 */
941 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) {
942 clocksource_register_khz(&clocksource_tsc, tsc_khz);
943 return 0;
944 }
945
946 schedule_delayed_work(&tsc_irqwork, 0);
947 return 0;
948}
949/*
950 * We use device_initcall here, to ensure we run after the hpet
951 * is fully initialized, which may occur at fs_initcall time.
952 */
953device_initcall(init_tsc_clocksource);
954
955void __init tsc_init(void)
956{
957 u64 lpj;
958 int cpu;
959
960 x86_init.timers.tsc_pre_init();
961
962 if (!cpu_has_tsc)
963 return;
964
965 tsc_khz = x86_platform.calibrate_tsc();
966 cpu_khz = tsc_khz;
967
968 if (!tsc_khz) {
969 mark_tsc_unstable("could not calculate TSC khz");
970 return;
971 }
972
973 printk("Detected %lu.%03lu MHz processor.\n",
974 (unsigned long)cpu_khz / 1000,
975 (unsigned long)cpu_khz % 1000);
976
977 /*
978 * Secondary CPUs do not run through tsc_init(), so set up
979 * all the scale factors for all CPUs, assuming the same
980 * speed as the bootup CPU. (cpufreq notifiers will fix this
981 * up if their speed diverges)
982 */
983 for_each_possible_cpu(cpu)
984 set_cyc2ns_scale(cpu_khz, cpu);
985
986 if (tsc_disabled > 0)
987 return;
988
989 /* now allow native_sched_clock() to use rdtsc */
990 tsc_disabled = 0;
991
992 if (!no_sched_irq_time)
993 enable_sched_clock_irqtime();
994
995 lpj = ((u64)tsc_khz * 1000);
996 do_div(lpj, HZ);
997 lpj_fine = lpj;
998
999 use_tsc_delay();
1000
1001 if (unsynchronized_tsc())
1002 mark_tsc_unstable("TSCs unsynchronized");
1003
1004 check_system_tsc_reliable();
1005}
1006
1007#ifdef CONFIG_SMP
1008/*
1009 * If we have a constant TSC and are using the TSC for the delay loop,
1010 * we can skip clock calibration if another cpu in the same socket has already
1011 * been calibrated. This assumes that CONSTANT_TSC applies to all
1012 * cpus in the socket - this should be a safe assumption.
1013 */
1014unsigned long __cpuinit calibrate_delay_is_known(void)
1015{
1016 int i, cpu = smp_processor_id();
1017
1018 if (!tsc_disabled && !cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC))
1019 return 0;
1020
1021 for_each_online_cpu(i)
1022 if (cpu_data(i).phys_proc_id == cpu_data(cpu).phys_proc_id)
1023 return cpu_data(i).loops_per_jiffy;
1024 return 0;
1025}
1026#endif
1#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
2
3#include <linux/kernel.h>
4#include <linux/sched.h>
5#include <linux/init.h>
6#include <linux/module.h>
7#include <linux/timer.h>
8#include <linux/acpi_pmtmr.h>
9#include <linux/cpufreq.h>
10#include <linux/delay.h>
11#include <linux/clocksource.h>
12#include <linux/percpu.h>
13#include <linux/timex.h>
14#include <linux/static_key.h>
15
16#include <asm/hpet.h>
17#include <asm/timer.h>
18#include <asm/vgtod.h>
19#include <asm/time.h>
20#include <asm/delay.h>
21#include <asm/hypervisor.h>
22#include <asm/nmi.h>
23#include <asm/x86_init.h>
24#include <asm/geode.h>
25
26unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
27EXPORT_SYMBOL(cpu_khz);
28
29unsigned int __read_mostly tsc_khz;
30EXPORT_SYMBOL(tsc_khz);
31
32/*
33 * TSC can be unstable due to cpufreq or due to unsynced TSCs
34 */
35static int __read_mostly tsc_unstable;
36
37/* native_sched_clock() is called before tsc_init(), so
38 we must start with the TSC soft disabled to prevent
39 erroneous rdtsc usage on !cpu_has_tsc processors */
40static int __read_mostly tsc_disabled = -1;
41
42static DEFINE_STATIC_KEY_FALSE(__use_tsc);
43
44int tsc_clocksource_reliable;
45
46static u32 art_to_tsc_numerator;
47static u32 art_to_tsc_denominator;
48static u64 art_to_tsc_offset;
49struct clocksource *art_related_clocksource;
50
51/*
52 * Use a ring-buffer like data structure, where a writer advances the head by
53 * writing a new data entry and a reader advances the tail when it observes a
54 * new entry.
55 *
56 * Writers are made to wait on readers until there's space to write a new
57 * entry.
58 *
59 * This means that we can always use an {offset, mul} pair to compute a ns
60 * value that is 'roughly' in the right direction, even if we're writing a new
61 * {offset, mul} pair during the clock read.
62 *
63 * The down-side is that we can no longer guarantee strict monotonicity anymore
64 * (assuming the TSC was that to begin with), because while we compute the
65 * intersection point of the two clock slopes and make sure the time is
66 * continuous at the point of switching; we can no longer guarantee a reader is
67 * strictly before or after the switch point.
68 *
69 * It does mean a reader no longer needs to disable IRQs in order to avoid
70 * CPU-Freq updates messing with his times, and similarly an NMI reader will
71 * no longer run the risk of hitting half-written state.
72 */
73
74struct cyc2ns {
75 struct cyc2ns_data data[2]; /* 0 + 2*24 = 48 */
76 struct cyc2ns_data *head; /* 48 + 8 = 56 */
77 struct cyc2ns_data *tail; /* 56 + 8 = 64 */
78}; /* exactly fits one cacheline */
79
80static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns);
81
82struct cyc2ns_data *cyc2ns_read_begin(void)
83{
84 struct cyc2ns_data *head;
85
86 preempt_disable();
87
88 head = this_cpu_read(cyc2ns.head);
89 /*
90 * Ensure we observe the entry when we observe the pointer to it.
91 * matches the wmb from cyc2ns_write_end().
92 */
93 smp_read_barrier_depends();
94 head->__count++;
95 barrier();
96
97 return head;
98}
99
100void cyc2ns_read_end(struct cyc2ns_data *head)
101{
102 barrier();
103 /*
104 * If we're the outer most nested read; update the tail pointer
105 * when we're done. This notifies possible pending writers
106 * that we've observed the head pointer and that the other
107 * entry is now free.
108 */
109 if (!--head->__count) {
110 /*
111 * x86-TSO does not reorder writes with older reads;
112 * therefore once this write becomes visible to another
113 * cpu, we must be finished reading the cyc2ns_data.
114 *
115 * matches with cyc2ns_write_begin().
116 */
117 this_cpu_write(cyc2ns.tail, head);
118 }
119 preempt_enable();
120}
121
122/*
123 * Begin writing a new @data entry for @cpu.
124 *
125 * Assumes some sort of write side lock; currently 'provided' by the assumption
126 * that cpufreq will call its notifiers sequentially.
127 */
128static struct cyc2ns_data *cyc2ns_write_begin(int cpu)
129{
130 struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
131 struct cyc2ns_data *data = c2n->data;
132
133 if (data == c2n->head)
134 data++;
135
136 /* XXX send an IPI to @cpu in order to guarantee a read? */
137
138 /*
139 * When we observe the tail write from cyc2ns_read_end(),
140 * the cpu must be done with that entry and its safe
141 * to start writing to it.
142 */
143 while (c2n->tail == data)
144 cpu_relax();
145
146 return data;
147}
148
149static void cyc2ns_write_end(int cpu, struct cyc2ns_data *data)
150{
151 struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
152
153 /*
154 * Ensure the @data writes are visible before we publish the
155 * entry. Matches the data-depencency in cyc2ns_read_begin().
156 */
157 smp_wmb();
158
159 ACCESS_ONCE(c2n->head) = data;
160}
161
162/*
163 * Accelerators for sched_clock()
164 * convert from cycles(64bits) => nanoseconds (64bits)
165 * basic equation:
166 * ns = cycles / (freq / ns_per_sec)
167 * ns = cycles * (ns_per_sec / freq)
168 * ns = cycles * (10^9 / (cpu_khz * 10^3))
169 * ns = cycles * (10^6 / cpu_khz)
170 *
171 * Then we use scaling math (suggested by george@mvista.com) to get:
172 * ns = cycles * (10^6 * SC / cpu_khz) / SC
173 * ns = cycles * cyc2ns_scale / SC
174 *
175 * And since SC is a constant power of two, we can convert the div
176 * into a shift. The larger SC is, the more accurate the conversion, but
177 * cyc2ns_scale needs to be a 32-bit value so that 32-bit multiplication
178 * (64-bit result) can be used.
179 *
180 * We can use khz divisor instead of mhz to keep a better precision.
181 * (mathieu.desnoyers@polymtl.ca)
182 *
183 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
184 */
185
186static void cyc2ns_data_init(struct cyc2ns_data *data)
187{
188 data->cyc2ns_mul = 0;
189 data->cyc2ns_shift = 0;
190 data->cyc2ns_offset = 0;
191 data->__count = 0;
192}
193
194static void cyc2ns_init(int cpu)
195{
196 struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
197
198 cyc2ns_data_init(&c2n->data[0]);
199 cyc2ns_data_init(&c2n->data[1]);
200
201 c2n->head = c2n->data;
202 c2n->tail = c2n->data;
203}
204
205static inline unsigned long long cycles_2_ns(unsigned long long cyc)
206{
207 struct cyc2ns_data *data, *tail;
208 unsigned long long ns;
209
210 /*
211 * See cyc2ns_read_*() for details; replicated in order to avoid
212 * an extra few instructions that came with the abstraction.
213 * Notable, it allows us to only do the __count and tail update
214 * dance when its actually needed.
215 */
216
217 preempt_disable_notrace();
218 data = this_cpu_read(cyc2ns.head);
219 tail = this_cpu_read(cyc2ns.tail);
220
221 if (likely(data == tail)) {
222 ns = data->cyc2ns_offset;
223 ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, data->cyc2ns_shift);
224 } else {
225 data->__count++;
226
227 barrier();
228
229 ns = data->cyc2ns_offset;
230 ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, data->cyc2ns_shift);
231
232 barrier();
233
234 if (!--data->__count)
235 this_cpu_write(cyc2ns.tail, data);
236 }
237 preempt_enable_notrace();
238
239 return ns;
240}
241
242static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
243{
244 unsigned long long tsc_now, ns_now;
245 struct cyc2ns_data *data;
246 unsigned long flags;
247
248 local_irq_save(flags);
249 sched_clock_idle_sleep_event();
250
251 if (!cpu_khz)
252 goto done;
253
254 data = cyc2ns_write_begin(cpu);
255
256 tsc_now = rdtsc();
257 ns_now = cycles_2_ns(tsc_now);
258
259 /*
260 * Compute a new multiplier as per the above comment and ensure our
261 * time function is continuous; see the comment near struct
262 * cyc2ns_data.
263 */
264 clocks_calc_mult_shift(&data->cyc2ns_mul, &data->cyc2ns_shift, cpu_khz,
265 NSEC_PER_MSEC, 0);
266
267 /*
268 * cyc2ns_shift is exported via arch_perf_update_userpage() where it is
269 * not expected to be greater than 31 due to the original published
270 * conversion algorithm shifting a 32-bit value (now specifies a 64-bit
271 * value) - refer perf_event_mmap_page documentation in perf_event.h.
272 */
273 if (data->cyc2ns_shift == 32) {
274 data->cyc2ns_shift = 31;
275 data->cyc2ns_mul >>= 1;
276 }
277
278 data->cyc2ns_offset = ns_now -
279 mul_u64_u32_shr(tsc_now, data->cyc2ns_mul, data->cyc2ns_shift);
280
281 cyc2ns_write_end(cpu, data);
282
283done:
284 sched_clock_idle_wakeup_event(0);
285 local_irq_restore(flags);
286}
287/*
288 * Scheduler clock - returns current time in nanosec units.
289 */
290u64 native_sched_clock(void)
291{
292 if (static_branch_likely(&__use_tsc)) {
293 u64 tsc_now = rdtsc();
294
295 /* return the value in ns */
296 return cycles_2_ns(tsc_now);
297 }
298
299 /*
300 * Fall back to jiffies if there's no TSC available:
301 * ( But note that we still use it if the TSC is marked
302 * unstable. We do this because unlike Time Of Day,
303 * the scheduler clock tolerates small errors and it's
304 * very important for it to be as fast as the platform
305 * can achieve it. )
306 */
307
308 /* No locking but a rare wrong value is not a big deal: */
309 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
310}
311
312/*
313 * Generate a sched_clock if you already have a TSC value.
314 */
315u64 native_sched_clock_from_tsc(u64 tsc)
316{
317 return cycles_2_ns(tsc);
318}
319
320/* We need to define a real function for sched_clock, to override the
321 weak default version */
322#ifdef CONFIG_PARAVIRT
323unsigned long long sched_clock(void)
324{
325 return paravirt_sched_clock();
326}
327#else
328unsigned long long
329sched_clock(void) __attribute__((alias("native_sched_clock")));
330#endif
331
332int check_tsc_unstable(void)
333{
334 return tsc_unstable;
335}
336EXPORT_SYMBOL_GPL(check_tsc_unstable);
337
338int check_tsc_disabled(void)
339{
340 return tsc_disabled;
341}
342EXPORT_SYMBOL_GPL(check_tsc_disabled);
343
344#ifdef CONFIG_X86_TSC
345int __init notsc_setup(char *str)
346{
347 pr_warn("Kernel compiled with CONFIG_X86_TSC, cannot disable TSC completely\n");
348 tsc_disabled = 1;
349 return 1;
350}
351#else
352/*
353 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
354 * in cpu/common.c
355 */
356int __init notsc_setup(char *str)
357{
358 setup_clear_cpu_cap(X86_FEATURE_TSC);
359 return 1;
360}
361#endif
362
363__setup("notsc", notsc_setup);
364
365static int no_sched_irq_time;
366
367static int __init tsc_setup(char *str)
368{
369 if (!strcmp(str, "reliable"))
370 tsc_clocksource_reliable = 1;
371 if (!strncmp(str, "noirqtime", 9))
372 no_sched_irq_time = 1;
373 return 1;
374}
375
376__setup("tsc=", tsc_setup);
377
378#define MAX_RETRIES 5
379#define SMI_TRESHOLD 50000
380
381/*
382 * Read TSC and the reference counters. Take care of SMI disturbance
383 */
384static u64 tsc_read_refs(u64 *p, int hpet)
385{
386 u64 t1, t2;
387 int i;
388
389 for (i = 0; i < MAX_RETRIES; i++) {
390 t1 = get_cycles();
391 if (hpet)
392 *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
393 else
394 *p = acpi_pm_read_early();
395 t2 = get_cycles();
396 if ((t2 - t1) < SMI_TRESHOLD)
397 return t2;
398 }
399 return ULLONG_MAX;
400}
401
402/*
403 * Calculate the TSC frequency from HPET reference
404 */
405static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
406{
407 u64 tmp;
408
409 if (hpet2 < hpet1)
410 hpet2 += 0x100000000ULL;
411 hpet2 -= hpet1;
412 tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
413 do_div(tmp, 1000000);
414 do_div(deltatsc, tmp);
415
416 return (unsigned long) deltatsc;
417}
418
419/*
420 * Calculate the TSC frequency from PMTimer reference
421 */
422static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
423{
424 u64 tmp;
425
426 if (!pm1 && !pm2)
427 return ULONG_MAX;
428
429 if (pm2 < pm1)
430 pm2 += (u64)ACPI_PM_OVRRUN;
431 pm2 -= pm1;
432 tmp = pm2 * 1000000000LL;
433 do_div(tmp, PMTMR_TICKS_PER_SEC);
434 do_div(deltatsc, tmp);
435
436 return (unsigned long) deltatsc;
437}
438
439#define CAL_MS 10
440#define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS))
441#define CAL_PIT_LOOPS 1000
442
443#define CAL2_MS 50
444#define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS))
445#define CAL2_PIT_LOOPS 5000
446
447
448/*
449 * Try to calibrate the TSC against the Programmable
450 * Interrupt Timer and return the frequency of the TSC
451 * in kHz.
452 *
453 * Return ULONG_MAX on failure to calibrate.
454 */
455static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
456{
457 u64 tsc, t1, t2, delta;
458 unsigned long tscmin, tscmax;
459 int pitcnt;
460
461 /* Set the Gate high, disable speaker */
462 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
463
464 /*
465 * Setup CTC channel 2* for mode 0, (interrupt on terminal
466 * count mode), binary count. Set the latch register to 50ms
467 * (LSB then MSB) to begin countdown.
468 */
469 outb(0xb0, 0x43);
470 outb(latch & 0xff, 0x42);
471 outb(latch >> 8, 0x42);
472
473 tsc = t1 = t2 = get_cycles();
474
475 pitcnt = 0;
476 tscmax = 0;
477 tscmin = ULONG_MAX;
478 while ((inb(0x61) & 0x20) == 0) {
479 t2 = get_cycles();
480 delta = t2 - tsc;
481 tsc = t2;
482 if ((unsigned long) delta < tscmin)
483 tscmin = (unsigned int) delta;
484 if ((unsigned long) delta > tscmax)
485 tscmax = (unsigned int) delta;
486 pitcnt++;
487 }
488
489 /*
490 * Sanity checks:
491 *
492 * If we were not able to read the PIT more than loopmin
493 * times, then we have been hit by a massive SMI
494 *
495 * If the maximum is 10 times larger than the minimum,
496 * then we got hit by an SMI as well.
497 */
498 if (pitcnt < loopmin || tscmax > 10 * tscmin)
499 return ULONG_MAX;
500
501 /* Calculate the PIT value */
502 delta = t2 - t1;
503 do_div(delta, ms);
504 return delta;
505}
506
507/*
508 * This reads the current MSB of the PIT counter, and
509 * checks if we are running on sufficiently fast and
510 * non-virtualized hardware.
511 *
512 * Our expectations are:
513 *
514 * - the PIT is running at roughly 1.19MHz
515 *
516 * - each IO is going to take about 1us on real hardware,
517 * but we allow it to be much faster (by a factor of 10) or
518 * _slightly_ slower (ie we allow up to a 2us read+counter
519 * update - anything else implies a unacceptably slow CPU
520 * or PIT for the fast calibration to work.
521 *
522 * - with 256 PIT ticks to read the value, we have 214us to
523 * see the same MSB (and overhead like doing a single TSC
524 * read per MSB value etc).
525 *
526 * - We're doing 2 reads per loop (LSB, MSB), and we expect
527 * them each to take about a microsecond on real hardware.
528 * So we expect a count value of around 100. But we'll be
529 * generous, and accept anything over 50.
530 *
531 * - if the PIT is stuck, and we see *many* more reads, we
532 * return early (and the next caller of pit_expect_msb()
533 * then consider it a failure when they don't see the
534 * next expected value).
535 *
536 * These expectations mean that we know that we have seen the
537 * transition from one expected value to another with a fairly
538 * high accuracy, and we didn't miss any events. We can thus
539 * use the TSC value at the transitions to calculate a pretty
540 * good value for the TSC frequencty.
541 */
542static inline int pit_verify_msb(unsigned char val)
543{
544 /* Ignore LSB */
545 inb(0x42);
546 return inb(0x42) == val;
547}
548
549static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
550{
551 int count;
552 u64 tsc = 0, prev_tsc = 0;
553
554 for (count = 0; count < 50000; count++) {
555 if (!pit_verify_msb(val))
556 break;
557 prev_tsc = tsc;
558 tsc = get_cycles();
559 }
560 *deltap = get_cycles() - prev_tsc;
561 *tscp = tsc;
562
563 /*
564 * We require _some_ success, but the quality control
565 * will be based on the error terms on the TSC values.
566 */
567 return count > 5;
568}
569
570/*
571 * How many MSB values do we want to see? We aim for
572 * a maximum error rate of 500ppm (in practice the
573 * real error is much smaller), but refuse to spend
574 * more than 50ms on it.
575 */
576#define MAX_QUICK_PIT_MS 50
577#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
578
579static unsigned long quick_pit_calibrate(void)
580{
581 int i;
582 u64 tsc, delta;
583 unsigned long d1, d2;
584
585 /* Set the Gate high, disable speaker */
586 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
587
588 /*
589 * Counter 2, mode 0 (one-shot), binary count
590 *
591 * NOTE! Mode 2 decrements by two (and then the
592 * output is flipped each time, giving the same
593 * final output frequency as a decrement-by-one),
594 * so mode 0 is much better when looking at the
595 * individual counts.
596 */
597 outb(0xb0, 0x43);
598
599 /* Start at 0xffff */
600 outb(0xff, 0x42);
601 outb(0xff, 0x42);
602
603 /*
604 * The PIT starts counting at the next edge, so we
605 * need to delay for a microsecond. The easiest way
606 * to do that is to just read back the 16-bit counter
607 * once from the PIT.
608 */
609 pit_verify_msb(0);
610
611 if (pit_expect_msb(0xff, &tsc, &d1)) {
612 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
613 if (!pit_expect_msb(0xff-i, &delta, &d2))
614 break;
615
616 delta -= tsc;
617
618 /*
619 * Extrapolate the error and fail fast if the error will
620 * never be below 500 ppm.
621 */
622 if (i == 1 &&
623 d1 + d2 >= (delta * MAX_QUICK_PIT_ITERATIONS) >> 11)
624 return 0;
625
626 /*
627 * Iterate until the error is less than 500 ppm
628 */
629 if (d1+d2 >= delta >> 11)
630 continue;
631
632 /*
633 * Check the PIT one more time to verify that
634 * all TSC reads were stable wrt the PIT.
635 *
636 * This also guarantees serialization of the
637 * last cycle read ('d2') in pit_expect_msb.
638 */
639 if (!pit_verify_msb(0xfe - i))
640 break;
641 goto success;
642 }
643 }
644 pr_info("Fast TSC calibration failed\n");
645 return 0;
646
647success:
648 /*
649 * Ok, if we get here, then we've seen the
650 * MSB of the PIT decrement 'i' times, and the
651 * error has shrunk to less than 500 ppm.
652 *
653 * As a result, we can depend on there not being
654 * any odd delays anywhere, and the TSC reads are
655 * reliable (within the error).
656 *
657 * kHz = ticks / time-in-seconds / 1000;
658 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
659 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
660 */
661 delta *= PIT_TICK_RATE;
662 do_div(delta, i*256*1000);
663 pr_info("Fast TSC calibration using PIT\n");
664 return delta;
665}
666
667/**
668 * native_calibrate_tsc - calibrate the tsc on boot
669 */
670unsigned long native_calibrate_tsc(void)
671{
672 u64 tsc1, tsc2, delta, ref1, ref2;
673 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
674 unsigned long flags, latch, ms, fast_calibrate;
675 int hpet = is_hpet_enabled(), i, loopmin;
676
677 /* Calibrate TSC using MSR for Intel Atom SoCs */
678 local_irq_save(flags);
679 fast_calibrate = try_msr_calibrate_tsc();
680 local_irq_restore(flags);
681 if (fast_calibrate)
682 return fast_calibrate;
683
684 local_irq_save(flags);
685 fast_calibrate = quick_pit_calibrate();
686 local_irq_restore(flags);
687 if (fast_calibrate)
688 return fast_calibrate;
689
690 /*
691 * Run 5 calibration loops to get the lowest frequency value
692 * (the best estimate). We use two different calibration modes
693 * here:
694 *
695 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
696 * load a timeout of 50ms. We read the time right after we
697 * started the timer and wait until the PIT count down reaches
698 * zero. In each wait loop iteration we read the TSC and check
699 * the delta to the previous read. We keep track of the min
700 * and max values of that delta. The delta is mostly defined
701 * by the IO time of the PIT access, so we can detect when a
702 * SMI/SMM disturbance happened between the two reads. If the
703 * maximum time is significantly larger than the minimum time,
704 * then we discard the result and have another try.
705 *
706 * 2) Reference counter. If available we use the HPET or the
707 * PMTIMER as a reference to check the sanity of that value.
708 * We use separate TSC readouts and check inside of the
709 * reference read for a SMI/SMM disturbance. We dicard
710 * disturbed values here as well. We do that around the PIT
711 * calibration delay loop as we have to wait for a certain
712 * amount of time anyway.
713 */
714
715 /* Preset PIT loop values */
716 latch = CAL_LATCH;
717 ms = CAL_MS;
718 loopmin = CAL_PIT_LOOPS;
719
720 for (i = 0; i < 3; i++) {
721 unsigned long tsc_pit_khz;
722
723 /*
724 * Read the start value and the reference count of
725 * hpet/pmtimer when available. Then do the PIT
726 * calibration, which will take at least 50ms, and
727 * read the end value.
728 */
729 local_irq_save(flags);
730 tsc1 = tsc_read_refs(&ref1, hpet);
731 tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
732 tsc2 = tsc_read_refs(&ref2, hpet);
733 local_irq_restore(flags);
734
735 /* Pick the lowest PIT TSC calibration so far */
736 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
737
738 /* hpet or pmtimer available ? */
739 if (ref1 == ref2)
740 continue;
741
742 /* Check, whether the sampling was disturbed by an SMI */
743 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
744 continue;
745
746 tsc2 = (tsc2 - tsc1) * 1000000LL;
747 if (hpet)
748 tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
749 else
750 tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
751
752 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
753
754 /* Check the reference deviation */
755 delta = ((u64) tsc_pit_min) * 100;
756 do_div(delta, tsc_ref_min);
757
758 /*
759 * If both calibration results are inside a 10% window
760 * then we can be sure, that the calibration
761 * succeeded. We break out of the loop right away. We
762 * use the reference value, as it is more precise.
763 */
764 if (delta >= 90 && delta <= 110) {
765 pr_info("PIT calibration matches %s. %d loops\n",
766 hpet ? "HPET" : "PMTIMER", i + 1);
767 return tsc_ref_min;
768 }
769
770 /*
771 * Check whether PIT failed more than once. This
772 * happens in virtualized environments. We need to
773 * give the virtual PC a slightly longer timeframe for
774 * the HPET/PMTIMER to make the result precise.
775 */
776 if (i == 1 && tsc_pit_min == ULONG_MAX) {
777 latch = CAL2_LATCH;
778 ms = CAL2_MS;
779 loopmin = CAL2_PIT_LOOPS;
780 }
781 }
782
783 /*
784 * Now check the results.
785 */
786 if (tsc_pit_min == ULONG_MAX) {
787 /* PIT gave no useful value */
788 pr_warn("Unable to calibrate against PIT\n");
789
790 /* We don't have an alternative source, disable TSC */
791 if (!hpet && !ref1 && !ref2) {
792 pr_notice("No reference (HPET/PMTIMER) available\n");
793 return 0;
794 }
795
796 /* The alternative source failed as well, disable TSC */
797 if (tsc_ref_min == ULONG_MAX) {
798 pr_warn("HPET/PMTIMER calibration failed\n");
799 return 0;
800 }
801
802 /* Use the alternative source */
803 pr_info("using %s reference calibration\n",
804 hpet ? "HPET" : "PMTIMER");
805
806 return tsc_ref_min;
807 }
808
809 /* We don't have an alternative source, use the PIT calibration value */
810 if (!hpet && !ref1 && !ref2) {
811 pr_info("Using PIT calibration value\n");
812 return tsc_pit_min;
813 }
814
815 /* The alternative source failed, use the PIT calibration value */
816 if (tsc_ref_min == ULONG_MAX) {
817 pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n");
818 return tsc_pit_min;
819 }
820
821 /*
822 * The calibration values differ too much. In doubt, we use
823 * the PIT value as we know that there are PMTIMERs around
824 * running at double speed. At least we let the user know:
825 */
826 pr_warn("PIT calibration deviates from %s: %lu %lu\n",
827 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
828 pr_info("Using PIT calibration value\n");
829 return tsc_pit_min;
830}
831
832int recalibrate_cpu_khz(void)
833{
834#ifndef CONFIG_SMP
835 unsigned long cpu_khz_old = cpu_khz;
836
837 if (cpu_has_tsc) {
838 tsc_khz = x86_platform.calibrate_tsc();
839 cpu_khz = tsc_khz;
840 cpu_data(0).loops_per_jiffy =
841 cpufreq_scale(cpu_data(0).loops_per_jiffy,
842 cpu_khz_old, cpu_khz);
843 return 0;
844 } else
845 return -ENODEV;
846#else
847 return -ENODEV;
848#endif
849}
850
851EXPORT_SYMBOL(recalibrate_cpu_khz);
852
853
854static unsigned long long cyc2ns_suspend;
855
856void tsc_save_sched_clock_state(void)
857{
858 if (!sched_clock_stable())
859 return;
860
861 cyc2ns_suspend = sched_clock();
862}
863
864/*
865 * Even on processors with invariant TSC, TSC gets reset in some the
866 * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
867 * arbitrary value (still sync'd across cpu's) during resume from such sleep
868 * states. To cope up with this, recompute the cyc2ns_offset for each cpu so
869 * that sched_clock() continues from the point where it was left off during
870 * suspend.
871 */
872void tsc_restore_sched_clock_state(void)
873{
874 unsigned long long offset;
875 unsigned long flags;
876 int cpu;
877
878 if (!sched_clock_stable())
879 return;
880
881 local_irq_save(flags);
882
883 /*
884 * We're coming out of suspend, there's no concurrency yet; don't
885 * bother being nice about the RCU stuff, just write to both
886 * data fields.
887 */
888
889 this_cpu_write(cyc2ns.data[0].cyc2ns_offset, 0);
890 this_cpu_write(cyc2ns.data[1].cyc2ns_offset, 0);
891
892 offset = cyc2ns_suspend - sched_clock();
893
894 for_each_possible_cpu(cpu) {
895 per_cpu(cyc2ns.data[0].cyc2ns_offset, cpu) = offset;
896 per_cpu(cyc2ns.data[1].cyc2ns_offset, cpu) = offset;
897 }
898
899 local_irq_restore(flags);
900}
901
902#ifdef CONFIG_CPU_FREQ
903
904/* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
905 * changes.
906 *
907 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
908 * not that important because current Opteron setups do not support
909 * scaling on SMP anyroads.
910 *
911 * Should fix up last_tsc too. Currently gettimeofday in the
912 * first tick after the change will be slightly wrong.
913 */
914
915static unsigned int ref_freq;
916static unsigned long loops_per_jiffy_ref;
917static unsigned long tsc_khz_ref;
918
919static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
920 void *data)
921{
922 struct cpufreq_freqs *freq = data;
923 unsigned long *lpj;
924
925 if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
926 return 0;
927
928 lpj = &boot_cpu_data.loops_per_jiffy;
929#ifdef CONFIG_SMP
930 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
931 lpj = &cpu_data(freq->cpu).loops_per_jiffy;
932#endif
933
934 if (!ref_freq) {
935 ref_freq = freq->old;
936 loops_per_jiffy_ref = *lpj;
937 tsc_khz_ref = tsc_khz;
938 }
939 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
940 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) {
941 *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
942
943 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
944 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
945 mark_tsc_unstable("cpufreq changes");
946
947 set_cyc2ns_scale(tsc_khz, freq->cpu);
948 }
949
950 return 0;
951}
952
953static struct notifier_block time_cpufreq_notifier_block = {
954 .notifier_call = time_cpufreq_notifier
955};
956
957static int __init cpufreq_tsc(void)
958{
959 if (!cpu_has_tsc)
960 return 0;
961 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
962 return 0;
963 cpufreq_register_notifier(&time_cpufreq_notifier_block,
964 CPUFREQ_TRANSITION_NOTIFIER);
965 return 0;
966}
967
968core_initcall(cpufreq_tsc);
969
970#endif /* CONFIG_CPU_FREQ */
971
972#define ART_CPUID_LEAF (0x15)
973#define ART_MIN_DENOMINATOR (1)
974
975
976/*
977 * If ART is present detect the numerator:denominator to convert to TSC
978 */
979static void detect_art(void)
980{
981 unsigned int unused[2];
982
983 if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF)
984 return;
985
986 cpuid(ART_CPUID_LEAF, &art_to_tsc_denominator,
987 &art_to_tsc_numerator, unused, unused+1);
988
989 /* Don't enable ART in a VM, non-stop TSC required */
990 if (boot_cpu_has(X86_FEATURE_HYPERVISOR) ||
991 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC) ||
992 art_to_tsc_denominator < ART_MIN_DENOMINATOR)
993 return;
994
995 if (rdmsrl_safe(MSR_IA32_TSC_ADJUST, &art_to_tsc_offset))
996 return;
997
998 /* Make this sticky over multiple CPU init calls */
999 setup_force_cpu_cap(X86_FEATURE_ART);
1000}
1001
1002
1003/* clocksource code */
1004
1005static struct clocksource clocksource_tsc;
1006
1007/*
1008 * We used to compare the TSC to the cycle_last value in the clocksource
1009 * structure to avoid a nasty time-warp. This can be observed in a
1010 * very small window right after one CPU updated cycle_last under
1011 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
1012 * is smaller than the cycle_last reference value due to a TSC which
1013 * is slighty behind. This delta is nowhere else observable, but in
1014 * that case it results in a forward time jump in the range of hours
1015 * due to the unsigned delta calculation of the time keeping core
1016 * code, which is necessary to support wrapping clocksources like pm
1017 * timer.
1018 *
1019 * This sanity check is now done in the core timekeeping code.
1020 * checking the result of read_tsc() - cycle_last for being negative.
1021 * That works because CLOCKSOURCE_MASK(64) does not mask out any bit.
1022 */
1023static cycle_t read_tsc(struct clocksource *cs)
1024{
1025 return (cycle_t)rdtsc_ordered();
1026}
1027
1028/*
1029 * .mask MUST be CLOCKSOURCE_MASK(64). See comment above read_tsc()
1030 */
1031static struct clocksource clocksource_tsc = {
1032 .name = "tsc",
1033 .rating = 300,
1034 .read = read_tsc,
1035 .mask = CLOCKSOURCE_MASK(64),
1036 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
1037 CLOCK_SOURCE_MUST_VERIFY,
1038 .archdata = { .vclock_mode = VCLOCK_TSC },
1039};
1040
1041void mark_tsc_unstable(char *reason)
1042{
1043 if (!tsc_unstable) {
1044 tsc_unstable = 1;
1045 clear_sched_clock_stable();
1046 disable_sched_clock_irqtime();
1047 pr_info("Marking TSC unstable due to %s\n", reason);
1048 /* Change only the rating, when not registered */
1049 if (clocksource_tsc.mult)
1050 clocksource_mark_unstable(&clocksource_tsc);
1051 else {
1052 clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE;
1053 clocksource_tsc.rating = 0;
1054 }
1055 }
1056}
1057
1058EXPORT_SYMBOL_GPL(mark_tsc_unstable);
1059
1060static void __init check_system_tsc_reliable(void)
1061{
1062#if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC)
1063 if (is_geode_lx()) {
1064 /* RTSC counts during suspend */
1065#define RTSC_SUSP 0x100
1066 unsigned long res_low, res_high;
1067
1068 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
1069 /* Geode_LX - the OLPC CPU has a very reliable TSC */
1070 if (res_low & RTSC_SUSP)
1071 tsc_clocksource_reliable = 1;
1072 }
1073#endif
1074 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
1075 tsc_clocksource_reliable = 1;
1076}
1077
1078/*
1079 * Make an educated guess if the TSC is trustworthy and synchronized
1080 * over all CPUs.
1081 */
1082int unsynchronized_tsc(void)
1083{
1084 if (!cpu_has_tsc || tsc_unstable)
1085 return 1;
1086
1087#ifdef CONFIG_SMP
1088 if (apic_is_clustered_box())
1089 return 1;
1090#endif
1091
1092 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
1093 return 0;
1094
1095 if (tsc_clocksource_reliable)
1096 return 0;
1097 /*
1098 * Intel systems are normally all synchronized.
1099 * Exceptions must mark TSC as unstable:
1100 */
1101 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
1102 /* assume multi socket systems are not synchronized: */
1103 if (num_possible_cpus() > 1)
1104 return 1;
1105 }
1106
1107 return 0;
1108}
1109
1110/*
1111 * Convert ART to TSC given numerator/denominator found in detect_art()
1112 */
1113struct system_counterval_t convert_art_to_tsc(cycle_t art)
1114{
1115 u64 tmp, res, rem;
1116
1117 rem = do_div(art, art_to_tsc_denominator);
1118
1119 res = art * art_to_tsc_numerator;
1120 tmp = rem * art_to_tsc_numerator;
1121
1122 do_div(tmp, art_to_tsc_denominator);
1123 res += tmp + art_to_tsc_offset;
1124
1125 return (struct system_counterval_t) {.cs = art_related_clocksource,
1126 .cycles = res};
1127}
1128EXPORT_SYMBOL(convert_art_to_tsc);
1129
1130static void tsc_refine_calibration_work(struct work_struct *work);
1131static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work);
1132/**
1133 * tsc_refine_calibration_work - Further refine tsc freq calibration
1134 * @work - ignored.
1135 *
1136 * This functions uses delayed work over a period of a
1137 * second to further refine the TSC freq value. Since this is
1138 * timer based, instead of loop based, we don't block the boot
1139 * process while this longer calibration is done.
1140 *
1141 * If there are any calibration anomalies (too many SMIs, etc),
1142 * or the refined calibration is off by 1% of the fast early
1143 * calibration, we throw out the new calibration and use the
1144 * early calibration.
1145 */
1146static void tsc_refine_calibration_work(struct work_struct *work)
1147{
1148 static u64 tsc_start = -1, ref_start;
1149 static int hpet;
1150 u64 tsc_stop, ref_stop, delta;
1151 unsigned long freq;
1152
1153 /* Don't bother refining TSC on unstable systems */
1154 if (check_tsc_unstable())
1155 goto out;
1156
1157 /*
1158 * Since the work is started early in boot, we may be
1159 * delayed the first time we expire. So set the workqueue
1160 * again once we know timers are working.
1161 */
1162 if (tsc_start == -1) {
1163 /*
1164 * Only set hpet once, to avoid mixing hardware
1165 * if the hpet becomes enabled later.
1166 */
1167 hpet = is_hpet_enabled();
1168 schedule_delayed_work(&tsc_irqwork, HZ);
1169 tsc_start = tsc_read_refs(&ref_start, hpet);
1170 return;
1171 }
1172
1173 tsc_stop = tsc_read_refs(&ref_stop, hpet);
1174
1175 /* hpet or pmtimer available ? */
1176 if (ref_start == ref_stop)
1177 goto out;
1178
1179 /* Check, whether the sampling was disturbed by an SMI */
1180 if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX)
1181 goto out;
1182
1183 delta = tsc_stop - tsc_start;
1184 delta *= 1000000LL;
1185 if (hpet)
1186 freq = calc_hpet_ref(delta, ref_start, ref_stop);
1187 else
1188 freq = calc_pmtimer_ref(delta, ref_start, ref_stop);
1189
1190 /* Make sure we're within 1% */
1191 if (abs(tsc_khz - freq) > tsc_khz/100)
1192 goto out;
1193
1194 tsc_khz = freq;
1195 pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n",
1196 (unsigned long)tsc_khz / 1000,
1197 (unsigned long)tsc_khz % 1000);
1198
1199out:
1200 if (boot_cpu_has(X86_FEATURE_ART))
1201 art_related_clocksource = &clocksource_tsc;
1202 clocksource_register_khz(&clocksource_tsc, tsc_khz);
1203}
1204
1205
1206static int __init init_tsc_clocksource(void)
1207{
1208 if (!cpu_has_tsc || tsc_disabled > 0 || !tsc_khz)
1209 return 0;
1210
1211 if (tsc_clocksource_reliable)
1212 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
1213 /* lower the rating if we already know its unstable: */
1214 if (check_tsc_unstable()) {
1215 clocksource_tsc.rating = 0;
1216 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
1217 }
1218
1219 if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3))
1220 clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
1221
1222 /*
1223 * Trust the results of the earlier calibration on systems
1224 * exporting a reliable TSC.
1225 */
1226 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) {
1227 clocksource_register_khz(&clocksource_tsc, tsc_khz);
1228 return 0;
1229 }
1230
1231 schedule_delayed_work(&tsc_irqwork, 0);
1232 return 0;
1233}
1234/*
1235 * We use device_initcall here, to ensure we run after the hpet
1236 * is fully initialized, which may occur at fs_initcall time.
1237 */
1238device_initcall(init_tsc_clocksource);
1239
1240void __init tsc_init(void)
1241{
1242 u64 lpj;
1243 int cpu;
1244
1245 if (!cpu_has_tsc) {
1246 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1247 return;
1248 }
1249
1250 tsc_khz = x86_platform.calibrate_tsc();
1251 cpu_khz = tsc_khz;
1252
1253 if (!tsc_khz) {
1254 mark_tsc_unstable("could not calculate TSC khz");
1255 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1256 return;
1257 }
1258
1259 pr_info("Detected %lu.%03lu MHz processor\n",
1260 (unsigned long)cpu_khz / 1000,
1261 (unsigned long)cpu_khz % 1000);
1262
1263 /*
1264 * Secondary CPUs do not run through tsc_init(), so set up
1265 * all the scale factors for all CPUs, assuming the same
1266 * speed as the bootup CPU. (cpufreq notifiers will fix this
1267 * up if their speed diverges)
1268 */
1269 for_each_possible_cpu(cpu) {
1270 cyc2ns_init(cpu);
1271 set_cyc2ns_scale(cpu_khz, cpu);
1272 }
1273
1274 if (tsc_disabled > 0)
1275 return;
1276
1277 /* now allow native_sched_clock() to use rdtsc */
1278
1279 tsc_disabled = 0;
1280 static_branch_enable(&__use_tsc);
1281
1282 if (!no_sched_irq_time)
1283 enable_sched_clock_irqtime();
1284
1285 lpj = ((u64)tsc_khz * 1000);
1286 do_div(lpj, HZ);
1287 lpj_fine = lpj;
1288
1289 use_tsc_delay();
1290
1291 if (unsynchronized_tsc())
1292 mark_tsc_unstable("TSCs unsynchronized");
1293
1294 check_system_tsc_reliable();
1295
1296 detect_art();
1297}
1298
1299#ifdef CONFIG_SMP
1300/*
1301 * If we have a constant TSC and are using the TSC for the delay loop,
1302 * we can skip clock calibration if another cpu in the same socket has already
1303 * been calibrated. This assumes that CONSTANT_TSC applies to all
1304 * cpus in the socket - this should be a safe assumption.
1305 */
1306unsigned long calibrate_delay_is_known(void)
1307{
1308 int sibling, cpu = smp_processor_id();
1309 struct cpumask *mask = topology_core_cpumask(cpu);
1310
1311 if (!tsc_disabled && !cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC))
1312 return 0;
1313
1314 if (!mask)
1315 return 0;
1316
1317 sibling = cpumask_any_but(mask, cpu);
1318 if (sibling < nr_cpu_ids)
1319 return cpu_data(sibling).loops_per_jiffy;
1320 return 0;
1321}
1322#endif