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1#include <linux/errno.h>
2#include <linux/kernel.h>
3#include <linux/mm.h>
4#include <linux/smp.h>
5#include <linux/prctl.h>
6#include <linux/slab.h>
7#include <linux/sched.h>
8#include <linux/module.h>
9#include <linux/pm.h>
10#include <linux/clockchips.h>
11#include <linux/random.h>
12#include <linux/user-return-notifier.h>
13#include <linux/dmi.h>
14#include <linux/utsname.h>
15#include <linux/stackprotector.h>
16#include <linux/tick.h>
17#include <linux/cpuidle.h>
18#include <trace/events/power.h>
19#include <linux/hw_breakpoint.h>
20#include <asm/cpu.h>
21#include <asm/apic.h>
22#include <asm/syscalls.h>
23#include <asm/idle.h>
24#include <asm/uaccess.h>
25#include <asm/i387.h>
26#include <asm/fpu-internal.h>
27#include <asm/debugreg.h>
28#include <asm/nmi.h>
29
30/*
31 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
32 * no more per-task TSS's. The TSS size is kept cacheline-aligned
33 * so they are allowed to end up in the .data..cacheline_aligned
34 * section. Since TSS's are completely CPU-local, we want them
35 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
36 */
37DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss) = INIT_TSS;
38
39#ifdef CONFIG_X86_64
40static DEFINE_PER_CPU(unsigned char, is_idle);
41static ATOMIC_NOTIFIER_HEAD(idle_notifier);
42
43void idle_notifier_register(struct notifier_block *n)
44{
45 atomic_notifier_chain_register(&idle_notifier, n);
46}
47EXPORT_SYMBOL_GPL(idle_notifier_register);
48
49void idle_notifier_unregister(struct notifier_block *n)
50{
51 atomic_notifier_chain_unregister(&idle_notifier, n);
52}
53EXPORT_SYMBOL_GPL(idle_notifier_unregister);
54#endif
55
56struct kmem_cache *task_xstate_cachep;
57EXPORT_SYMBOL_GPL(task_xstate_cachep);
58
59/*
60 * this gets called so that we can store lazy state into memory and copy the
61 * current task into the new thread.
62 */
63int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
64{
65 int ret;
66
67 unlazy_fpu(src);
68
69 *dst = *src;
70 if (fpu_allocated(&src->thread.fpu)) {
71 memset(&dst->thread.fpu, 0, sizeof(dst->thread.fpu));
72 ret = fpu_alloc(&dst->thread.fpu);
73 if (ret)
74 return ret;
75 fpu_copy(&dst->thread.fpu, &src->thread.fpu);
76 }
77 return 0;
78}
79
80void free_thread_xstate(struct task_struct *tsk)
81{
82 fpu_free(&tsk->thread.fpu);
83}
84
85void arch_release_task_struct(struct task_struct *tsk)
86{
87 free_thread_xstate(tsk);
88}
89
90void arch_task_cache_init(void)
91{
92 task_xstate_cachep =
93 kmem_cache_create("task_xstate", xstate_size,
94 __alignof__(union thread_xstate),
95 SLAB_PANIC | SLAB_NOTRACK, NULL);
96}
97
98static inline void drop_fpu(struct task_struct *tsk)
99{
100 /*
101 * Forget coprocessor state..
102 */
103 tsk->fpu_counter = 0;
104 clear_fpu(tsk);
105 clear_used_math();
106}
107
108/*
109 * Free current thread data structures etc..
110 */
111void exit_thread(void)
112{
113 struct task_struct *me = current;
114 struct thread_struct *t = &me->thread;
115 unsigned long *bp = t->io_bitmap_ptr;
116
117 if (bp) {
118 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
119
120 t->io_bitmap_ptr = NULL;
121 clear_thread_flag(TIF_IO_BITMAP);
122 /*
123 * Careful, clear this in the TSS too:
124 */
125 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
126 t->io_bitmap_max = 0;
127 put_cpu();
128 kfree(bp);
129 }
130
131 drop_fpu(me);
132}
133
134void show_regs_common(void)
135{
136 const char *vendor, *product, *board;
137
138 vendor = dmi_get_system_info(DMI_SYS_VENDOR);
139 if (!vendor)
140 vendor = "";
141 product = dmi_get_system_info(DMI_PRODUCT_NAME);
142 if (!product)
143 product = "";
144
145 /* Board Name is optional */
146 board = dmi_get_system_info(DMI_BOARD_NAME);
147
148 printk(KERN_CONT "\n");
149 printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s",
150 current->pid, current->comm, print_tainted(),
151 init_utsname()->release,
152 (int)strcspn(init_utsname()->version, " "),
153 init_utsname()->version);
154 printk(KERN_CONT " %s %s", vendor, product);
155 if (board)
156 printk(KERN_CONT "/%s", board);
157 printk(KERN_CONT "\n");
158}
159
160void flush_thread(void)
161{
162 struct task_struct *tsk = current;
163
164 flush_ptrace_hw_breakpoint(tsk);
165 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
166 drop_fpu(tsk);
167}
168
169static void hard_disable_TSC(void)
170{
171 write_cr4(read_cr4() | X86_CR4_TSD);
172}
173
174void disable_TSC(void)
175{
176 preempt_disable();
177 if (!test_and_set_thread_flag(TIF_NOTSC))
178 /*
179 * Must flip the CPU state synchronously with
180 * TIF_NOTSC in the current running context.
181 */
182 hard_disable_TSC();
183 preempt_enable();
184}
185
186static void hard_enable_TSC(void)
187{
188 write_cr4(read_cr4() & ~X86_CR4_TSD);
189}
190
191static void enable_TSC(void)
192{
193 preempt_disable();
194 if (test_and_clear_thread_flag(TIF_NOTSC))
195 /*
196 * Must flip the CPU state synchronously with
197 * TIF_NOTSC in the current running context.
198 */
199 hard_enable_TSC();
200 preempt_enable();
201}
202
203int get_tsc_mode(unsigned long adr)
204{
205 unsigned int val;
206
207 if (test_thread_flag(TIF_NOTSC))
208 val = PR_TSC_SIGSEGV;
209 else
210 val = PR_TSC_ENABLE;
211
212 return put_user(val, (unsigned int __user *)adr);
213}
214
215int set_tsc_mode(unsigned int val)
216{
217 if (val == PR_TSC_SIGSEGV)
218 disable_TSC();
219 else if (val == PR_TSC_ENABLE)
220 enable_TSC();
221 else
222 return -EINVAL;
223
224 return 0;
225}
226
227void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
228 struct tss_struct *tss)
229{
230 struct thread_struct *prev, *next;
231
232 prev = &prev_p->thread;
233 next = &next_p->thread;
234
235 if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
236 test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
237 unsigned long debugctl = get_debugctlmsr();
238
239 debugctl &= ~DEBUGCTLMSR_BTF;
240 if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
241 debugctl |= DEBUGCTLMSR_BTF;
242
243 update_debugctlmsr(debugctl);
244 }
245
246 if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
247 test_tsk_thread_flag(next_p, TIF_NOTSC)) {
248 /* prev and next are different */
249 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
250 hard_disable_TSC();
251 else
252 hard_enable_TSC();
253 }
254
255 if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
256 /*
257 * Copy the relevant range of the IO bitmap.
258 * Normally this is 128 bytes or less:
259 */
260 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
261 max(prev->io_bitmap_max, next->io_bitmap_max));
262 } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
263 /*
264 * Clear any possible leftover bits:
265 */
266 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
267 }
268 propagate_user_return_notify(prev_p, next_p);
269}
270
271int sys_fork(struct pt_regs *regs)
272{
273 return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
274}
275
276/*
277 * This is trivial, and on the face of it looks like it
278 * could equally well be done in user mode.
279 *
280 * Not so, for quite unobvious reasons - register pressure.
281 * In user mode vfork() cannot have a stack frame, and if
282 * done by calling the "clone()" system call directly, you
283 * do not have enough call-clobbered registers to hold all
284 * the information you need.
285 */
286int sys_vfork(struct pt_regs *regs)
287{
288 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
289 NULL, NULL);
290}
291
292long
293sys_clone(unsigned long clone_flags, unsigned long newsp,
294 void __user *parent_tid, void __user *child_tid, struct pt_regs *regs)
295{
296 if (!newsp)
297 newsp = regs->sp;
298 return do_fork(clone_flags, newsp, regs, 0, parent_tid, child_tid);
299}
300
301/*
302 * This gets run with %si containing the
303 * function to call, and %di containing
304 * the "args".
305 */
306extern void kernel_thread_helper(void);
307
308/*
309 * Create a kernel thread
310 */
311int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
312{
313 struct pt_regs regs;
314
315 memset(®s, 0, sizeof(regs));
316
317 regs.si = (unsigned long) fn;
318 regs.di = (unsigned long) arg;
319
320#ifdef CONFIG_X86_32
321 regs.ds = __USER_DS;
322 regs.es = __USER_DS;
323 regs.fs = __KERNEL_PERCPU;
324 regs.gs = __KERNEL_STACK_CANARY;
325#else
326 regs.ss = __KERNEL_DS;
327#endif
328
329 regs.orig_ax = -1;
330 regs.ip = (unsigned long) kernel_thread_helper;
331 regs.cs = __KERNEL_CS | get_kernel_rpl();
332 regs.flags = X86_EFLAGS_IF | X86_EFLAGS_BIT1;
333
334 /* Ok, create the new process.. */
335 return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, ®s, 0, NULL, NULL);
336}
337EXPORT_SYMBOL(kernel_thread);
338
339/*
340 * sys_execve() executes a new program.
341 */
342long sys_execve(const char __user *name,
343 const char __user *const __user *argv,
344 const char __user *const __user *envp, struct pt_regs *regs)
345{
346 long error;
347 char *filename;
348
349 filename = getname(name);
350 error = PTR_ERR(filename);
351 if (IS_ERR(filename))
352 return error;
353 error = do_execve(filename, argv, envp, regs);
354
355#ifdef CONFIG_X86_32
356 if (error == 0) {
357 /* Make sure we don't return using sysenter.. */
358 set_thread_flag(TIF_IRET);
359 }
360#endif
361
362 putname(filename);
363 return error;
364}
365
366/*
367 * Idle related variables and functions
368 */
369unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
370EXPORT_SYMBOL(boot_option_idle_override);
371
372/*
373 * Powermanagement idle function, if any..
374 */
375void (*pm_idle)(void);
376#ifdef CONFIG_APM_MODULE
377EXPORT_SYMBOL(pm_idle);
378#endif
379
380static inline int hlt_use_halt(void)
381{
382 return 1;
383}
384
385#ifndef CONFIG_SMP
386static inline void play_dead(void)
387{
388 BUG();
389}
390#endif
391
392#ifdef CONFIG_X86_64
393void enter_idle(void)
394{
395 this_cpu_write(is_idle, 1);
396 atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL);
397}
398
399static void __exit_idle(void)
400{
401 if (x86_test_and_clear_bit_percpu(0, is_idle) == 0)
402 return;
403 atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL);
404}
405
406/* Called from interrupts to signify idle end */
407void exit_idle(void)
408{
409 /* idle loop has pid 0 */
410 if (current->pid)
411 return;
412 __exit_idle();
413}
414#endif
415
416/*
417 * The idle thread. There's no useful work to be
418 * done, so just try to conserve power and have a
419 * low exit latency (ie sit in a loop waiting for
420 * somebody to say that they'd like to reschedule)
421 */
422void cpu_idle(void)
423{
424 /*
425 * If we're the non-boot CPU, nothing set the stack canary up
426 * for us. CPU0 already has it initialized but no harm in
427 * doing it again. This is a good place for updating it, as
428 * we wont ever return from this function (so the invalid
429 * canaries already on the stack wont ever trigger).
430 */
431 boot_init_stack_canary();
432 current_thread_info()->status |= TS_POLLING;
433
434 while (1) {
435 tick_nohz_idle_enter();
436
437 while (!need_resched()) {
438 rmb();
439
440 if (cpu_is_offline(smp_processor_id()))
441 play_dead();
442
443 /*
444 * Idle routines should keep interrupts disabled
445 * from here on, until they go to idle.
446 * Otherwise, idle callbacks can misfire.
447 */
448 local_touch_nmi();
449 local_irq_disable();
450
451 enter_idle();
452
453 /* Don't trace irqs off for idle */
454 stop_critical_timings();
455
456 /* enter_idle() needs rcu for notifiers */
457 rcu_idle_enter();
458
459 if (cpuidle_idle_call())
460 pm_idle();
461
462 rcu_idle_exit();
463 start_critical_timings();
464
465 /* In many cases the interrupt that ended idle
466 has already called exit_idle. But some idle
467 loops can be woken up without interrupt. */
468 __exit_idle();
469 }
470
471 tick_nohz_idle_exit();
472 preempt_enable_no_resched();
473 schedule();
474 preempt_disable();
475 }
476}
477
478/*
479 * We use this if we don't have any better
480 * idle routine..
481 */
482void default_idle(void)
483{
484 if (hlt_use_halt()) {
485 trace_power_start_rcuidle(POWER_CSTATE, 1, smp_processor_id());
486 trace_cpu_idle_rcuidle(1, smp_processor_id());
487 current_thread_info()->status &= ~TS_POLLING;
488 /*
489 * TS_POLLING-cleared state must be visible before we
490 * test NEED_RESCHED:
491 */
492 smp_mb();
493
494 if (!need_resched())
495 safe_halt(); /* enables interrupts racelessly */
496 else
497 local_irq_enable();
498 current_thread_info()->status |= TS_POLLING;
499 trace_power_end_rcuidle(smp_processor_id());
500 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
501 } else {
502 local_irq_enable();
503 /* loop is done by the caller */
504 cpu_relax();
505 }
506}
507#ifdef CONFIG_APM_MODULE
508EXPORT_SYMBOL(default_idle);
509#endif
510
511bool set_pm_idle_to_default(void)
512{
513 bool ret = !!pm_idle;
514
515 pm_idle = default_idle;
516
517 return ret;
518}
519void stop_this_cpu(void *dummy)
520{
521 local_irq_disable();
522 /*
523 * Remove this CPU:
524 */
525 set_cpu_online(smp_processor_id(), false);
526 disable_local_APIC();
527
528 for (;;) {
529 if (hlt_works(smp_processor_id()))
530 halt();
531 }
532}
533
534/* Default MONITOR/MWAIT with no hints, used for default C1 state */
535static void mwait_idle(void)
536{
537 if (!need_resched()) {
538 trace_power_start_rcuidle(POWER_CSTATE, 1, smp_processor_id());
539 trace_cpu_idle_rcuidle(1, smp_processor_id());
540 if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR))
541 clflush((void *)¤t_thread_info()->flags);
542
543 __monitor((void *)¤t_thread_info()->flags, 0, 0);
544 smp_mb();
545 if (!need_resched())
546 __sti_mwait(0, 0);
547 else
548 local_irq_enable();
549 trace_power_end_rcuidle(smp_processor_id());
550 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
551 } else
552 local_irq_enable();
553}
554
555/*
556 * On SMP it's slightly faster (but much more power-consuming!)
557 * to poll the ->work.need_resched flag instead of waiting for the
558 * cross-CPU IPI to arrive. Use this option with caution.
559 */
560static void poll_idle(void)
561{
562 trace_power_start_rcuidle(POWER_CSTATE, 0, smp_processor_id());
563 trace_cpu_idle_rcuidle(0, smp_processor_id());
564 local_irq_enable();
565 while (!need_resched())
566 cpu_relax();
567 trace_power_end_rcuidle(smp_processor_id());
568 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
569}
570
571/*
572 * mwait selection logic:
573 *
574 * It depends on the CPU. For AMD CPUs that support MWAIT this is
575 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
576 * then depend on a clock divisor and current Pstate of the core. If
577 * all cores of a processor are in halt state (C1) the processor can
578 * enter the C1E (C1 enhanced) state. If mwait is used this will never
579 * happen.
580 *
581 * idle=mwait overrides this decision and forces the usage of mwait.
582 */
583
584#define MWAIT_INFO 0x05
585#define MWAIT_ECX_EXTENDED_INFO 0x01
586#define MWAIT_EDX_C1 0xf0
587
588int mwait_usable(const struct cpuinfo_x86 *c)
589{
590 u32 eax, ebx, ecx, edx;
591
592 /* Use mwait if idle=mwait boot option is given */
593 if (boot_option_idle_override == IDLE_FORCE_MWAIT)
594 return 1;
595
596 /*
597 * Any idle= boot option other than idle=mwait means that we must not
598 * use mwait. Eg: idle=halt or idle=poll or idle=nomwait
599 */
600 if (boot_option_idle_override != IDLE_NO_OVERRIDE)
601 return 0;
602
603 if (c->cpuid_level < MWAIT_INFO)
604 return 0;
605
606 cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
607 /* Check, whether EDX has extended info about MWAIT */
608 if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
609 return 1;
610
611 /*
612 * edx enumeratios MONITOR/MWAIT extensions. Check, whether
613 * C1 supports MWAIT
614 */
615 return (edx & MWAIT_EDX_C1);
616}
617
618bool amd_e400_c1e_detected;
619EXPORT_SYMBOL(amd_e400_c1e_detected);
620
621static cpumask_var_t amd_e400_c1e_mask;
622
623void amd_e400_remove_cpu(int cpu)
624{
625 if (amd_e400_c1e_mask != NULL)
626 cpumask_clear_cpu(cpu, amd_e400_c1e_mask);
627}
628
629/*
630 * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
631 * pending message MSR. If we detect C1E, then we handle it the same
632 * way as C3 power states (local apic timer and TSC stop)
633 */
634static void amd_e400_idle(void)
635{
636 if (need_resched())
637 return;
638
639 if (!amd_e400_c1e_detected) {
640 u32 lo, hi;
641
642 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
643
644 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
645 amd_e400_c1e_detected = true;
646 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
647 mark_tsc_unstable("TSC halt in AMD C1E");
648 printk(KERN_INFO "System has AMD C1E enabled\n");
649 }
650 }
651
652 if (amd_e400_c1e_detected) {
653 int cpu = smp_processor_id();
654
655 if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) {
656 cpumask_set_cpu(cpu, amd_e400_c1e_mask);
657 /*
658 * Force broadcast so ACPI can not interfere.
659 */
660 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
661 &cpu);
662 printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
663 cpu);
664 }
665 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
666
667 default_idle();
668
669 /*
670 * The switch back from broadcast mode needs to be
671 * called with interrupts disabled.
672 */
673 local_irq_disable();
674 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
675 local_irq_enable();
676 } else
677 default_idle();
678}
679
680void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
681{
682#ifdef CONFIG_SMP
683 if (pm_idle == poll_idle && smp_num_siblings > 1) {
684 printk_once(KERN_WARNING "WARNING: polling idle and HT enabled,"
685 " performance may degrade.\n");
686 }
687#endif
688 if (pm_idle)
689 return;
690
691 if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
692 /*
693 * One CPU supports mwait => All CPUs supports mwait
694 */
695 printk(KERN_INFO "using mwait in idle threads.\n");
696 pm_idle = mwait_idle;
697 } else if (cpu_has_amd_erratum(amd_erratum_400)) {
698 /* E400: APIC timer interrupt does not wake up CPU from C1e */
699 printk(KERN_INFO "using AMD E400 aware idle routine\n");
700 pm_idle = amd_e400_idle;
701 } else
702 pm_idle = default_idle;
703}
704
705void __init init_amd_e400_c1e_mask(void)
706{
707 /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
708 if (pm_idle == amd_e400_idle)
709 zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL);
710}
711
712static int __init idle_setup(char *str)
713{
714 if (!str)
715 return -EINVAL;
716
717 if (!strcmp(str, "poll")) {
718 printk("using polling idle threads.\n");
719 pm_idle = poll_idle;
720 boot_option_idle_override = IDLE_POLL;
721 } else if (!strcmp(str, "mwait")) {
722 boot_option_idle_override = IDLE_FORCE_MWAIT;
723 WARN_ONCE(1, "\"idle=mwait\" will be removed in 2012\n");
724 } else if (!strcmp(str, "halt")) {
725 /*
726 * When the boot option of idle=halt is added, halt is
727 * forced to be used for CPU idle. In such case CPU C2/C3
728 * won't be used again.
729 * To continue to load the CPU idle driver, don't touch
730 * the boot_option_idle_override.
731 */
732 pm_idle = default_idle;
733 boot_option_idle_override = IDLE_HALT;
734 } else if (!strcmp(str, "nomwait")) {
735 /*
736 * If the boot option of "idle=nomwait" is added,
737 * it means that mwait will be disabled for CPU C2/C3
738 * states. In such case it won't touch the variable
739 * of boot_option_idle_override.
740 */
741 boot_option_idle_override = IDLE_NOMWAIT;
742 } else
743 return -1;
744
745 return 0;
746}
747early_param("idle", idle_setup);
748
749unsigned long arch_align_stack(unsigned long sp)
750{
751 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
752 sp -= get_random_int() % 8192;
753 return sp & ~0xf;
754}
755
756unsigned long arch_randomize_brk(struct mm_struct *mm)
757{
758 unsigned long range_end = mm->brk + 0x02000000;
759 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
760}
761
1#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
2
3#include <linux/errno.h>
4#include <linux/kernel.h>
5#include <linux/mm.h>
6#include <linux/smp.h>
7#include <linux/prctl.h>
8#include <linux/slab.h>
9#include <linux/sched.h>
10#include <linux/module.h>
11#include <linux/pm.h>
12#include <linux/tick.h>
13#include <linux/random.h>
14#include <linux/user-return-notifier.h>
15#include <linux/dmi.h>
16#include <linux/utsname.h>
17#include <linux/stackprotector.h>
18#include <linux/tick.h>
19#include <linux/cpuidle.h>
20#include <trace/events/power.h>
21#include <linux/hw_breakpoint.h>
22#include <asm/cpu.h>
23#include <asm/apic.h>
24#include <asm/syscalls.h>
25#include <asm/idle.h>
26#include <asm/uaccess.h>
27#include <asm/mwait.h>
28#include <asm/fpu/internal.h>
29#include <asm/debugreg.h>
30#include <asm/nmi.h>
31#include <asm/tlbflush.h>
32#include <asm/mce.h>
33#include <asm/vm86.h>
34
35/*
36 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
37 * no more per-task TSS's. The TSS size is kept cacheline-aligned
38 * so they are allowed to end up in the .data..cacheline_aligned
39 * section. Since TSS's are completely CPU-local, we want them
40 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
41 */
42__visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = {
43 .x86_tss = {
44 .sp0 = TOP_OF_INIT_STACK,
45#ifdef CONFIG_X86_32
46 .ss0 = __KERNEL_DS,
47 .ss1 = __KERNEL_CS,
48 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,
49#endif
50 },
51#ifdef CONFIG_X86_32
52 /*
53 * Note that the .io_bitmap member must be extra-big. This is because
54 * the CPU will access an additional byte beyond the end of the IO
55 * permission bitmap. The extra byte must be all 1 bits, and must
56 * be within the limit.
57 */
58 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 },
59#endif
60#ifdef CONFIG_X86_32
61 .SYSENTER_stack_canary = STACK_END_MAGIC,
62#endif
63};
64EXPORT_PER_CPU_SYMBOL(cpu_tss);
65
66#ifdef CONFIG_X86_64
67static DEFINE_PER_CPU(unsigned char, is_idle);
68static ATOMIC_NOTIFIER_HEAD(idle_notifier);
69
70void idle_notifier_register(struct notifier_block *n)
71{
72 atomic_notifier_chain_register(&idle_notifier, n);
73}
74EXPORT_SYMBOL_GPL(idle_notifier_register);
75
76void idle_notifier_unregister(struct notifier_block *n)
77{
78 atomic_notifier_chain_unregister(&idle_notifier, n);
79}
80EXPORT_SYMBOL_GPL(idle_notifier_unregister);
81#endif
82
83/*
84 * this gets called so that we can store lazy state into memory and copy the
85 * current task into the new thread.
86 */
87int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
88{
89 memcpy(dst, src, arch_task_struct_size);
90#ifdef CONFIG_VM86
91 dst->thread.vm86 = NULL;
92#endif
93
94 return fpu__copy(&dst->thread.fpu, &src->thread.fpu);
95}
96
97/*
98 * Free current thread data structures etc..
99 */
100void exit_thread(void)
101{
102 struct task_struct *me = current;
103 struct thread_struct *t = &me->thread;
104 unsigned long *bp = t->io_bitmap_ptr;
105 struct fpu *fpu = &t->fpu;
106
107 if (bp) {
108 struct tss_struct *tss = &per_cpu(cpu_tss, get_cpu());
109
110 t->io_bitmap_ptr = NULL;
111 clear_thread_flag(TIF_IO_BITMAP);
112 /*
113 * Careful, clear this in the TSS too:
114 */
115 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
116 t->io_bitmap_max = 0;
117 put_cpu();
118 kfree(bp);
119 }
120
121 free_vm86(t);
122
123 fpu__drop(fpu);
124}
125
126void flush_thread(void)
127{
128 struct task_struct *tsk = current;
129
130 flush_ptrace_hw_breakpoint(tsk);
131 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
132
133 fpu__clear(&tsk->thread.fpu);
134}
135
136static void hard_disable_TSC(void)
137{
138 cr4_set_bits(X86_CR4_TSD);
139}
140
141void disable_TSC(void)
142{
143 preempt_disable();
144 if (!test_and_set_thread_flag(TIF_NOTSC))
145 /*
146 * Must flip the CPU state synchronously with
147 * TIF_NOTSC in the current running context.
148 */
149 hard_disable_TSC();
150 preempt_enable();
151}
152
153static void hard_enable_TSC(void)
154{
155 cr4_clear_bits(X86_CR4_TSD);
156}
157
158static void enable_TSC(void)
159{
160 preempt_disable();
161 if (test_and_clear_thread_flag(TIF_NOTSC))
162 /*
163 * Must flip the CPU state synchronously with
164 * TIF_NOTSC in the current running context.
165 */
166 hard_enable_TSC();
167 preempt_enable();
168}
169
170int get_tsc_mode(unsigned long adr)
171{
172 unsigned int val;
173
174 if (test_thread_flag(TIF_NOTSC))
175 val = PR_TSC_SIGSEGV;
176 else
177 val = PR_TSC_ENABLE;
178
179 return put_user(val, (unsigned int __user *)adr);
180}
181
182int set_tsc_mode(unsigned int val)
183{
184 if (val == PR_TSC_SIGSEGV)
185 disable_TSC();
186 else if (val == PR_TSC_ENABLE)
187 enable_TSC();
188 else
189 return -EINVAL;
190
191 return 0;
192}
193
194void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
195 struct tss_struct *tss)
196{
197 struct thread_struct *prev, *next;
198
199 prev = &prev_p->thread;
200 next = &next_p->thread;
201
202 if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
203 test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
204 unsigned long debugctl = get_debugctlmsr();
205
206 debugctl &= ~DEBUGCTLMSR_BTF;
207 if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
208 debugctl |= DEBUGCTLMSR_BTF;
209
210 update_debugctlmsr(debugctl);
211 }
212
213 if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
214 test_tsk_thread_flag(next_p, TIF_NOTSC)) {
215 /* prev and next are different */
216 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
217 hard_disable_TSC();
218 else
219 hard_enable_TSC();
220 }
221
222 if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
223 /*
224 * Copy the relevant range of the IO bitmap.
225 * Normally this is 128 bytes or less:
226 */
227 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
228 max(prev->io_bitmap_max, next->io_bitmap_max));
229 } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
230 /*
231 * Clear any possible leftover bits:
232 */
233 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
234 }
235 propagate_user_return_notify(prev_p, next_p);
236}
237
238/*
239 * Idle related variables and functions
240 */
241unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
242EXPORT_SYMBOL(boot_option_idle_override);
243
244static void (*x86_idle)(void);
245
246#ifndef CONFIG_SMP
247static inline void play_dead(void)
248{
249 BUG();
250}
251#endif
252
253#ifdef CONFIG_X86_64
254void enter_idle(void)
255{
256 this_cpu_write(is_idle, 1);
257 atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL);
258}
259
260static void __exit_idle(void)
261{
262 if (x86_test_and_clear_bit_percpu(0, is_idle) == 0)
263 return;
264 atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL);
265}
266
267/* Called from interrupts to signify idle end */
268void exit_idle(void)
269{
270 /* idle loop has pid 0 */
271 if (current->pid)
272 return;
273 __exit_idle();
274}
275#endif
276
277void arch_cpu_idle_enter(void)
278{
279 local_touch_nmi();
280 enter_idle();
281}
282
283void arch_cpu_idle_exit(void)
284{
285 __exit_idle();
286}
287
288void arch_cpu_idle_dead(void)
289{
290 play_dead();
291}
292
293/*
294 * Called from the generic idle code.
295 */
296void arch_cpu_idle(void)
297{
298 x86_idle();
299}
300
301/*
302 * We use this if we don't have any better idle routine..
303 */
304void default_idle(void)
305{
306 trace_cpu_idle_rcuidle(1, smp_processor_id());
307 safe_halt();
308 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
309}
310#ifdef CONFIG_APM_MODULE
311EXPORT_SYMBOL(default_idle);
312#endif
313
314#ifdef CONFIG_XEN
315bool xen_set_default_idle(void)
316{
317 bool ret = !!x86_idle;
318
319 x86_idle = default_idle;
320
321 return ret;
322}
323#endif
324void stop_this_cpu(void *dummy)
325{
326 local_irq_disable();
327 /*
328 * Remove this CPU:
329 */
330 set_cpu_online(smp_processor_id(), false);
331 disable_local_APIC();
332 mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
333
334 for (;;)
335 halt();
336}
337
338bool amd_e400_c1e_detected;
339EXPORT_SYMBOL(amd_e400_c1e_detected);
340
341static cpumask_var_t amd_e400_c1e_mask;
342
343void amd_e400_remove_cpu(int cpu)
344{
345 if (amd_e400_c1e_mask != NULL)
346 cpumask_clear_cpu(cpu, amd_e400_c1e_mask);
347}
348
349/*
350 * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
351 * pending message MSR. If we detect C1E, then we handle it the same
352 * way as C3 power states (local apic timer and TSC stop)
353 */
354static void amd_e400_idle(void)
355{
356 if (!amd_e400_c1e_detected) {
357 u32 lo, hi;
358
359 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
360
361 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
362 amd_e400_c1e_detected = true;
363 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
364 mark_tsc_unstable("TSC halt in AMD C1E");
365 pr_info("System has AMD C1E enabled\n");
366 }
367 }
368
369 if (amd_e400_c1e_detected) {
370 int cpu = smp_processor_id();
371
372 if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) {
373 cpumask_set_cpu(cpu, amd_e400_c1e_mask);
374 /* Force broadcast so ACPI can not interfere. */
375 tick_broadcast_force();
376 pr_info("Switch to broadcast mode on CPU%d\n", cpu);
377 }
378 tick_broadcast_enter();
379
380 default_idle();
381
382 /*
383 * The switch back from broadcast mode needs to be
384 * called with interrupts disabled.
385 */
386 local_irq_disable();
387 tick_broadcast_exit();
388 local_irq_enable();
389 } else
390 default_idle();
391}
392
393/*
394 * Intel Core2 and older machines prefer MWAIT over HALT for C1.
395 * We can't rely on cpuidle installing MWAIT, because it will not load
396 * on systems that support only C1 -- so the boot default must be MWAIT.
397 *
398 * Some AMD machines are the opposite, they depend on using HALT.
399 *
400 * So for default C1, which is used during boot until cpuidle loads,
401 * use MWAIT-C1 on Intel HW that has it, else use HALT.
402 */
403static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
404{
405 if (c->x86_vendor != X86_VENDOR_INTEL)
406 return 0;
407
408 if (!cpu_has(c, X86_FEATURE_MWAIT))
409 return 0;
410
411 return 1;
412}
413
414/*
415 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
416 * with interrupts enabled and no flags, which is backwards compatible with the
417 * original MWAIT implementation.
418 */
419static void mwait_idle(void)
420{
421 if (!current_set_polling_and_test()) {
422 trace_cpu_idle_rcuidle(1, smp_processor_id());
423 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
424 mb(); /* quirk */
425 clflush((void *)¤t_thread_info()->flags);
426 mb(); /* quirk */
427 }
428
429 __monitor((void *)¤t_thread_info()->flags, 0, 0);
430 if (!need_resched())
431 __sti_mwait(0, 0);
432 else
433 local_irq_enable();
434 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
435 } else {
436 local_irq_enable();
437 }
438 __current_clr_polling();
439}
440
441void select_idle_routine(const struct cpuinfo_x86 *c)
442{
443#ifdef CONFIG_SMP
444 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
445 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
446#endif
447 if (x86_idle || boot_option_idle_override == IDLE_POLL)
448 return;
449
450 if (cpu_has_bug(c, X86_BUG_AMD_APIC_C1E)) {
451 /* E400: APIC timer interrupt does not wake up CPU from C1e */
452 pr_info("using AMD E400 aware idle routine\n");
453 x86_idle = amd_e400_idle;
454 } else if (prefer_mwait_c1_over_halt(c)) {
455 pr_info("using mwait in idle threads\n");
456 x86_idle = mwait_idle;
457 } else
458 x86_idle = default_idle;
459}
460
461void __init init_amd_e400_c1e_mask(void)
462{
463 /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
464 if (x86_idle == amd_e400_idle)
465 zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL);
466}
467
468static int __init idle_setup(char *str)
469{
470 if (!str)
471 return -EINVAL;
472
473 if (!strcmp(str, "poll")) {
474 pr_info("using polling idle threads\n");
475 boot_option_idle_override = IDLE_POLL;
476 cpu_idle_poll_ctrl(true);
477 } else if (!strcmp(str, "halt")) {
478 /*
479 * When the boot option of idle=halt is added, halt is
480 * forced to be used for CPU idle. In such case CPU C2/C3
481 * won't be used again.
482 * To continue to load the CPU idle driver, don't touch
483 * the boot_option_idle_override.
484 */
485 x86_idle = default_idle;
486 boot_option_idle_override = IDLE_HALT;
487 } else if (!strcmp(str, "nomwait")) {
488 /*
489 * If the boot option of "idle=nomwait" is added,
490 * it means that mwait will be disabled for CPU C2/C3
491 * states. In such case it won't touch the variable
492 * of boot_option_idle_override.
493 */
494 boot_option_idle_override = IDLE_NOMWAIT;
495 } else
496 return -1;
497
498 return 0;
499}
500early_param("idle", idle_setup);
501
502unsigned long arch_align_stack(unsigned long sp)
503{
504 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
505 sp -= get_random_int() % 8192;
506 return sp & ~0xf;
507}
508
509unsigned long arch_randomize_brk(struct mm_struct *mm)
510{
511 unsigned long range_end = mm->brk + 0x02000000;
512 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
513}
514
515/*
516 * Called from fs/proc with a reference on @p to find the function
517 * which called into schedule(). This needs to be done carefully
518 * because the task might wake up and we might look at a stack
519 * changing under us.
520 */
521unsigned long get_wchan(struct task_struct *p)
522{
523 unsigned long start, bottom, top, sp, fp, ip;
524 int count = 0;
525
526 if (!p || p == current || p->state == TASK_RUNNING)
527 return 0;
528
529 start = (unsigned long)task_stack_page(p);
530 if (!start)
531 return 0;
532
533 /*
534 * Layout of the stack page:
535 *
536 * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
537 * PADDING
538 * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
539 * stack
540 * ----------- bottom = start + sizeof(thread_info)
541 * thread_info
542 * ----------- start
543 *
544 * The tasks stack pointer points at the location where the
545 * framepointer is stored. The data on the stack is:
546 * ... IP FP ... IP FP
547 *
548 * We need to read FP and IP, so we need to adjust the upper
549 * bound by another unsigned long.
550 */
551 top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
552 top -= 2 * sizeof(unsigned long);
553 bottom = start + sizeof(struct thread_info);
554
555 sp = READ_ONCE(p->thread.sp);
556 if (sp < bottom || sp > top)
557 return 0;
558
559 fp = READ_ONCE_NOCHECK(*(unsigned long *)sp);
560 do {
561 if (fp < bottom || fp > top)
562 return 0;
563 ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
564 if (!in_sched_functions(ip))
565 return ip;
566 fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
567 } while (count++ < 16 && p->state != TASK_RUNNING);
568 return 0;
569}