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1#include <linux/clocksource.h>
2#include <linux/clockchips.h>
3#include <linux/interrupt.h>
4#include <linux/export.h>
5#include <linux/delay.h>
6#include <linux/errno.h>
7#include <linux/i8253.h>
8#include <linux/slab.h>
9#include <linux/hpet.h>
10#include <linux/init.h>
11#include <linux/cpu.h>
12#include <linux/pm.h>
13#include <linux/io.h>
14
15#include <asm/fixmap.h>
16#include <asm/hpet.h>
17#include <asm/time.h>
18
19#define HPET_MASK CLOCKSOURCE_MASK(32)
20
21/* FSEC = 10^-15
22 NSEC = 10^-9 */
23#define FSEC_PER_NSEC 1000000L
24
25#define HPET_DEV_USED_BIT 2
26#define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
27#define HPET_DEV_VALID 0x8
28#define HPET_DEV_FSB_CAP 0x1000
29#define HPET_DEV_PERI_CAP 0x2000
30
31#define HPET_MIN_CYCLES 128
32#define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
33
34/*
35 * HPET address is set in acpi/boot.c, when an ACPI entry exists
36 */
37unsigned long hpet_address;
38u8 hpet_blockid; /* OS timer block num */
39u8 hpet_msi_disable;
40
41#ifdef CONFIG_PCI_MSI
42static unsigned long hpet_num_timers;
43#endif
44static void __iomem *hpet_virt_address;
45
46struct hpet_dev {
47 struct clock_event_device evt;
48 unsigned int num;
49 int cpu;
50 unsigned int irq;
51 unsigned int flags;
52 char name[10];
53};
54
55inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev)
56{
57 return container_of(evtdev, struct hpet_dev, evt);
58}
59
60inline unsigned int hpet_readl(unsigned int a)
61{
62 return readl(hpet_virt_address + a);
63}
64
65static inline void hpet_writel(unsigned int d, unsigned int a)
66{
67 writel(d, hpet_virt_address + a);
68}
69
70#ifdef CONFIG_X86_64
71#include <asm/pgtable.h>
72#endif
73
74static inline void hpet_set_mapping(void)
75{
76 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
77#ifdef CONFIG_X86_64
78 __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VVAR_NOCACHE);
79#endif
80}
81
82static inline void hpet_clear_mapping(void)
83{
84 iounmap(hpet_virt_address);
85 hpet_virt_address = NULL;
86}
87
88/*
89 * HPET command line enable / disable
90 */
91static int boot_hpet_disable;
92int hpet_force_user;
93static int hpet_verbose;
94
95static int __init hpet_setup(char *str)
96{
97 while (str) {
98 char *next = strchr(str, ',');
99
100 if (next)
101 *next++ = 0;
102 if (!strncmp("disable", str, 7))
103 boot_hpet_disable = 1;
104 if (!strncmp("force", str, 5))
105 hpet_force_user = 1;
106 if (!strncmp("verbose", str, 7))
107 hpet_verbose = 1;
108 str = next;
109 }
110 return 1;
111}
112__setup("hpet=", hpet_setup);
113
114static int __init disable_hpet(char *str)
115{
116 boot_hpet_disable = 1;
117 return 1;
118}
119__setup("nohpet", disable_hpet);
120
121static inline int is_hpet_capable(void)
122{
123 return !boot_hpet_disable && hpet_address;
124}
125
126/*
127 * HPET timer interrupt enable / disable
128 */
129static int hpet_legacy_int_enabled;
130
131/**
132 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
133 */
134int is_hpet_enabled(void)
135{
136 return is_hpet_capable() && hpet_legacy_int_enabled;
137}
138EXPORT_SYMBOL_GPL(is_hpet_enabled);
139
140static void _hpet_print_config(const char *function, int line)
141{
142 u32 i, timers, l, h;
143 printk(KERN_INFO "hpet: %s(%d):\n", function, line);
144 l = hpet_readl(HPET_ID);
145 h = hpet_readl(HPET_PERIOD);
146 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
147 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
148 l = hpet_readl(HPET_CFG);
149 h = hpet_readl(HPET_STATUS);
150 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
151 l = hpet_readl(HPET_COUNTER);
152 h = hpet_readl(HPET_COUNTER+4);
153 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
154
155 for (i = 0; i < timers; i++) {
156 l = hpet_readl(HPET_Tn_CFG(i));
157 h = hpet_readl(HPET_Tn_CFG(i)+4);
158 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
159 i, l, h);
160 l = hpet_readl(HPET_Tn_CMP(i));
161 h = hpet_readl(HPET_Tn_CMP(i)+4);
162 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
163 i, l, h);
164 l = hpet_readl(HPET_Tn_ROUTE(i));
165 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
166 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
167 i, l, h);
168 }
169}
170
171#define hpet_print_config() \
172do { \
173 if (hpet_verbose) \
174 _hpet_print_config(__FUNCTION__, __LINE__); \
175} while (0)
176
177/*
178 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
179 * timer 0 and timer 1 in case of RTC emulation.
180 */
181#ifdef CONFIG_HPET
182
183static void hpet_reserve_msi_timers(struct hpet_data *hd);
184
185static void hpet_reserve_platform_timers(unsigned int id)
186{
187 struct hpet __iomem *hpet = hpet_virt_address;
188 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
189 unsigned int nrtimers, i;
190 struct hpet_data hd;
191
192 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
193
194 memset(&hd, 0, sizeof(hd));
195 hd.hd_phys_address = hpet_address;
196 hd.hd_address = hpet;
197 hd.hd_nirqs = nrtimers;
198 hpet_reserve_timer(&hd, 0);
199
200#ifdef CONFIG_HPET_EMULATE_RTC
201 hpet_reserve_timer(&hd, 1);
202#endif
203
204 /*
205 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
206 * is wrong for i8259!) not the output IRQ. Many BIOS writers
207 * don't bother configuring *any* comparator interrupts.
208 */
209 hd.hd_irq[0] = HPET_LEGACY_8254;
210 hd.hd_irq[1] = HPET_LEGACY_RTC;
211
212 for (i = 2; i < nrtimers; timer++, i++) {
213 hd.hd_irq[i] = (readl(&timer->hpet_config) &
214 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
215 }
216
217 hpet_reserve_msi_timers(&hd);
218
219 hpet_alloc(&hd);
220
221}
222#else
223static void hpet_reserve_platform_timers(unsigned int id) { }
224#endif
225
226/*
227 * Common hpet info
228 */
229static unsigned long hpet_freq;
230
231static void hpet_legacy_set_mode(enum clock_event_mode mode,
232 struct clock_event_device *evt);
233static int hpet_legacy_next_event(unsigned long delta,
234 struct clock_event_device *evt);
235
236/*
237 * The hpet clock event device
238 */
239static struct clock_event_device hpet_clockevent = {
240 .name = "hpet",
241 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
242 .set_mode = hpet_legacy_set_mode,
243 .set_next_event = hpet_legacy_next_event,
244 .irq = 0,
245 .rating = 50,
246};
247
248static void hpet_stop_counter(void)
249{
250 unsigned long cfg = hpet_readl(HPET_CFG);
251 cfg &= ~HPET_CFG_ENABLE;
252 hpet_writel(cfg, HPET_CFG);
253}
254
255static void hpet_reset_counter(void)
256{
257 hpet_writel(0, HPET_COUNTER);
258 hpet_writel(0, HPET_COUNTER + 4);
259}
260
261static void hpet_start_counter(void)
262{
263 unsigned int cfg = hpet_readl(HPET_CFG);
264 cfg |= HPET_CFG_ENABLE;
265 hpet_writel(cfg, HPET_CFG);
266}
267
268static void hpet_restart_counter(void)
269{
270 hpet_stop_counter();
271 hpet_reset_counter();
272 hpet_start_counter();
273}
274
275static void hpet_resume_device(void)
276{
277 force_hpet_resume();
278}
279
280static void hpet_resume_counter(struct clocksource *cs)
281{
282 hpet_resume_device();
283 hpet_restart_counter();
284}
285
286static void hpet_enable_legacy_int(void)
287{
288 unsigned int cfg = hpet_readl(HPET_CFG);
289
290 cfg |= HPET_CFG_LEGACY;
291 hpet_writel(cfg, HPET_CFG);
292 hpet_legacy_int_enabled = 1;
293}
294
295static void hpet_legacy_clockevent_register(void)
296{
297 /* Start HPET legacy interrupts */
298 hpet_enable_legacy_int();
299
300 /*
301 * Start hpet with the boot cpu mask and make it
302 * global after the IO_APIC has been initialized.
303 */
304 hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
305 clockevents_config_and_register(&hpet_clockevent, hpet_freq,
306 HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
307 global_clock_event = &hpet_clockevent;
308 printk(KERN_DEBUG "hpet clockevent registered\n");
309}
310
311static int hpet_setup_msi_irq(unsigned int irq);
312
313static void hpet_set_mode(enum clock_event_mode mode,
314 struct clock_event_device *evt, int timer)
315{
316 unsigned int cfg, cmp, now;
317 uint64_t delta;
318
319 switch (mode) {
320 case CLOCK_EVT_MODE_PERIODIC:
321 hpet_stop_counter();
322 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
323 delta >>= evt->shift;
324 now = hpet_readl(HPET_COUNTER);
325 cmp = now + (unsigned int) delta;
326 cfg = hpet_readl(HPET_Tn_CFG(timer));
327 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
328 HPET_TN_SETVAL | HPET_TN_32BIT;
329 hpet_writel(cfg, HPET_Tn_CFG(timer));
330 hpet_writel(cmp, HPET_Tn_CMP(timer));
331 udelay(1);
332 /*
333 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
334 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
335 * bit is automatically cleared after the first write.
336 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
337 * Publication # 24674)
338 */
339 hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer));
340 hpet_start_counter();
341 hpet_print_config();
342 break;
343
344 case CLOCK_EVT_MODE_ONESHOT:
345 cfg = hpet_readl(HPET_Tn_CFG(timer));
346 cfg &= ~HPET_TN_PERIODIC;
347 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
348 hpet_writel(cfg, HPET_Tn_CFG(timer));
349 break;
350
351 case CLOCK_EVT_MODE_UNUSED:
352 case CLOCK_EVT_MODE_SHUTDOWN:
353 cfg = hpet_readl(HPET_Tn_CFG(timer));
354 cfg &= ~HPET_TN_ENABLE;
355 hpet_writel(cfg, HPET_Tn_CFG(timer));
356 break;
357
358 case CLOCK_EVT_MODE_RESUME:
359 if (timer == 0) {
360 hpet_enable_legacy_int();
361 } else {
362 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
363 hpet_setup_msi_irq(hdev->irq);
364 disable_irq(hdev->irq);
365 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
366 enable_irq(hdev->irq);
367 }
368 hpet_print_config();
369 break;
370 }
371}
372
373static int hpet_next_event(unsigned long delta,
374 struct clock_event_device *evt, int timer)
375{
376 u32 cnt;
377 s32 res;
378
379 cnt = hpet_readl(HPET_COUNTER);
380 cnt += (u32) delta;
381 hpet_writel(cnt, HPET_Tn_CMP(timer));
382
383 /*
384 * HPETs are a complete disaster. The compare register is
385 * based on a equal comparison and neither provides a less
386 * than or equal functionality (which would require to take
387 * the wraparound into account) nor a simple count down event
388 * mode. Further the write to the comparator register is
389 * delayed internally up to two HPET clock cycles in certain
390 * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
391 * longer delays. We worked around that by reading back the
392 * compare register, but that required another workaround for
393 * ICH9,10 chips where the first readout after write can
394 * return the old stale value. We already had a minimum
395 * programming delta of 5us enforced, but a NMI or SMI hitting
396 * between the counter readout and the comparator write can
397 * move us behind that point easily. Now instead of reading
398 * the compare register back several times, we make the ETIME
399 * decision based on the following: Return ETIME if the
400 * counter value after the write is less than HPET_MIN_CYCLES
401 * away from the event or if the counter is already ahead of
402 * the event. The minimum programming delta for the generic
403 * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
404 */
405 res = (s32)(cnt - hpet_readl(HPET_COUNTER));
406
407 return res < HPET_MIN_CYCLES ? -ETIME : 0;
408}
409
410static void hpet_legacy_set_mode(enum clock_event_mode mode,
411 struct clock_event_device *evt)
412{
413 hpet_set_mode(mode, evt, 0);
414}
415
416static int hpet_legacy_next_event(unsigned long delta,
417 struct clock_event_device *evt)
418{
419 return hpet_next_event(delta, evt, 0);
420}
421
422/*
423 * HPET MSI Support
424 */
425#ifdef CONFIG_PCI_MSI
426
427static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
428static struct hpet_dev *hpet_devs;
429
430void hpet_msi_unmask(struct irq_data *data)
431{
432 struct hpet_dev *hdev = data->handler_data;
433 unsigned int cfg;
434
435 /* unmask it */
436 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
437 cfg |= HPET_TN_FSB;
438 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
439}
440
441void hpet_msi_mask(struct irq_data *data)
442{
443 struct hpet_dev *hdev = data->handler_data;
444 unsigned int cfg;
445
446 /* mask it */
447 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
448 cfg &= ~HPET_TN_FSB;
449 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
450}
451
452void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
453{
454 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
455 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
456}
457
458void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
459{
460 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
461 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
462 msg->address_hi = 0;
463}
464
465static void hpet_msi_set_mode(enum clock_event_mode mode,
466 struct clock_event_device *evt)
467{
468 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
469 hpet_set_mode(mode, evt, hdev->num);
470}
471
472static int hpet_msi_next_event(unsigned long delta,
473 struct clock_event_device *evt)
474{
475 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
476 return hpet_next_event(delta, evt, hdev->num);
477}
478
479static int hpet_setup_msi_irq(unsigned int irq)
480{
481 if (arch_setup_hpet_msi(irq, hpet_blockid)) {
482 destroy_irq(irq);
483 return -EINVAL;
484 }
485 return 0;
486}
487
488static int hpet_assign_irq(struct hpet_dev *dev)
489{
490 unsigned int irq;
491
492 irq = create_irq_nr(0, -1);
493 if (!irq)
494 return -EINVAL;
495
496 irq_set_handler_data(irq, dev);
497
498 if (hpet_setup_msi_irq(irq))
499 return -EINVAL;
500
501 dev->irq = irq;
502 return 0;
503}
504
505static irqreturn_t hpet_interrupt_handler(int irq, void *data)
506{
507 struct hpet_dev *dev = (struct hpet_dev *)data;
508 struct clock_event_device *hevt = &dev->evt;
509
510 if (!hevt->event_handler) {
511 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
512 dev->num);
513 return IRQ_HANDLED;
514 }
515
516 hevt->event_handler(hevt);
517 return IRQ_HANDLED;
518}
519
520static int hpet_setup_irq(struct hpet_dev *dev)
521{
522
523 if (request_irq(dev->irq, hpet_interrupt_handler,
524 IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING,
525 dev->name, dev))
526 return -1;
527
528 disable_irq(dev->irq);
529 irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
530 enable_irq(dev->irq);
531
532 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
533 dev->name, dev->irq);
534
535 return 0;
536}
537
538/* This should be called in specific @cpu */
539static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
540{
541 struct clock_event_device *evt = &hdev->evt;
542
543 WARN_ON(cpu != smp_processor_id());
544 if (!(hdev->flags & HPET_DEV_VALID))
545 return;
546
547 if (hpet_setup_msi_irq(hdev->irq))
548 return;
549
550 hdev->cpu = cpu;
551 per_cpu(cpu_hpet_dev, cpu) = hdev;
552 evt->name = hdev->name;
553 hpet_setup_irq(hdev);
554 evt->irq = hdev->irq;
555
556 evt->rating = 110;
557 evt->features = CLOCK_EVT_FEAT_ONESHOT;
558 if (hdev->flags & HPET_DEV_PERI_CAP)
559 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
560
561 evt->set_mode = hpet_msi_set_mode;
562 evt->set_next_event = hpet_msi_next_event;
563 evt->cpumask = cpumask_of(hdev->cpu);
564
565 clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
566 0x7FFFFFFF);
567}
568
569#ifdef CONFIG_HPET
570/* Reserve at least one timer for userspace (/dev/hpet) */
571#define RESERVE_TIMERS 1
572#else
573#define RESERVE_TIMERS 0
574#endif
575
576static void hpet_msi_capability_lookup(unsigned int start_timer)
577{
578 unsigned int id;
579 unsigned int num_timers;
580 unsigned int num_timers_used = 0;
581 int i;
582
583 if (hpet_msi_disable)
584 return;
585
586 if (boot_cpu_has(X86_FEATURE_ARAT))
587 return;
588 id = hpet_readl(HPET_ID);
589
590 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
591 num_timers++; /* Value read out starts from 0 */
592 hpet_print_config();
593
594 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
595 if (!hpet_devs)
596 return;
597
598 hpet_num_timers = num_timers;
599
600 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
601 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
602 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
603
604 /* Only consider HPET timer with MSI support */
605 if (!(cfg & HPET_TN_FSB_CAP))
606 continue;
607
608 hdev->flags = 0;
609 if (cfg & HPET_TN_PERIODIC_CAP)
610 hdev->flags |= HPET_DEV_PERI_CAP;
611 hdev->num = i;
612
613 sprintf(hdev->name, "hpet%d", i);
614 if (hpet_assign_irq(hdev))
615 continue;
616
617 hdev->flags |= HPET_DEV_FSB_CAP;
618 hdev->flags |= HPET_DEV_VALID;
619 num_timers_used++;
620 if (num_timers_used == num_possible_cpus())
621 break;
622 }
623
624 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
625 num_timers, num_timers_used);
626}
627
628#ifdef CONFIG_HPET
629static void hpet_reserve_msi_timers(struct hpet_data *hd)
630{
631 int i;
632
633 if (!hpet_devs)
634 return;
635
636 for (i = 0; i < hpet_num_timers; i++) {
637 struct hpet_dev *hdev = &hpet_devs[i];
638
639 if (!(hdev->flags & HPET_DEV_VALID))
640 continue;
641
642 hd->hd_irq[hdev->num] = hdev->irq;
643 hpet_reserve_timer(hd, hdev->num);
644 }
645}
646#endif
647
648static struct hpet_dev *hpet_get_unused_timer(void)
649{
650 int i;
651
652 if (!hpet_devs)
653 return NULL;
654
655 for (i = 0; i < hpet_num_timers; i++) {
656 struct hpet_dev *hdev = &hpet_devs[i];
657
658 if (!(hdev->flags & HPET_DEV_VALID))
659 continue;
660 if (test_and_set_bit(HPET_DEV_USED_BIT,
661 (unsigned long *)&hdev->flags))
662 continue;
663 return hdev;
664 }
665 return NULL;
666}
667
668struct hpet_work_struct {
669 struct delayed_work work;
670 struct completion complete;
671};
672
673static void hpet_work(struct work_struct *w)
674{
675 struct hpet_dev *hdev;
676 int cpu = smp_processor_id();
677 struct hpet_work_struct *hpet_work;
678
679 hpet_work = container_of(w, struct hpet_work_struct, work.work);
680
681 hdev = hpet_get_unused_timer();
682 if (hdev)
683 init_one_hpet_msi_clockevent(hdev, cpu);
684
685 complete(&hpet_work->complete);
686}
687
688static int hpet_cpuhp_notify(struct notifier_block *n,
689 unsigned long action, void *hcpu)
690{
691 unsigned long cpu = (unsigned long)hcpu;
692 struct hpet_work_struct work;
693 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
694
695 switch (action & 0xf) {
696 case CPU_ONLINE:
697 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work);
698 init_completion(&work.complete);
699 /* FIXME: add schedule_work_on() */
700 schedule_delayed_work_on(cpu, &work.work, 0);
701 wait_for_completion(&work.complete);
702 destroy_timer_on_stack(&work.work.timer);
703 break;
704 case CPU_DEAD:
705 if (hdev) {
706 free_irq(hdev->irq, hdev);
707 hdev->flags &= ~HPET_DEV_USED;
708 per_cpu(cpu_hpet_dev, cpu) = NULL;
709 }
710 break;
711 }
712 return NOTIFY_OK;
713}
714#else
715
716static int hpet_setup_msi_irq(unsigned int irq)
717{
718 return 0;
719}
720static void hpet_msi_capability_lookup(unsigned int start_timer)
721{
722 return;
723}
724
725#ifdef CONFIG_HPET
726static void hpet_reserve_msi_timers(struct hpet_data *hd)
727{
728 return;
729}
730#endif
731
732static int hpet_cpuhp_notify(struct notifier_block *n,
733 unsigned long action, void *hcpu)
734{
735 return NOTIFY_OK;
736}
737
738#endif
739
740/*
741 * Clock source related code
742 */
743static cycle_t read_hpet(struct clocksource *cs)
744{
745 return (cycle_t)hpet_readl(HPET_COUNTER);
746}
747
748static struct clocksource clocksource_hpet = {
749 .name = "hpet",
750 .rating = 250,
751 .read = read_hpet,
752 .mask = HPET_MASK,
753 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
754 .resume = hpet_resume_counter,
755#ifdef CONFIG_X86_64
756 .archdata = { .vclock_mode = VCLOCK_HPET },
757#endif
758};
759
760static int hpet_clocksource_register(void)
761{
762 u64 start, now;
763 cycle_t t1;
764
765 /* Start the counter */
766 hpet_restart_counter();
767
768 /* Verify whether hpet counter works */
769 t1 = hpet_readl(HPET_COUNTER);
770 rdtscll(start);
771
772 /*
773 * We don't know the TSC frequency yet, but waiting for
774 * 200000 TSC cycles is safe:
775 * 4 GHz == 50us
776 * 1 GHz == 200us
777 */
778 do {
779 rep_nop();
780 rdtscll(now);
781 } while ((now - start) < 200000UL);
782
783 if (t1 == hpet_readl(HPET_COUNTER)) {
784 printk(KERN_WARNING
785 "HPET counter not counting. HPET disabled\n");
786 return -ENODEV;
787 }
788
789 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
790 return 0;
791}
792
793static u32 *hpet_boot_cfg;
794
795/**
796 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
797 */
798int __init hpet_enable(void)
799{
800 u32 hpet_period, cfg, id;
801 u64 freq;
802 unsigned int i, last;
803
804 if (!is_hpet_capable())
805 return 0;
806
807 hpet_set_mapping();
808
809 /*
810 * Read the period and check for a sane value:
811 */
812 hpet_period = hpet_readl(HPET_PERIOD);
813
814 /*
815 * AMD SB700 based systems with spread spectrum enabled use a
816 * SMM based HPET emulation to provide proper frequency
817 * setting. The SMM code is initialized with the first HPET
818 * register access and takes some time to complete. During
819 * this time the config register reads 0xffffffff. We check
820 * for max. 1000 loops whether the config register reads a non
821 * 0xffffffff value to make sure that HPET is up and running
822 * before we go further. A counting loop is safe, as the HPET
823 * access takes thousands of CPU cycles. On non SB700 based
824 * machines this check is only done once and has no side
825 * effects.
826 */
827 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
828 if (i == 1000) {
829 printk(KERN_WARNING
830 "HPET config register value = 0xFFFFFFFF. "
831 "Disabling HPET\n");
832 goto out_nohpet;
833 }
834 }
835
836 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
837 goto out_nohpet;
838
839 /*
840 * The period is a femto seconds value. Convert it to a
841 * frequency.
842 */
843 freq = FSEC_PER_SEC;
844 do_div(freq, hpet_period);
845 hpet_freq = freq;
846
847 /*
848 * Read the HPET ID register to retrieve the IRQ routing
849 * information and the number of channels
850 */
851 id = hpet_readl(HPET_ID);
852 hpet_print_config();
853
854 last = (id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT;
855
856#ifdef CONFIG_HPET_EMULATE_RTC
857 /*
858 * The legacy routing mode needs at least two channels, tick timer
859 * and the rtc emulation channel.
860 */
861 if (!last)
862 goto out_nohpet;
863#endif
864
865 cfg = hpet_readl(HPET_CFG);
866 hpet_boot_cfg = kmalloc((last + 2) * sizeof(*hpet_boot_cfg),
867 GFP_KERNEL);
868 if (hpet_boot_cfg)
869 *hpet_boot_cfg = cfg;
870 else
871 pr_warn("HPET initial state will not be saved\n");
872 cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
873 hpet_writel(cfg, HPET_CFG);
874 if (cfg)
875 pr_warn("HPET: Unrecognized bits %#x set in global cfg\n",
876 cfg);
877
878 for (i = 0; i <= last; ++i) {
879 cfg = hpet_readl(HPET_Tn_CFG(i));
880 if (hpet_boot_cfg)
881 hpet_boot_cfg[i + 1] = cfg;
882 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB);
883 hpet_writel(cfg, HPET_Tn_CFG(i));
884 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP
885 | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE
886 | HPET_TN_FSB | HPET_TN_FSB_CAP);
887 if (cfg)
888 pr_warn("HPET: Unrecognized bits %#x set in cfg#%u\n",
889 cfg, i);
890 }
891 hpet_print_config();
892
893 if (hpet_clocksource_register())
894 goto out_nohpet;
895
896 if (id & HPET_ID_LEGSUP) {
897 hpet_legacy_clockevent_register();
898 return 1;
899 }
900 return 0;
901
902out_nohpet:
903 hpet_clear_mapping();
904 hpet_address = 0;
905 return 0;
906}
907
908/*
909 * Needs to be late, as the reserve_timer code calls kalloc !
910 *
911 * Not a problem on i386 as hpet_enable is called from late_time_init,
912 * but on x86_64 it is necessary !
913 */
914static __init int hpet_late_init(void)
915{
916 int cpu;
917
918 if (boot_hpet_disable)
919 return -ENODEV;
920
921 if (!hpet_address) {
922 if (!force_hpet_address)
923 return -ENODEV;
924
925 hpet_address = force_hpet_address;
926 hpet_enable();
927 }
928
929 if (!hpet_virt_address)
930 return -ENODEV;
931
932 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
933 hpet_msi_capability_lookup(2);
934 else
935 hpet_msi_capability_lookup(0);
936
937 hpet_reserve_platform_timers(hpet_readl(HPET_ID));
938 hpet_print_config();
939
940 if (hpet_msi_disable)
941 return 0;
942
943 if (boot_cpu_has(X86_FEATURE_ARAT))
944 return 0;
945
946 for_each_online_cpu(cpu) {
947 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
948 }
949
950 /* This notifier should be called after workqueue is ready */
951 hotcpu_notifier(hpet_cpuhp_notify, -20);
952
953 return 0;
954}
955fs_initcall(hpet_late_init);
956
957void hpet_disable(void)
958{
959 if (is_hpet_capable() && hpet_virt_address) {
960 unsigned int cfg = hpet_readl(HPET_CFG), id, last;
961
962 if (hpet_boot_cfg)
963 cfg = *hpet_boot_cfg;
964 else if (hpet_legacy_int_enabled) {
965 cfg &= ~HPET_CFG_LEGACY;
966 hpet_legacy_int_enabled = 0;
967 }
968 cfg &= ~HPET_CFG_ENABLE;
969 hpet_writel(cfg, HPET_CFG);
970
971 if (!hpet_boot_cfg)
972 return;
973
974 id = hpet_readl(HPET_ID);
975 last = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
976
977 for (id = 0; id <= last; ++id)
978 hpet_writel(hpet_boot_cfg[id + 1], HPET_Tn_CFG(id));
979
980 if (*hpet_boot_cfg & HPET_CFG_ENABLE)
981 hpet_writel(*hpet_boot_cfg, HPET_CFG);
982 }
983}
984
985#ifdef CONFIG_HPET_EMULATE_RTC
986
987/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
988 * is enabled, we support RTC interrupt functionality in software.
989 * RTC has 3 kinds of interrupts:
990 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
991 * is updated
992 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
993 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
994 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
995 * (1) and (2) above are implemented using polling at a frequency of
996 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
997 * overhead. (DEFAULT_RTC_INT_FREQ)
998 * For (3), we use interrupts at 64Hz or user specified periodic
999 * frequency, whichever is higher.
1000 */
1001#include <linux/mc146818rtc.h>
1002#include <linux/rtc.h>
1003#include <asm/rtc.h>
1004
1005#define DEFAULT_RTC_INT_FREQ 64
1006#define DEFAULT_RTC_SHIFT 6
1007#define RTC_NUM_INTS 1
1008
1009static unsigned long hpet_rtc_flags;
1010static int hpet_prev_update_sec;
1011static struct rtc_time hpet_alarm_time;
1012static unsigned long hpet_pie_count;
1013static u32 hpet_t1_cmp;
1014static u32 hpet_default_delta;
1015static u32 hpet_pie_delta;
1016static unsigned long hpet_pie_limit;
1017
1018static rtc_irq_handler irq_handler;
1019
1020/*
1021 * Check that the hpet counter c1 is ahead of the c2
1022 */
1023static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1024{
1025 return (s32)(c2 - c1) < 0;
1026}
1027
1028/*
1029 * Registers a IRQ handler.
1030 */
1031int hpet_register_irq_handler(rtc_irq_handler handler)
1032{
1033 if (!is_hpet_enabled())
1034 return -ENODEV;
1035 if (irq_handler)
1036 return -EBUSY;
1037
1038 irq_handler = handler;
1039
1040 return 0;
1041}
1042EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1043
1044/*
1045 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1046 * and does cleanup.
1047 */
1048void hpet_unregister_irq_handler(rtc_irq_handler handler)
1049{
1050 if (!is_hpet_enabled())
1051 return;
1052
1053 irq_handler = NULL;
1054 hpet_rtc_flags = 0;
1055}
1056EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1057
1058/*
1059 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1060 * is not supported by all HPET implementations for timer 1.
1061 *
1062 * hpet_rtc_timer_init() is called when the rtc is initialized.
1063 */
1064int hpet_rtc_timer_init(void)
1065{
1066 unsigned int cfg, cnt, delta;
1067 unsigned long flags;
1068
1069 if (!is_hpet_enabled())
1070 return 0;
1071
1072 if (!hpet_default_delta) {
1073 uint64_t clc;
1074
1075 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1076 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1077 hpet_default_delta = clc;
1078 }
1079
1080 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1081 delta = hpet_default_delta;
1082 else
1083 delta = hpet_pie_delta;
1084
1085 local_irq_save(flags);
1086
1087 cnt = delta + hpet_readl(HPET_COUNTER);
1088 hpet_writel(cnt, HPET_T1_CMP);
1089 hpet_t1_cmp = cnt;
1090
1091 cfg = hpet_readl(HPET_T1_CFG);
1092 cfg &= ~HPET_TN_PERIODIC;
1093 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1094 hpet_writel(cfg, HPET_T1_CFG);
1095
1096 local_irq_restore(flags);
1097
1098 return 1;
1099}
1100EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1101
1102static void hpet_disable_rtc_channel(void)
1103{
1104 unsigned long cfg;
1105 cfg = hpet_readl(HPET_T1_CFG);
1106 cfg &= ~HPET_TN_ENABLE;
1107 hpet_writel(cfg, HPET_T1_CFG);
1108}
1109
1110/*
1111 * The functions below are called from rtc driver.
1112 * Return 0 if HPET is not being used.
1113 * Otherwise do the necessary changes and return 1.
1114 */
1115int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1116{
1117 if (!is_hpet_enabled())
1118 return 0;
1119
1120 hpet_rtc_flags &= ~bit_mask;
1121 if (unlikely(!hpet_rtc_flags))
1122 hpet_disable_rtc_channel();
1123
1124 return 1;
1125}
1126EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1127
1128int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1129{
1130 unsigned long oldbits = hpet_rtc_flags;
1131
1132 if (!is_hpet_enabled())
1133 return 0;
1134
1135 hpet_rtc_flags |= bit_mask;
1136
1137 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1138 hpet_prev_update_sec = -1;
1139
1140 if (!oldbits)
1141 hpet_rtc_timer_init();
1142
1143 return 1;
1144}
1145EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1146
1147int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1148 unsigned char sec)
1149{
1150 if (!is_hpet_enabled())
1151 return 0;
1152
1153 hpet_alarm_time.tm_hour = hrs;
1154 hpet_alarm_time.tm_min = min;
1155 hpet_alarm_time.tm_sec = sec;
1156
1157 return 1;
1158}
1159EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1160
1161int hpet_set_periodic_freq(unsigned long freq)
1162{
1163 uint64_t clc;
1164
1165 if (!is_hpet_enabled())
1166 return 0;
1167
1168 if (freq <= DEFAULT_RTC_INT_FREQ)
1169 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1170 else {
1171 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1172 do_div(clc, freq);
1173 clc >>= hpet_clockevent.shift;
1174 hpet_pie_delta = clc;
1175 hpet_pie_limit = 0;
1176 }
1177 return 1;
1178}
1179EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1180
1181int hpet_rtc_dropped_irq(void)
1182{
1183 return is_hpet_enabled();
1184}
1185EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1186
1187static void hpet_rtc_timer_reinit(void)
1188{
1189 unsigned int delta;
1190 int lost_ints = -1;
1191
1192 if (unlikely(!hpet_rtc_flags))
1193 hpet_disable_rtc_channel();
1194
1195 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1196 delta = hpet_default_delta;
1197 else
1198 delta = hpet_pie_delta;
1199
1200 /*
1201 * Increment the comparator value until we are ahead of the
1202 * current count.
1203 */
1204 do {
1205 hpet_t1_cmp += delta;
1206 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1207 lost_ints++;
1208 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1209
1210 if (lost_ints) {
1211 if (hpet_rtc_flags & RTC_PIE)
1212 hpet_pie_count += lost_ints;
1213 if (printk_ratelimit())
1214 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1215 lost_ints);
1216 }
1217}
1218
1219irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1220{
1221 struct rtc_time curr_time;
1222 unsigned long rtc_int_flag = 0;
1223
1224 hpet_rtc_timer_reinit();
1225 memset(&curr_time, 0, sizeof(struct rtc_time));
1226
1227 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1228 get_rtc_time(&curr_time);
1229
1230 if (hpet_rtc_flags & RTC_UIE &&
1231 curr_time.tm_sec != hpet_prev_update_sec) {
1232 if (hpet_prev_update_sec >= 0)
1233 rtc_int_flag = RTC_UF;
1234 hpet_prev_update_sec = curr_time.tm_sec;
1235 }
1236
1237 if (hpet_rtc_flags & RTC_PIE &&
1238 ++hpet_pie_count >= hpet_pie_limit) {
1239 rtc_int_flag |= RTC_PF;
1240 hpet_pie_count = 0;
1241 }
1242
1243 if (hpet_rtc_flags & RTC_AIE &&
1244 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1245 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1246 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1247 rtc_int_flag |= RTC_AF;
1248
1249 if (rtc_int_flag) {
1250 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1251 if (irq_handler)
1252 irq_handler(rtc_int_flag, dev_id);
1253 }
1254 return IRQ_HANDLED;
1255}
1256EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
1257#endif
1#include <linux/clocksource.h>
2#include <linux/clockchips.h>
3#include <linux/interrupt.h>
4#include <linux/export.h>
5#include <linux/delay.h>
6#include <linux/errno.h>
7#include <linux/i8253.h>
8#include <linux/slab.h>
9#include <linux/hpet.h>
10#include <linux/init.h>
11#include <linux/cpu.h>
12#include <linux/pm.h>
13#include <linux/io.h>
14
15#include <asm/cpufeature.h>
16#include <asm/irqdomain.h>
17#include <asm/fixmap.h>
18#include <asm/hpet.h>
19#include <asm/time.h>
20
21#define HPET_MASK CLOCKSOURCE_MASK(32)
22
23/* FSEC = 10^-15
24 NSEC = 10^-9 */
25#define FSEC_PER_NSEC 1000000L
26
27#define HPET_DEV_USED_BIT 2
28#define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
29#define HPET_DEV_VALID 0x8
30#define HPET_DEV_FSB_CAP 0x1000
31#define HPET_DEV_PERI_CAP 0x2000
32
33#define HPET_MIN_CYCLES 128
34#define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
35
36/*
37 * HPET address is set in acpi/boot.c, when an ACPI entry exists
38 */
39unsigned long hpet_address;
40u8 hpet_blockid; /* OS timer block num */
41bool hpet_msi_disable;
42
43#ifdef CONFIG_PCI_MSI
44static unsigned int hpet_num_timers;
45#endif
46static void __iomem *hpet_virt_address;
47
48struct hpet_dev {
49 struct clock_event_device evt;
50 unsigned int num;
51 int cpu;
52 unsigned int irq;
53 unsigned int flags;
54 char name[10];
55};
56
57inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev)
58{
59 return container_of(evtdev, struct hpet_dev, evt);
60}
61
62inline unsigned int hpet_readl(unsigned int a)
63{
64 return readl(hpet_virt_address + a);
65}
66
67static inline void hpet_writel(unsigned int d, unsigned int a)
68{
69 writel(d, hpet_virt_address + a);
70}
71
72#ifdef CONFIG_X86_64
73#include <asm/pgtable.h>
74#endif
75
76static inline void hpet_set_mapping(void)
77{
78 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
79}
80
81static inline void hpet_clear_mapping(void)
82{
83 iounmap(hpet_virt_address);
84 hpet_virt_address = NULL;
85}
86
87/*
88 * HPET command line enable / disable
89 */
90bool boot_hpet_disable;
91bool hpet_force_user;
92static bool hpet_verbose;
93
94static int __init hpet_setup(char *str)
95{
96 while (str) {
97 char *next = strchr(str, ',');
98
99 if (next)
100 *next++ = 0;
101 if (!strncmp("disable", str, 7))
102 boot_hpet_disable = true;
103 if (!strncmp("force", str, 5))
104 hpet_force_user = true;
105 if (!strncmp("verbose", str, 7))
106 hpet_verbose = true;
107 str = next;
108 }
109 return 1;
110}
111__setup("hpet=", hpet_setup);
112
113static int __init disable_hpet(char *str)
114{
115 boot_hpet_disable = true;
116 return 1;
117}
118__setup("nohpet", disable_hpet);
119
120static inline int is_hpet_capable(void)
121{
122 return !boot_hpet_disable && hpet_address;
123}
124
125/*
126 * HPET timer interrupt enable / disable
127 */
128static bool hpet_legacy_int_enabled;
129
130/**
131 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
132 */
133int is_hpet_enabled(void)
134{
135 return is_hpet_capable() && hpet_legacy_int_enabled;
136}
137EXPORT_SYMBOL_GPL(is_hpet_enabled);
138
139static void _hpet_print_config(const char *function, int line)
140{
141 u32 i, timers, l, h;
142 printk(KERN_INFO "hpet: %s(%d):\n", function, line);
143 l = hpet_readl(HPET_ID);
144 h = hpet_readl(HPET_PERIOD);
145 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
146 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
147 l = hpet_readl(HPET_CFG);
148 h = hpet_readl(HPET_STATUS);
149 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
150 l = hpet_readl(HPET_COUNTER);
151 h = hpet_readl(HPET_COUNTER+4);
152 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
153
154 for (i = 0; i < timers; i++) {
155 l = hpet_readl(HPET_Tn_CFG(i));
156 h = hpet_readl(HPET_Tn_CFG(i)+4);
157 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
158 i, l, h);
159 l = hpet_readl(HPET_Tn_CMP(i));
160 h = hpet_readl(HPET_Tn_CMP(i)+4);
161 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
162 i, l, h);
163 l = hpet_readl(HPET_Tn_ROUTE(i));
164 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
165 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
166 i, l, h);
167 }
168}
169
170#define hpet_print_config() \
171do { \
172 if (hpet_verbose) \
173 _hpet_print_config(__func__, __LINE__); \
174} while (0)
175
176/*
177 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
178 * timer 0 and timer 1 in case of RTC emulation.
179 */
180#ifdef CONFIG_HPET
181
182static void hpet_reserve_msi_timers(struct hpet_data *hd);
183
184static void hpet_reserve_platform_timers(unsigned int id)
185{
186 struct hpet __iomem *hpet = hpet_virt_address;
187 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
188 unsigned int nrtimers, i;
189 struct hpet_data hd;
190
191 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
192
193 memset(&hd, 0, sizeof(hd));
194 hd.hd_phys_address = hpet_address;
195 hd.hd_address = hpet;
196 hd.hd_nirqs = nrtimers;
197 hpet_reserve_timer(&hd, 0);
198
199#ifdef CONFIG_HPET_EMULATE_RTC
200 hpet_reserve_timer(&hd, 1);
201#endif
202
203 /*
204 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
205 * is wrong for i8259!) not the output IRQ. Many BIOS writers
206 * don't bother configuring *any* comparator interrupts.
207 */
208 hd.hd_irq[0] = HPET_LEGACY_8254;
209 hd.hd_irq[1] = HPET_LEGACY_RTC;
210
211 for (i = 2; i < nrtimers; timer++, i++) {
212 hd.hd_irq[i] = (readl(&timer->hpet_config) &
213 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
214 }
215
216 hpet_reserve_msi_timers(&hd);
217
218 hpet_alloc(&hd);
219
220}
221#else
222static void hpet_reserve_platform_timers(unsigned int id) { }
223#endif
224
225/*
226 * Common hpet info
227 */
228static unsigned long hpet_freq;
229
230static struct clock_event_device hpet_clockevent;
231
232static void hpet_stop_counter(void)
233{
234 u32 cfg = hpet_readl(HPET_CFG);
235 cfg &= ~HPET_CFG_ENABLE;
236 hpet_writel(cfg, HPET_CFG);
237}
238
239static void hpet_reset_counter(void)
240{
241 hpet_writel(0, HPET_COUNTER);
242 hpet_writel(0, HPET_COUNTER + 4);
243}
244
245static void hpet_start_counter(void)
246{
247 unsigned int cfg = hpet_readl(HPET_CFG);
248 cfg |= HPET_CFG_ENABLE;
249 hpet_writel(cfg, HPET_CFG);
250}
251
252static void hpet_restart_counter(void)
253{
254 hpet_stop_counter();
255 hpet_reset_counter();
256 hpet_start_counter();
257}
258
259static void hpet_resume_device(void)
260{
261 force_hpet_resume();
262}
263
264static void hpet_resume_counter(struct clocksource *cs)
265{
266 hpet_resume_device();
267 hpet_restart_counter();
268}
269
270static void hpet_enable_legacy_int(void)
271{
272 unsigned int cfg = hpet_readl(HPET_CFG);
273
274 cfg |= HPET_CFG_LEGACY;
275 hpet_writel(cfg, HPET_CFG);
276 hpet_legacy_int_enabled = true;
277}
278
279static void hpet_legacy_clockevent_register(void)
280{
281 /* Start HPET legacy interrupts */
282 hpet_enable_legacy_int();
283
284 /*
285 * Start hpet with the boot cpu mask and make it
286 * global after the IO_APIC has been initialized.
287 */
288 hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
289 clockevents_config_and_register(&hpet_clockevent, hpet_freq,
290 HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
291 global_clock_event = &hpet_clockevent;
292 printk(KERN_DEBUG "hpet clockevent registered\n");
293}
294
295static int hpet_set_periodic(struct clock_event_device *evt, int timer)
296{
297 unsigned int cfg, cmp, now;
298 uint64_t delta;
299
300 hpet_stop_counter();
301 delta = ((uint64_t)(NSEC_PER_SEC / HZ)) * evt->mult;
302 delta >>= evt->shift;
303 now = hpet_readl(HPET_COUNTER);
304 cmp = now + (unsigned int)delta;
305 cfg = hpet_readl(HPET_Tn_CFG(timer));
306 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL |
307 HPET_TN_32BIT;
308 hpet_writel(cfg, HPET_Tn_CFG(timer));
309 hpet_writel(cmp, HPET_Tn_CMP(timer));
310 udelay(1);
311 /*
312 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
313 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
314 * bit is automatically cleared after the first write.
315 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
316 * Publication # 24674)
317 */
318 hpet_writel((unsigned int)delta, HPET_Tn_CMP(timer));
319 hpet_start_counter();
320 hpet_print_config();
321
322 return 0;
323}
324
325static int hpet_set_oneshot(struct clock_event_device *evt, int timer)
326{
327 unsigned int cfg;
328
329 cfg = hpet_readl(HPET_Tn_CFG(timer));
330 cfg &= ~HPET_TN_PERIODIC;
331 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
332 hpet_writel(cfg, HPET_Tn_CFG(timer));
333
334 return 0;
335}
336
337static int hpet_shutdown(struct clock_event_device *evt, int timer)
338{
339 unsigned int cfg;
340
341 cfg = hpet_readl(HPET_Tn_CFG(timer));
342 cfg &= ~HPET_TN_ENABLE;
343 hpet_writel(cfg, HPET_Tn_CFG(timer));
344
345 return 0;
346}
347
348static int hpet_resume(struct clock_event_device *evt, int timer)
349{
350 if (!timer) {
351 hpet_enable_legacy_int();
352 } else {
353 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
354
355 irq_domain_activate_irq(irq_get_irq_data(hdev->irq));
356 disable_irq(hdev->irq);
357 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
358 enable_irq(hdev->irq);
359 }
360 hpet_print_config();
361
362 return 0;
363}
364
365static int hpet_next_event(unsigned long delta,
366 struct clock_event_device *evt, int timer)
367{
368 u32 cnt;
369 s32 res;
370
371 cnt = hpet_readl(HPET_COUNTER);
372 cnt += (u32) delta;
373 hpet_writel(cnt, HPET_Tn_CMP(timer));
374
375 /*
376 * HPETs are a complete disaster. The compare register is
377 * based on a equal comparison and neither provides a less
378 * than or equal functionality (which would require to take
379 * the wraparound into account) nor a simple count down event
380 * mode. Further the write to the comparator register is
381 * delayed internally up to two HPET clock cycles in certain
382 * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
383 * longer delays. We worked around that by reading back the
384 * compare register, but that required another workaround for
385 * ICH9,10 chips where the first readout after write can
386 * return the old stale value. We already had a minimum
387 * programming delta of 5us enforced, but a NMI or SMI hitting
388 * between the counter readout and the comparator write can
389 * move us behind that point easily. Now instead of reading
390 * the compare register back several times, we make the ETIME
391 * decision based on the following: Return ETIME if the
392 * counter value after the write is less than HPET_MIN_CYCLES
393 * away from the event or if the counter is already ahead of
394 * the event. The minimum programming delta for the generic
395 * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
396 */
397 res = (s32)(cnt - hpet_readl(HPET_COUNTER));
398
399 return res < HPET_MIN_CYCLES ? -ETIME : 0;
400}
401
402static int hpet_legacy_shutdown(struct clock_event_device *evt)
403{
404 return hpet_shutdown(evt, 0);
405}
406
407static int hpet_legacy_set_oneshot(struct clock_event_device *evt)
408{
409 return hpet_set_oneshot(evt, 0);
410}
411
412static int hpet_legacy_set_periodic(struct clock_event_device *evt)
413{
414 return hpet_set_periodic(evt, 0);
415}
416
417static int hpet_legacy_resume(struct clock_event_device *evt)
418{
419 return hpet_resume(evt, 0);
420}
421
422static int hpet_legacy_next_event(unsigned long delta,
423 struct clock_event_device *evt)
424{
425 return hpet_next_event(delta, evt, 0);
426}
427
428/*
429 * The hpet clock event device
430 */
431static struct clock_event_device hpet_clockevent = {
432 .name = "hpet",
433 .features = CLOCK_EVT_FEAT_PERIODIC |
434 CLOCK_EVT_FEAT_ONESHOT,
435 .set_state_periodic = hpet_legacy_set_periodic,
436 .set_state_oneshot = hpet_legacy_set_oneshot,
437 .set_state_shutdown = hpet_legacy_shutdown,
438 .tick_resume = hpet_legacy_resume,
439 .set_next_event = hpet_legacy_next_event,
440 .irq = 0,
441 .rating = 50,
442};
443
444/*
445 * HPET MSI Support
446 */
447#ifdef CONFIG_PCI_MSI
448
449static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
450static struct hpet_dev *hpet_devs;
451static struct irq_domain *hpet_domain;
452
453void hpet_msi_unmask(struct irq_data *data)
454{
455 struct hpet_dev *hdev = irq_data_get_irq_handler_data(data);
456 unsigned int cfg;
457
458 /* unmask it */
459 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
460 cfg |= HPET_TN_ENABLE | HPET_TN_FSB;
461 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
462}
463
464void hpet_msi_mask(struct irq_data *data)
465{
466 struct hpet_dev *hdev = irq_data_get_irq_handler_data(data);
467 unsigned int cfg;
468
469 /* mask it */
470 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
471 cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB);
472 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
473}
474
475void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
476{
477 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
478 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
479}
480
481void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
482{
483 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
484 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
485 msg->address_hi = 0;
486}
487
488static int hpet_msi_shutdown(struct clock_event_device *evt)
489{
490 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
491
492 return hpet_shutdown(evt, hdev->num);
493}
494
495static int hpet_msi_set_oneshot(struct clock_event_device *evt)
496{
497 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
498
499 return hpet_set_oneshot(evt, hdev->num);
500}
501
502static int hpet_msi_set_periodic(struct clock_event_device *evt)
503{
504 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
505
506 return hpet_set_periodic(evt, hdev->num);
507}
508
509static int hpet_msi_resume(struct clock_event_device *evt)
510{
511 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
512
513 return hpet_resume(evt, hdev->num);
514}
515
516static int hpet_msi_next_event(unsigned long delta,
517 struct clock_event_device *evt)
518{
519 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
520 return hpet_next_event(delta, evt, hdev->num);
521}
522
523static irqreturn_t hpet_interrupt_handler(int irq, void *data)
524{
525 struct hpet_dev *dev = (struct hpet_dev *)data;
526 struct clock_event_device *hevt = &dev->evt;
527
528 if (!hevt->event_handler) {
529 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
530 dev->num);
531 return IRQ_HANDLED;
532 }
533
534 hevt->event_handler(hevt);
535 return IRQ_HANDLED;
536}
537
538static int hpet_setup_irq(struct hpet_dev *dev)
539{
540
541 if (request_irq(dev->irq, hpet_interrupt_handler,
542 IRQF_TIMER | IRQF_NOBALANCING,
543 dev->name, dev))
544 return -1;
545
546 disable_irq(dev->irq);
547 irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
548 enable_irq(dev->irq);
549
550 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
551 dev->name, dev->irq);
552
553 return 0;
554}
555
556/* This should be called in specific @cpu */
557static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
558{
559 struct clock_event_device *evt = &hdev->evt;
560
561 WARN_ON(cpu != smp_processor_id());
562 if (!(hdev->flags & HPET_DEV_VALID))
563 return;
564
565 hdev->cpu = cpu;
566 per_cpu(cpu_hpet_dev, cpu) = hdev;
567 evt->name = hdev->name;
568 hpet_setup_irq(hdev);
569 evt->irq = hdev->irq;
570
571 evt->rating = 110;
572 evt->features = CLOCK_EVT_FEAT_ONESHOT;
573 if (hdev->flags & HPET_DEV_PERI_CAP) {
574 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
575 evt->set_state_periodic = hpet_msi_set_periodic;
576 }
577
578 evt->set_state_shutdown = hpet_msi_shutdown;
579 evt->set_state_oneshot = hpet_msi_set_oneshot;
580 evt->tick_resume = hpet_msi_resume;
581 evt->set_next_event = hpet_msi_next_event;
582 evt->cpumask = cpumask_of(hdev->cpu);
583
584 clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
585 0x7FFFFFFF);
586}
587
588#ifdef CONFIG_HPET
589/* Reserve at least one timer for userspace (/dev/hpet) */
590#define RESERVE_TIMERS 1
591#else
592#define RESERVE_TIMERS 0
593#endif
594
595static void hpet_msi_capability_lookup(unsigned int start_timer)
596{
597 unsigned int id;
598 unsigned int num_timers;
599 unsigned int num_timers_used = 0;
600 int i, irq;
601
602 if (hpet_msi_disable)
603 return;
604
605 if (boot_cpu_has(X86_FEATURE_ARAT))
606 return;
607 id = hpet_readl(HPET_ID);
608
609 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
610 num_timers++; /* Value read out starts from 0 */
611 hpet_print_config();
612
613 hpet_domain = hpet_create_irq_domain(hpet_blockid);
614 if (!hpet_domain)
615 return;
616
617 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
618 if (!hpet_devs)
619 return;
620
621 hpet_num_timers = num_timers;
622
623 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
624 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
625 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
626
627 /* Only consider HPET timer with MSI support */
628 if (!(cfg & HPET_TN_FSB_CAP))
629 continue;
630
631 hdev->flags = 0;
632 if (cfg & HPET_TN_PERIODIC_CAP)
633 hdev->flags |= HPET_DEV_PERI_CAP;
634 sprintf(hdev->name, "hpet%d", i);
635 hdev->num = i;
636
637 irq = hpet_assign_irq(hpet_domain, hdev, hdev->num);
638 if (irq <= 0)
639 continue;
640
641 hdev->irq = irq;
642 hdev->flags |= HPET_DEV_FSB_CAP;
643 hdev->flags |= HPET_DEV_VALID;
644 num_timers_used++;
645 if (num_timers_used == num_possible_cpus())
646 break;
647 }
648
649 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
650 num_timers, num_timers_used);
651}
652
653#ifdef CONFIG_HPET
654static void hpet_reserve_msi_timers(struct hpet_data *hd)
655{
656 int i;
657
658 if (!hpet_devs)
659 return;
660
661 for (i = 0; i < hpet_num_timers; i++) {
662 struct hpet_dev *hdev = &hpet_devs[i];
663
664 if (!(hdev->flags & HPET_DEV_VALID))
665 continue;
666
667 hd->hd_irq[hdev->num] = hdev->irq;
668 hpet_reserve_timer(hd, hdev->num);
669 }
670}
671#endif
672
673static struct hpet_dev *hpet_get_unused_timer(void)
674{
675 int i;
676
677 if (!hpet_devs)
678 return NULL;
679
680 for (i = 0; i < hpet_num_timers; i++) {
681 struct hpet_dev *hdev = &hpet_devs[i];
682
683 if (!(hdev->flags & HPET_DEV_VALID))
684 continue;
685 if (test_and_set_bit(HPET_DEV_USED_BIT,
686 (unsigned long *)&hdev->flags))
687 continue;
688 return hdev;
689 }
690 return NULL;
691}
692
693struct hpet_work_struct {
694 struct delayed_work work;
695 struct completion complete;
696};
697
698static void hpet_work(struct work_struct *w)
699{
700 struct hpet_dev *hdev;
701 int cpu = smp_processor_id();
702 struct hpet_work_struct *hpet_work;
703
704 hpet_work = container_of(w, struct hpet_work_struct, work.work);
705
706 hdev = hpet_get_unused_timer();
707 if (hdev)
708 init_one_hpet_msi_clockevent(hdev, cpu);
709
710 complete(&hpet_work->complete);
711}
712
713static int hpet_cpuhp_notify(struct notifier_block *n,
714 unsigned long action, void *hcpu)
715{
716 unsigned long cpu = (unsigned long)hcpu;
717 struct hpet_work_struct work;
718 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
719
720 switch (action & ~CPU_TASKS_FROZEN) {
721 case CPU_ONLINE:
722 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work);
723 init_completion(&work.complete);
724 /* FIXME: add schedule_work_on() */
725 schedule_delayed_work_on(cpu, &work.work, 0);
726 wait_for_completion(&work.complete);
727 destroy_delayed_work_on_stack(&work.work);
728 break;
729 case CPU_DEAD:
730 if (hdev) {
731 free_irq(hdev->irq, hdev);
732 hdev->flags &= ~HPET_DEV_USED;
733 per_cpu(cpu_hpet_dev, cpu) = NULL;
734 }
735 break;
736 }
737 return NOTIFY_OK;
738}
739#else
740
741static void hpet_msi_capability_lookup(unsigned int start_timer)
742{
743 return;
744}
745
746#ifdef CONFIG_HPET
747static void hpet_reserve_msi_timers(struct hpet_data *hd)
748{
749 return;
750}
751#endif
752
753static int hpet_cpuhp_notify(struct notifier_block *n,
754 unsigned long action, void *hcpu)
755{
756 return NOTIFY_OK;
757}
758
759#endif
760
761/*
762 * Clock source related code
763 */
764static cycle_t read_hpet(struct clocksource *cs)
765{
766 return (cycle_t)hpet_readl(HPET_COUNTER);
767}
768
769static struct clocksource clocksource_hpet = {
770 .name = "hpet",
771 .rating = 250,
772 .read = read_hpet,
773 .mask = HPET_MASK,
774 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
775 .resume = hpet_resume_counter,
776 .archdata = { .vclock_mode = VCLOCK_HPET },
777};
778
779static int hpet_clocksource_register(void)
780{
781 u64 start, now;
782 cycle_t t1;
783
784 /* Start the counter */
785 hpet_restart_counter();
786
787 /* Verify whether hpet counter works */
788 t1 = hpet_readl(HPET_COUNTER);
789 start = rdtsc();
790
791 /*
792 * We don't know the TSC frequency yet, but waiting for
793 * 200000 TSC cycles is safe:
794 * 4 GHz == 50us
795 * 1 GHz == 200us
796 */
797 do {
798 rep_nop();
799 now = rdtsc();
800 } while ((now - start) < 200000UL);
801
802 if (t1 == hpet_readl(HPET_COUNTER)) {
803 printk(KERN_WARNING
804 "HPET counter not counting. HPET disabled\n");
805 return -ENODEV;
806 }
807
808 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
809 return 0;
810}
811
812static u32 *hpet_boot_cfg;
813
814/**
815 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
816 */
817int __init hpet_enable(void)
818{
819 u32 hpet_period, cfg, id;
820 u64 freq;
821 unsigned int i, last;
822
823 if (!is_hpet_capable())
824 return 0;
825
826 hpet_set_mapping();
827
828 /*
829 * Read the period and check for a sane value:
830 */
831 hpet_period = hpet_readl(HPET_PERIOD);
832
833 /*
834 * AMD SB700 based systems with spread spectrum enabled use a
835 * SMM based HPET emulation to provide proper frequency
836 * setting. The SMM code is initialized with the first HPET
837 * register access and takes some time to complete. During
838 * this time the config register reads 0xffffffff. We check
839 * for max. 1000 loops whether the config register reads a non
840 * 0xffffffff value to make sure that HPET is up and running
841 * before we go further. A counting loop is safe, as the HPET
842 * access takes thousands of CPU cycles. On non SB700 based
843 * machines this check is only done once and has no side
844 * effects.
845 */
846 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
847 if (i == 1000) {
848 printk(KERN_WARNING
849 "HPET config register value = 0xFFFFFFFF. "
850 "Disabling HPET\n");
851 goto out_nohpet;
852 }
853 }
854
855 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
856 goto out_nohpet;
857
858 /*
859 * The period is a femto seconds value. Convert it to a
860 * frequency.
861 */
862 freq = FSEC_PER_SEC;
863 do_div(freq, hpet_period);
864 hpet_freq = freq;
865
866 /*
867 * Read the HPET ID register to retrieve the IRQ routing
868 * information and the number of channels
869 */
870 id = hpet_readl(HPET_ID);
871 hpet_print_config();
872
873 last = (id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT;
874
875#ifdef CONFIG_HPET_EMULATE_RTC
876 /*
877 * The legacy routing mode needs at least two channels, tick timer
878 * and the rtc emulation channel.
879 */
880 if (!last)
881 goto out_nohpet;
882#endif
883
884 cfg = hpet_readl(HPET_CFG);
885 hpet_boot_cfg = kmalloc((last + 2) * sizeof(*hpet_boot_cfg),
886 GFP_KERNEL);
887 if (hpet_boot_cfg)
888 *hpet_boot_cfg = cfg;
889 else
890 pr_warn("HPET initial state will not be saved\n");
891 cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
892 hpet_writel(cfg, HPET_CFG);
893 if (cfg)
894 pr_warn("HPET: Unrecognized bits %#x set in global cfg\n",
895 cfg);
896
897 for (i = 0; i <= last; ++i) {
898 cfg = hpet_readl(HPET_Tn_CFG(i));
899 if (hpet_boot_cfg)
900 hpet_boot_cfg[i + 1] = cfg;
901 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB);
902 hpet_writel(cfg, HPET_Tn_CFG(i));
903 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP
904 | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE
905 | HPET_TN_FSB | HPET_TN_FSB_CAP);
906 if (cfg)
907 pr_warn("HPET: Unrecognized bits %#x set in cfg#%u\n",
908 cfg, i);
909 }
910 hpet_print_config();
911
912 if (hpet_clocksource_register())
913 goto out_nohpet;
914
915 if (id & HPET_ID_LEGSUP) {
916 hpet_legacy_clockevent_register();
917 return 1;
918 }
919 return 0;
920
921out_nohpet:
922 hpet_clear_mapping();
923 hpet_address = 0;
924 return 0;
925}
926
927/*
928 * Needs to be late, as the reserve_timer code calls kalloc !
929 *
930 * Not a problem on i386 as hpet_enable is called from late_time_init,
931 * but on x86_64 it is necessary !
932 */
933static __init int hpet_late_init(void)
934{
935 int cpu;
936
937 if (boot_hpet_disable)
938 return -ENODEV;
939
940 if (!hpet_address) {
941 if (!force_hpet_address)
942 return -ENODEV;
943
944 hpet_address = force_hpet_address;
945 hpet_enable();
946 }
947
948 if (!hpet_virt_address)
949 return -ENODEV;
950
951 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
952 hpet_msi_capability_lookup(2);
953 else
954 hpet_msi_capability_lookup(0);
955
956 hpet_reserve_platform_timers(hpet_readl(HPET_ID));
957 hpet_print_config();
958
959 if (hpet_msi_disable)
960 return 0;
961
962 if (boot_cpu_has(X86_FEATURE_ARAT))
963 return 0;
964
965 cpu_notifier_register_begin();
966 for_each_online_cpu(cpu) {
967 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
968 }
969
970 /* This notifier should be called after workqueue is ready */
971 __hotcpu_notifier(hpet_cpuhp_notify, -20);
972 cpu_notifier_register_done();
973
974 return 0;
975}
976fs_initcall(hpet_late_init);
977
978void hpet_disable(void)
979{
980 if (is_hpet_capable() && hpet_virt_address) {
981 unsigned int cfg = hpet_readl(HPET_CFG), id, last;
982
983 if (hpet_boot_cfg)
984 cfg = *hpet_boot_cfg;
985 else if (hpet_legacy_int_enabled) {
986 cfg &= ~HPET_CFG_LEGACY;
987 hpet_legacy_int_enabled = false;
988 }
989 cfg &= ~HPET_CFG_ENABLE;
990 hpet_writel(cfg, HPET_CFG);
991
992 if (!hpet_boot_cfg)
993 return;
994
995 id = hpet_readl(HPET_ID);
996 last = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
997
998 for (id = 0; id <= last; ++id)
999 hpet_writel(hpet_boot_cfg[id + 1], HPET_Tn_CFG(id));
1000
1001 if (*hpet_boot_cfg & HPET_CFG_ENABLE)
1002 hpet_writel(*hpet_boot_cfg, HPET_CFG);
1003 }
1004}
1005
1006#ifdef CONFIG_HPET_EMULATE_RTC
1007
1008/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
1009 * is enabled, we support RTC interrupt functionality in software.
1010 * RTC has 3 kinds of interrupts:
1011 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
1012 * is updated
1013 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
1014 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
1015 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
1016 * (1) and (2) above are implemented using polling at a frequency of
1017 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
1018 * overhead. (DEFAULT_RTC_INT_FREQ)
1019 * For (3), we use interrupts at 64Hz or user specified periodic
1020 * frequency, whichever is higher.
1021 */
1022#include <linux/mc146818rtc.h>
1023#include <linux/rtc.h>
1024#include <asm/rtc.h>
1025
1026#define DEFAULT_RTC_INT_FREQ 64
1027#define DEFAULT_RTC_SHIFT 6
1028#define RTC_NUM_INTS 1
1029
1030static unsigned long hpet_rtc_flags;
1031static int hpet_prev_update_sec;
1032static struct rtc_time hpet_alarm_time;
1033static unsigned long hpet_pie_count;
1034static u32 hpet_t1_cmp;
1035static u32 hpet_default_delta;
1036static u32 hpet_pie_delta;
1037static unsigned long hpet_pie_limit;
1038
1039static rtc_irq_handler irq_handler;
1040
1041/*
1042 * Check that the hpet counter c1 is ahead of the c2
1043 */
1044static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1045{
1046 return (s32)(c2 - c1) < 0;
1047}
1048
1049/*
1050 * Registers a IRQ handler.
1051 */
1052int hpet_register_irq_handler(rtc_irq_handler handler)
1053{
1054 if (!is_hpet_enabled())
1055 return -ENODEV;
1056 if (irq_handler)
1057 return -EBUSY;
1058
1059 irq_handler = handler;
1060
1061 return 0;
1062}
1063EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1064
1065/*
1066 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1067 * and does cleanup.
1068 */
1069void hpet_unregister_irq_handler(rtc_irq_handler handler)
1070{
1071 if (!is_hpet_enabled())
1072 return;
1073
1074 irq_handler = NULL;
1075 hpet_rtc_flags = 0;
1076}
1077EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1078
1079/*
1080 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1081 * is not supported by all HPET implementations for timer 1.
1082 *
1083 * hpet_rtc_timer_init() is called when the rtc is initialized.
1084 */
1085int hpet_rtc_timer_init(void)
1086{
1087 unsigned int cfg, cnt, delta;
1088 unsigned long flags;
1089
1090 if (!is_hpet_enabled())
1091 return 0;
1092
1093 if (!hpet_default_delta) {
1094 uint64_t clc;
1095
1096 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1097 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1098 hpet_default_delta = clc;
1099 }
1100
1101 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1102 delta = hpet_default_delta;
1103 else
1104 delta = hpet_pie_delta;
1105
1106 local_irq_save(flags);
1107
1108 cnt = delta + hpet_readl(HPET_COUNTER);
1109 hpet_writel(cnt, HPET_T1_CMP);
1110 hpet_t1_cmp = cnt;
1111
1112 cfg = hpet_readl(HPET_T1_CFG);
1113 cfg &= ~HPET_TN_PERIODIC;
1114 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1115 hpet_writel(cfg, HPET_T1_CFG);
1116
1117 local_irq_restore(flags);
1118
1119 return 1;
1120}
1121EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1122
1123static void hpet_disable_rtc_channel(void)
1124{
1125 u32 cfg = hpet_readl(HPET_T1_CFG);
1126 cfg &= ~HPET_TN_ENABLE;
1127 hpet_writel(cfg, HPET_T1_CFG);
1128}
1129
1130/*
1131 * The functions below are called from rtc driver.
1132 * Return 0 if HPET is not being used.
1133 * Otherwise do the necessary changes and return 1.
1134 */
1135int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1136{
1137 if (!is_hpet_enabled())
1138 return 0;
1139
1140 hpet_rtc_flags &= ~bit_mask;
1141 if (unlikely(!hpet_rtc_flags))
1142 hpet_disable_rtc_channel();
1143
1144 return 1;
1145}
1146EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1147
1148int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1149{
1150 unsigned long oldbits = hpet_rtc_flags;
1151
1152 if (!is_hpet_enabled())
1153 return 0;
1154
1155 hpet_rtc_flags |= bit_mask;
1156
1157 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1158 hpet_prev_update_sec = -1;
1159
1160 if (!oldbits)
1161 hpet_rtc_timer_init();
1162
1163 return 1;
1164}
1165EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1166
1167int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1168 unsigned char sec)
1169{
1170 if (!is_hpet_enabled())
1171 return 0;
1172
1173 hpet_alarm_time.tm_hour = hrs;
1174 hpet_alarm_time.tm_min = min;
1175 hpet_alarm_time.tm_sec = sec;
1176
1177 return 1;
1178}
1179EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1180
1181int hpet_set_periodic_freq(unsigned long freq)
1182{
1183 uint64_t clc;
1184
1185 if (!is_hpet_enabled())
1186 return 0;
1187
1188 if (freq <= DEFAULT_RTC_INT_FREQ)
1189 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1190 else {
1191 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1192 do_div(clc, freq);
1193 clc >>= hpet_clockevent.shift;
1194 hpet_pie_delta = clc;
1195 hpet_pie_limit = 0;
1196 }
1197 return 1;
1198}
1199EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1200
1201int hpet_rtc_dropped_irq(void)
1202{
1203 return is_hpet_enabled();
1204}
1205EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1206
1207static void hpet_rtc_timer_reinit(void)
1208{
1209 unsigned int delta;
1210 int lost_ints = -1;
1211
1212 if (unlikely(!hpet_rtc_flags))
1213 hpet_disable_rtc_channel();
1214
1215 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1216 delta = hpet_default_delta;
1217 else
1218 delta = hpet_pie_delta;
1219
1220 /*
1221 * Increment the comparator value until we are ahead of the
1222 * current count.
1223 */
1224 do {
1225 hpet_t1_cmp += delta;
1226 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1227 lost_ints++;
1228 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1229
1230 if (lost_ints) {
1231 if (hpet_rtc_flags & RTC_PIE)
1232 hpet_pie_count += lost_ints;
1233 if (printk_ratelimit())
1234 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1235 lost_ints);
1236 }
1237}
1238
1239irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1240{
1241 struct rtc_time curr_time;
1242 unsigned long rtc_int_flag = 0;
1243
1244 hpet_rtc_timer_reinit();
1245 memset(&curr_time, 0, sizeof(struct rtc_time));
1246
1247 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1248 get_rtc_time(&curr_time);
1249
1250 if (hpet_rtc_flags & RTC_UIE &&
1251 curr_time.tm_sec != hpet_prev_update_sec) {
1252 if (hpet_prev_update_sec >= 0)
1253 rtc_int_flag = RTC_UF;
1254 hpet_prev_update_sec = curr_time.tm_sec;
1255 }
1256
1257 if (hpet_rtc_flags & RTC_PIE &&
1258 ++hpet_pie_count >= hpet_pie_limit) {
1259 rtc_int_flag |= RTC_PF;
1260 hpet_pie_count = 0;
1261 }
1262
1263 if (hpet_rtc_flags & RTC_AIE &&
1264 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1265 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1266 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1267 rtc_int_flag |= RTC_AF;
1268
1269 if (rtc_int_flag) {
1270 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1271 if (irq_handler)
1272 irq_handler(rtc_int_flag, dev_id);
1273 }
1274 return IRQ_HANDLED;
1275}
1276EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
1277#endif