1/*
  2 *  AMD CPU Microcode Update Driver for Linux
  3 *
  4 *  This driver allows to upgrade microcode on F10h AMD
  5 *  CPUs and later.
  6 *
  7 *  Copyright (C) 2008-2011 Advanced Micro Devices Inc.
  8 *
  9 *  Author: Peter Oruba <peter.oruba@amd.com>
 10 *
 11 *  Based on work by:
 12 *  Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
 13 *
 14 *  early loader:
 15 *  Copyright (C) 2013 Advanced Micro Devices, Inc.
 16 *
 17 *  Author: Jacob Shin <jacob.shin@amd.com>
 18 *  Fixes: Borislav Petkov <bp@suse.de>
 19 *
 20 *  Licensed under the terms of the GNU General Public
 21 *  License version 2. See file COPYING for details.
 22 */
 23#define pr_fmt(fmt) "microcode: " fmt
 24
 25#include <linux/earlycpio.h>
 26#include <linux/firmware.h>
 27#include <linux/uaccess.h>
 28#include <linux/vmalloc.h>
 29#include <linux/initrd.h>
 30#include <linux/kernel.h>
 31#include <linux/pci.h>
 32
 33#include <asm/microcode_amd.h>
 34#include <asm/microcode.h>
 35#include <asm/processor.h>
 36#include <asm/setup.h>
 37#include <asm/cpu.h>
 38#include <asm/msr.h>
 39
 40static struct equiv_cpu_entry *equiv_cpu_table;
 41
 42struct ucode_patch {
 43	struct list_head plist;
 44	void *data;
 45	u32 patch_id;
 46	u16 equiv_cpu;
 47};
 48
 49static LIST_HEAD(pcache);
 50
 51/*
 52 * This points to the current valid container of microcode patches which we will
 53 * save from the initrd before jettisoning its contents.
 54 */
 55static u8 *container;
 56static size_t container_size;
 57
 58static u32 ucode_new_rev;
 59u8 amd_ucode_patch[PATCH_MAX_SIZE];
 60static u16 this_equiv_id;
 61
 62static struct cpio_data ucode_cpio;
 63
 64/*
 65 * Microcode patch container file is prepended to the initrd in cpio format.
 66 * See Documentation/x86/early-microcode.txt
 67 */
 68static __initdata char ucode_path[] = "kernel/x86/microcode/AuthenticAMD.bin";
 69
 70static struct cpio_data __init find_ucode_in_initrd(void)
 71{
 72	long offset = 0;
 73	char *path;
 74	void *start;
 75	size_t size;
 76
 77#ifdef CONFIG_X86_32
 78	struct boot_params *p;
 79
 80	/*
 81	 * On 32-bit, early load occurs before paging is turned on so we need
 82	 * to use physical addresses.
 83	 */
 84	p       = (struct boot_params *)__pa_nodebug(&boot_params);
 85	path    = (char *)__pa_nodebug(ucode_path);
 86	start   = (void *)p->hdr.ramdisk_image;
 87	size    = p->hdr.ramdisk_size;
 88#else
 89	path    = ucode_path;
 90	start   = (void *)(boot_params.hdr.ramdisk_image + PAGE_OFFSET);
 91	size    = boot_params.hdr.ramdisk_size;
 92#endif
 93
 94	return find_cpio_data(path, start, size, &offset);
 95}
 96
 97static size_t compute_container_size(u8 *data, u32 total_size)
 98{
 99	size_t size = 0;
100	u32 *header = (u32 *)data;
101
102	if (header[0] != UCODE_MAGIC ||
103	    header[1] != UCODE_EQUIV_CPU_TABLE_TYPE || /* type */
104	    header[2] == 0)                            /* size */
105		return size;
106
107	size = header[2] + CONTAINER_HDR_SZ;
108	total_size -= size;
109	data += size;
110
111	while (total_size) {
112		u16 patch_size;
113
114		header = (u32 *)data;
115
116		if (header[0] != UCODE_UCODE_TYPE)
117			break;
118
119		/*
120		 * Sanity-check patch size.
121		 */
122		patch_size = header[1];
123		if (patch_size > PATCH_MAX_SIZE)
124			break;
125
126		size	   += patch_size + SECTION_HDR_SIZE;
127		data	   += patch_size + SECTION_HDR_SIZE;
128		total_size -= patch_size + SECTION_HDR_SIZE;
129	}
130
131	return size;
132}
133
134/*
135 * Early load occurs before we can vmalloc(). So we look for the microcode
136 * patch container file in initrd, traverse equivalent cpu table, look for a
137 * matching microcode patch, and update, all in initrd memory in place.
138 * When vmalloc() is available for use later -- on 64-bit during first AP load,
139 * and on 32-bit during save_microcode_in_initrd_amd() -- we can call
140 * load_microcode_amd() to save equivalent cpu table and microcode patches in
141 * kernel heap memory.
142 */
143static void apply_ucode_in_initrd(void *ucode, size_t size, bool save_patch)
144{
145	struct equiv_cpu_entry *eq;
146	size_t *cont_sz;
147	u32 *header;
148	u8  *data, **cont;
149	u8 (*patch)[PATCH_MAX_SIZE];
150	u16 eq_id = 0;
151	int offset, left;
152	u32 rev, eax, ebx, ecx, edx;
153	u32 *new_rev;
154
155#ifdef CONFIG_X86_32
156	new_rev = (u32 *)__pa_nodebug(&ucode_new_rev);
157	cont_sz = (size_t *)__pa_nodebug(&container_size);
158	cont	= (u8 **)__pa_nodebug(&container);
159	patch	= (u8 (*)[PATCH_MAX_SIZE])__pa_nodebug(&amd_ucode_patch);
160#else
161	new_rev = &ucode_new_rev;
162	cont_sz = &container_size;
163	cont	= &container;
164	patch	= &amd_ucode_patch;
165#endif
166
167	data   = ucode;
168	left   = size;
169	header = (u32 *)data;
170
171	/* find equiv cpu table */
172	if (header[0] != UCODE_MAGIC ||
173	    header[1] != UCODE_EQUIV_CPU_TABLE_TYPE || /* type */
174	    header[2] == 0)                            /* size */
175		return;
176
177	eax = 0x00000001;
178	ecx = 0;
179	native_cpuid(&eax, &ebx, &ecx, &edx);
180
181	while (left > 0) {
182		eq = (struct equiv_cpu_entry *)(data + CONTAINER_HDR_SZ);
183
184		*cont = data;
185
186		/* Advance past the container header */
187		offset = header[2] + CONTAINER_HDR_SZ;
188		data  += offset;
189		left  -= offset;
190
191		eq_id = find_equiv_id(eq, eax);
192		if (eq_id) {
193			this_equiv_id = eq_id;
194			*cont_sz = compute_container_size(*cont, left + offset);
195
196			/*
197			 * truncate how much we need to iterate over in the
198			 * ucode update loop below
199			 */
200			left = *cont_sz - offset;
201			break;
202		}
203
204		/*
205		 * support multiple container files appended together. if this
206		 * one does not have a matching equivalent cpu entry, we fast
207		 * forward to the next container file.
208		 */
209		while (left > 0) {
210			header = (u32 *)data;
211			if (header[0] == UCODE_MAGIC &&
212			    header[1] == UCODE_EQUIV_CPU_TABLE_TYPE)
213				break;
214
215			offset = header[1] + SECTION_HDR_SIZE;
216			data  += offset;
217			left  -= offset;
218		}
219
220		/* mark where the next microcode container file starts */
221		offset    = data - (u8 *)ucode;
222		ucode     = data;
223	}
224
225	if (!eq_id) {
226		*cont = NULL;
227		*cont_sz = 0;
228		return;
229	}
230
231	if (check_current_patch_level(&rev, true))
232		return;
233
234	while (left > 0) {
235		struct microcode_amd *mc;
236
237		header = (u32 *)data;
238		if (header[0] != UCODE_UCODE_TYPE || /* type */
239		    header[1] == 0)                  /* size */
240			break;
241
242		mc = (struct microcode_amd *)(data + SECTION_HDR_SIZE);
243
244		if (eq_id == mc->hdr.processor_rev_id && rev < mc->hdr.patch_id) {
245
246			if (!__apply_microcode_amd(mc)) {
247				rev = mc->hdr.patch_id;
248				*new_rev = rev;
249
250				if (save_patch)
251					memcpy(patch, mc,
252					       min_t(u32, header[1], PATCH_MAX_SIZE));
253			}
254		}
255
256		offset  = header[1] + SECTION_HDR_SIZE;
257		data   += offset;
258		left   -= offset;
259	}
260}
261
262static bool __init load_builtin_amd_microcode(struct cpio_data *cp,
263					      unsigned int family)
264{
265#ifdef CONFIG_X86_64
266	char fw_name[36] = "amd-ucode/microcode_amd.bin";
267
268	if (family >= 0x15)
269		snprintf(fw_name, sizeof(fw_name),
270			 "amd-ucode/microcode_amd_fam%.2xh.bin", family);
271
272	return get_builtin_firmware(cp, fw_name);
273#else
274	return false;
275#endif
276}
277
278void __init load_ucode_amd_bsp(unsigned int family)
279{
280	struct cpio_data cp;
281	void **data;
282	size_t *size;
283
284#ifdef CONFIG_X86_32
285	data =  (void **)__pa_nodebug(&ucode_cpio.data);
286	size = (size_t *)__pa_nodebug(&ucode_cpio.size);
287#else
288	data = &ucode_cpio.data;
289	size = &ucode_cpio.size;
290#endif
291
292	cp = find_ucode_in_initrd();
293	if (!cp.data) {
294		if (!load_builtin_amd_microcode(&cp, family))
295			return;
296	}
297
298	*data = cp.data;
299	*size = cp.size;
300
301	apply_ucode_in_initrd(cp.data, cp.size, true);
302}
303
304#ifdef CONFIG_X86_32
305/*
306 * On 32-bit, since AP's early load occurs before paging is turned on, we
307 * cannot traverse cpu_equiv_table and pcache in kernel heap memory. So during
308 * cold boot, AP will apply_ucode_in_initrd() just like the BSP. During
309 * save_microcode_in_initrd_amd() BSP's patch is copied to amd_ucode_patch,
310 * which is used upon resume from suspend.
311 */
312void load_ucode_amd_ap(void)
313{
314	struct microcode_amd *mc;
315	size_t *usize;
316	void **ucode;
317
318	mc = (struct microcode_amd *)__pa_nodebug(amd_ucode_patch);
319	if (mc->hdr.patch_id && mc->hdr.processor_rev_id) {
320		__apply_microcode_amd(mc);
321		return;
322	}
323
324	ucode = (void *)__pa_nodebug(&container);
325	usize = (size_t *)__pa_nodebug(&container_size);
326
327	if (!*ucode || !*usize)
328		return;
329
330	apply_ucode_in_initrd(*ucode, *usize, false);
331}
332
333static void __init collect_cpu_sig_on_bsp(void *arg)
334{
335	unsigned int cpu = smp_processor_id();
336	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
337
338	uci->cpu_sig.sig = cpuid_eax(0x00000001);
339}
340
341static void __init get_bsp_sig(void)
342{
343	unsigned int bsp = boot_cpu_data.cpu_index;
344	struct ucode_cpu_info *uci = ucode_cpu_info + bsp;
345
346	if (!uci->cpu_sig.sig)
347		smp_call_function_single(bsp, collect_cpu_sig_on_bsp, NULL, 1);
348}
349#else
350void load_ucode_amd_ap(void)
351{
352	unsigned int cpu = smp_processor_id();
353	struct equiv_cpu_entry *eq;
354	struct microcode_amd *mc;
355	u32 rev, eax;
356	u16 eq_id;
357
358	/* Exit if called on the BSP. */
359	if (!cpu)
360		return;
361
362	if (!container)
363		return;
364
365	/*
366	 * 64-bit runs with paging enabled, thus early==false.
367	 */
368	if (check_current_patch_level(&rev, false))
369		return;
370
371	eax = cpuid_eax(0x00000001);
372	eq  = (struct equiv_cpu_entry *)(container + CONTAINER_HDR_SZ);
373
374	eq_id = find_equiv_id(eq, eax);
375	if (!eq_id)
376		return;
377
378	if (eq_id == this_equiv_id) {
379		mc = (struct microcode_amd *)amd_ucode_patch;
380
381		if (mc && rev < mc->hdr.patch_id) {
382			if (!__apply_microcode_amd(mc))
383				ucode_new_rev = mc->hdr.patch_id;
384		}
385
386	} else {
387		if (!ucode_cpio.data)
388			return;
389
390		/*
391		 * AP has a different equivalence ID than BSP, looks like
392		 * mixed-steppings silicon so go through the ucode blob anew.
393		 */
394		apply_ucode_in_initrd(ucode_cpio.data, ucode_cpio.size, false);
395	}
396}
397#endif
398
399int __init save_microcode_in_initrd_amd(void)
400{
401	unsigned long cont;
402	int retval = 0;
403	enum ucode_state ret;
404	u8 *cont_va;
405	u32 eax;
406
407	if (!container)
408		return -EINVAL;
409
410#ifdef CONFIG_X86_32
411	get_bsp_sig();
412	cont	= (unsigned long)container;
413	cont_va = __va(container);
414#else
415	/*
416	 * We need the physical address of the container for both bitness since
417	 * boot_params.hdr.ramdisk_image is a physical address.
418	 */
419	cont    = __pa(container);
420	cont_va = container;
421#endif
422
423	/*
424	 * Take into account the fact that the ramdisk might get relocated and
425	 * therefore we need to recompute the container's position in virtual
426	 * memory space.
427	 */
428	if (relocated_ramdisk)
429		container = (u8 *)(__va(relocated_ramdisk) +
430			     (cont - boot_params.hdr.ramdisk_image));
431	else
432		container = cont_va;
433
434	eax   = cpuid_eax(0x00000001);
435	eax   = ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff);
436
437	ret = load_microcode_amd(smp_processor_id(), eax, container, container_size);
438	if (ret != UCODE_OK)
439		retval = -EINVAL;
440
441	/*
442	 * This will be freed any msec now, stash patches for the current
443	 * family and switch to patch cache for cpu hotplug, etc later.
444	 */
445	container = NULL;
446	container_size = 0;
447
448	return retval;
449}
450
451void reload_ucode_amd(void)
452{
453	struct microcode_amd *mc;
454	u32 rev;
455
456	/*
457	 * early==false because this is a syscore ->resume path and by
458	 * that time paging is long enabled.
459	 */
460	if (check_current_patch_level(&rev, false))
461		return;
462
463	mc = (struct microcode_amd *)amd_ucode_patch;
464
465	if (mc && rev < mc->hdr.patch_id) {
466		if (!__apply_microcode_amd(mc)) {
467			ucode_new_rev = mc->hdr.patch_id;
468			pr_info("reload patch_level=0x%08x\n", ucode_new_rev);
469		}
470	}
471}
472static u16 __find_equiv_id(unsigned int cpu)
473{
474	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
475	return find_equiv_id(equiv_cpu_table, uci->cpu_sig.sig);
476}
477
478static u32 find_cpu_family_by_equiv_cpu(u16 equiv_cpu)
479{
480	int i = 0;
481
482	BUG_ON(!equiv_cpu_table);
483
484	while (equiv_cpu_table[i].equiv_cpu != 0) {
485		if (equiv_cpu == equiv_cpu_table[i].equiv_cpu)
486			return equiv_cpu_table[i].installed_cpu;
487		i++;
488	}
489	return 0;
490}
491
492/*
493 * a small, trivial cache of per-family ucode patches
494 */
495static struct ucode_patch *cache_find_patch(u16 equiv_cpu)
496{
497	struct ucode_patch *p;
498
499	list_for_each_entry(p, &pcache, plist)
500		if (p->equiv_cpu == equiv_cpu)
501			return p;
502	return NULL;
503}
504
505static void update_cache(struct ucode_patch *new_patch)
506{
507	struct ucode_patch *p;
508
509	list_for_each_entry(p, &pcache, plist) {
510		if (p->equiv_cpu == new_patch->equiv_cpu) {
511			if (p->patch_id >= new_patch->patch_id)
512				/* we already have the latest patch */
513				return;
514
515			list_replace(&p->plist, &new_patch->plist);
516			kfree(p->data);
517			kfree(p);
518			return;
519		}
520	}
521	/* no patch found, add it */
522	list_add_tail(&new_patch->plist, &pcache);
523}
524
525static void free_cache(void)
526{
527	struct ucode_patch *p, *tmp;
528
529	list_for_each_entry_safe(p, tmp, &pcache, plist) {
530		__list_del(p->plist.prev, p->plist.next);
531		kfree(p->data);
532		kfree(p);
533	}
534}
535
536static struct ucode_patch *find_patch(unsigned int cpu)
537{
538	u16 equiv_id;
539
540	equiv_id = __find_equiv_id(cpu);
541	if (!equiv_id)
542		return NULL;
543
544	return cache_find_patch(equiv_id);
545}
546
547static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
548{
549	struct cpuinfo_x86 *c = &cpu_data(cpu);
550	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
551	struct ucode_patch *p;
552
553	csig->sig = cpuid_eax(0x00000001);
554	csig->rev = c->microcode;
555
556	/*
557	 * a patch could have been loaded early, set uci->mc so that
558	 * mc_bp_resume() can call apply_microcode()
559	 */
560	p = find_patch(cpu);
561	if (p && (p->patch_id == csig->rev))
562		uci->mc = p->data;
563
564	pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);
565
566	return 0;
567}
568
569static unsigned int verify_patch_size(u8 family, u32 patch_size,
570				      unsigned int size)
571{
572	u32 max_size;
573
574#define F1XH_MPB_MAX_SIZE 2048
575#define F14H_MPB_MAX_SIZE 1824
576#define F15H_MPB_MAX_SIZE 4096
577#define F16H_MPB_MAX_SIZE 3458
578
579	switch (family) {
580	case 0x14:
581		max_size = F14H_MPB_MAX_SIZE;
582		break;
583	case 0x15:
584		max_size = F15H_MPB_MAX_SIZE;
585		break;
586	case 0x16:
587		max_size = F16H_MPB_MAX_SIZE;
588		break;
589	default:
590		max_size = F1XH_MPB_MAX_SIZE;
591		break;
592	}
593
594	if (patch_size > min_t(u32, size, max_size)) {
595		pr_err("patch size mismatch\n");
596		return 0;
597	}
598
599	return patch_size;
600}
601
602/*
603 * Those patch levels cannot be updated to newer ones and thus should be final.
604 */
605static u32 final_levels[] = {
606	0x01000098,
607	0x0100009f,
608	0x010000af,
609	0, /* T-101 terminator */
610};
611
612/*
613 * Check the current patch level on this CPU.
614 *
615 * @rev: Use it to return the patch level. It is set to 0 in the case of
616 * error.
617 *
618 * Returns:
619 *  - true: if update should stop
620 *  - false: otherwise
621 */
622bool check_current_patch_level(u32 *rev, bool early)
623{
624	u32 lvl, dummy, i;
625	bool ret = false;
626	u32 *levels;
627
628	native_rdmsr(MSR_AMD64_PATCH_LEVEL, lvl, dummy);
629
630	if (IS_ENABLED(CONFIG_X86_32) && early)
631		levels = (u32 *)__pa_nodebug(&final_levels);
632	else
633		levels = final_levels;
634
635	for (i = 0; levels[i]; i++) {
636		if (lvl == levels[i]) {
637			lvl = 0;
638			ret = true;
639			break;
640		}
641	}
642
643	if (rev)
644		*rev = lvl;
645
646	return ret;
647}
648
649int __apply_microcode_amd(struct microcode_amd *mc_amd)
650{
651	u32 rev, dummy;
652
653	native_wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);
654
655	/* verify patch application was successful */
656	native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
657	if (rev != mc_amd->hdr.patch_id)
658		return -1;
659
660	return 0;
661}
662
663int apply_microcode_amd(int cpu)
664{
665	struct cpuinfo_x86 *c = &cpu_data(cpu);
666	struct microcode_amd *mc_amd;
667	struct ucode_cpu_info *uci;
668	struct ucode_patch *p;
669	u32 rev;
670
671	BUG_ON(raw_smp_processor_id() != cpu);
672
673	uci = ucode_cpu_info + cpu;
674
675	p = find_patch(cpu);
676	if (!p)
677		return 0;
678
679	mc_amd  = p->data;
680	uci->mc = p->data;
681
682	if (check_current_patch_level(&rev, false))
683		return -1;
684
685	/* need to apply patch? */
686	if (rev >= mc_amd->hdr.patch_id) {
687		c->microcode = rev;
688		uci->cpu_sig.rev = rev;
689		return 0;
690	}
691
692	if (__apply_microcode_amd(mc_amd)) {
693		pr_err("CPU%d: update failed for patch_level=0x%08x\n",
694			cpu, mc_amd->hdr.patch_id);
695		return -1;
696	}
697	pr_info("CPU%d: new patch_level=0x%08x\n", cpu,
698		mc_amd->hdr.patch_id);
699
700	uci->cpu_sig.rev = mc_amd->hdr.patch_id;
701	c->microcode = mc_amd->hdr.patch_id;
702
703	return 0;
704}
705
706static int install_equiv_cpu_table(const u8 *buf)
707{
708	unsigned int *ibuf = (unsigned int *)buf;
709	unsigned int type = ibuf[1];
710	unsigned int size = ibuf[2];
711
712	if (type != UCODE_EQUIV_CPU_TABLE_TYPE || !size) {
713		pr_err("empty section/"
714		       "invalid type field in container file section header\n");
715		return -EINVAL;
716	}
717
718	equiv_cpu_table = vmalloc(size);
719	if (!equiv_cpu_table) {
720		pr_err("failed to allocate equivalent CPU table\n");
721		return -ENOMEM;
722	}
723
724	memcpy(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size);
725
726	/* add header length */
727	return size + CONTAINER_HDR_SZ;
728}
729
730static void free_equiv_cpu_table(void)
731{
732	vfree(equiv_cpu_table);
733	equiv_cpu_table = NULL;
734}
735
736static void cleanup(void)
737{
738	free_equiv_cpu_table();
739	free_cache();
740}
741
742/*
743 * We return the current size even if some of the checks failed so that
744 * we can skip over the next patch. If we return a negative value, we
745 * signal a grave error like a memory allocation has failed and the
746 * driver cannot continue functioning normally. In such cases, we tear
747 * down everything we've used up so far and exit.
748 */
749static int verify_and_add_patch(u8 family, u8 *fw, unsigned int leftover)
750{
751	struct microcode_header_amd *mc_hdr;
752	struct ucode_patch *patch;
753	unsigned int patch_size, crnt_size, ret;
754	u32 proc_fam;
755	u16 proc_id;
756
757	patch_size  = *(u32 *)(fw + 4);
758	crnt_size   = patch_size + SECTION_HDR_SIZE;
759	mc_hdr	    = (struct microcode_header_amd *)(fw + SECTION_HDR_SIZE);
760	proc_id	    = mc_hdr->processor_rev_id;
761
762	proc_fam = find_cpu_family_by_equiv_cpu(proc_id);
763	if (!proc_fam) {
764		pr_err("No patch family for equiv ID: 0x%04x\n", proc_id);
765		return crnt_size;
766	}
767
768	/* check if patch is for the current family */
769	proc_fam = ((proc_fam >> 8) & 0xf) + ((proc_fam >> 20) & 0xff);
770	if (proc_fam != family)
771		return crnt_size;
772
773	if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) {
774		pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n",
775			mc_hdr->patch_id);
776		return crnt_size;
777	}
778
779	ret = verify_patch_size(family, patch_size, leftover);
780	if (!ret) {
781		pr_err("Patch-ID 0x%08x: size mismatch.\n", mc_hdr->patch_id);
782		return crnt_size;
783	}
784
785	patch = kzalloc(sizeof(*patch), GFP_KERNEL);
786	if (!patch) {
787		pr_err("Patch allocation failure.\n");
788		return -EINVAL;
789	}
790
791	patch->data = kmemdup(fw + SECTION_HDR_SIZE, patch_size, GFP_KERNEL);
792	if (!patch->data) {
793		pr_err("Patch data allocation failure.\n");
794		kfree(patch);
795		return -EINVAL;
796	}
797
798	INIT_LIST_HEAD(&patch->plist);
799	patch->patch_id  = mc_hdr->patch_id;
800	patch->equiv_cpu = proc_id;
801
802	pr_debug("%s: Added patch_id: 0x%08x, proc_id: 0x%04x\n",
803		 __func__, patch->patch_id, proc_id);
804
805	/* ... and add to cache. */
806	update_cache(patch);
807
808	return crnt_size;
809}
810
811static enum ucode_state __load_microcode_amd(u8 family, const u8 *data,
812					     size_t size)
813{
814	enum ucode_state ret = UCODE_ERROR;
815	unsigned int leftover;
816	u8 *fw = (u8 *)data;
817	int crnt_size = 0;
818	int offset;
819
820	offset = install_equiv_cpu_table(data);
821	if (offset < 0) {
822		pr_err("failed to create equivalent cpu table\n");
823		return ret;
824	}
825	fw += offset;
826	leftover = size - offset;
827
828	if (*(u32 *)fw != UCODE_UCODE_TYPE) {
829		pr_err("invalid type field in container file section header\n");
830		free_equiv_cpu_table();
831		return ret;
832	}
833
834	while (leftover) {
835		crnt_size = verify_and_add_patch(family, fw, leftover);
836		if (crnt_size < 0)
837			return ret;
838
839		fw	 += crnt_size;
840		leftover -= crnt_size;
841	}
842
843	return UCODE_OK;
844}
845
846enum ucode_state load_microcode_amd(int cpu, u8 family, const u8 *data, size_t size)
847{
848	enum ucode_state ret;
849
850	/* free old equiv table */
851	free_equiv_cpu_table();
852
853	ret = __load_microcode_amd(family, data, size);
854
855	if (ret != UCODE_OK)
856		cleanup();
857
858#ifdef CONFIG_X86_32
859	/* save BSP's matching patch for early load */
860	if (cpu_data(cpu).cpu_index == boot_cpu_data.cpu_index) {
861		struct ucode_patch *p = find_patch(cpu);
862		if (p) {
863			memset(amd_ucode_patch, 0, PATCH_MAX_SIZE);
864			memcpy(amd_ucode_patch, p->data, min_t(u32, ksize(p->data),
865							       PATCH_MAX_SIZE));
866		}
867	}
868#endif
869	return ret;
870}
871
872/*
873 * AMD microcode firmware naming convention, up to family 15h they are in
874 * the legacy file:
875 *
876 *    amd-ucode/microcode_amd.bin
877 *
878 * This legacy file is always smaller than 2K in size.
879 *
880 * Beginning with family 15h, they are in family-specific firmware files:
881 *
882 *    amd-ucode/microcode_amd_fam15h.bin
883 *    amd-ucode/microcode_amd_fam16h.bin
884 *    ...
885 *
886 * These might be larger than 2K.
887 */
888static enum ucode_state request_microcode_amd(int cpu, struct device *device,
889					      bool refresh_fw)
890{
891	char fw_name[36] = "amd-ucode/microcode_amd.bin";
892	struct cpuinfo_x86 *c = &cpu_data(cpu);
893	enum ucode_state ret = UCODE_NFOUND;
894	const struct firmware *fw;
895
896	/* reload ucode container only on the boot cpu */
897	if (!refresh_fw || c->cpu_index != boot_cpu_data.cpu_index)
898		return UCODE_OK;
899
900	if (c->x86 >= 0x15)
901		snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86);
902
903	if (request_firmware_direct(&fw, (const char *)fw_name, device)) {
904		pr_debug("failed to load file %s\n", fw_name);
905		goto out;
906	}
907
908	ret = UCODE_ERROR;
909	if (*(u32 *)fw->data != UCODE_MAGIC) {
910		pr_err("invalid magic value (0x%08x)\n", *(u32 *)fw->data);
911		goto fw_release;
912	}
913
914	ret = load_microcode_amd(cpu, c->x86, fw->data, fw->size);
915
916 fw_release:
917	release_firmware(fw);
918
919 out:
920	return ret;
921}
922
923static enum ucode_state
924request_microcode_user(int cpu, const void __user *buf, size_t size)
925{
926	return UCODE_ERROR;
927}
928
929static void microcode_fini_cpu_amd(int cpu)
930{
931	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
932
933	uci->mc = NULL;
934}
935
936static struct microcode_ops microcode_amd_ops = {
937	.request_microcode_user           = request_microcode_user,
938	.request_microcode_fw             = request_microcode_amd,
939	.collect_cpu_info                 = collect_cpu_info_amd,
940	.apply_microcode                  = apply_microcode_amd,
941	.microcode_fini_cpu               = microcode_fini_cpu_amd,
942};
943
944struct microcode_ops * __init init_amd_microcode(void)
945{
946	struct cpuinfo_x86 *c = &boot_cpu_data;
947
948	if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
949		pr_warn("AMD CPU family 0x%x not supported\n", c->x86);
950		return NULL;
951	}
952
953	if (ucode_new_rev)
954		pr_info_once("microcode updated early to new patch_level=0x%08x\n",
955			     ucode_new_rev);
956
957	return &microcode_amd_ops;
958}
959
960void __exit exit_amd_microcode(void)
961{
962	cleanup();
963}