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1/* Performance event support for sparc64.
2 *
3 * Copyright (C) 2009, 2010 David S. Miller <davem@davemloft.net>
4 *
5 * This code is based almost entirely upon the x86 perf event
6 * code, which is:
7 *
8 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
9 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
10 * Copyright (C) 2009 Jaswinder Singh Rajput
11 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
12 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
13 */
14
15#include <linux/perf_event.h>
16#include <linux/kprobes.h>
17#include <linux/ftrace.h>
18#include <linux/kernel.h>
19#include <linux/kdebug.h>
20#include <linux/mutex.h>
21
22#include <asm/stacktrace.h>
23#include <asm/cpudata.h>
24#include <asm/uaccess.h>
25#include <linux/atomic.h>
26#include <asm/nmi.h>
27#include <asm/pcr.h>
28#include <asm/perfctr.h>
29#include <asm/cacheflush.h>
30
31#include "kernel.h"
32#include "kstack.h"
33
34/* Sparc64 chips have two performance counters, 32-bits each, with
35 * overflow interrupts generated on transition from 0xffffffff to 0.
36 * The counters are accessed in one go using a 64-bit register.
37 *
38 * Both counters are controlled using a single control register. The
39 * only way to stop all sampling is to clear all of the context (user,
40 * supervisor, hypervisor) sampling enable bits. But these bits apply
41 * to both counters, thus the two counters can't be enabled/disabled
42 * individually.
43 *
44 * The control register has two event fields, one for each of the two
45 * counters. It's thus nearly impossible to have one counter going
46 * while keeping the other one stopped. Therefore it is possible to
47 * get overflow interrupts for counters not currently "in use" and
48 * that condition must be checked in the overflow interrupt handler.
49 *
50 * So we use a hack, in that we program inactive counters with the
51 * "sw_count0" and "sw_count1" events. These count how many times
52 * the instruction "sethi %hi(0xfc000), %g0" is executed. It's an
53 * unusual way to encode a NOP and therefore will not trigger in
54 * normal code.
55 */
56
57#define MAX_HWEVENTS 2
58#define MAX_PERIOD ((1UL << 32) - 1)
59
60#define PIC_UPPER_INDEX 0
61#define PIC_LOWER_INDEX 1
62#define PIC_NO_INDEX -1
63
64struct cpu_hw_events {
65 /* Number of events currently scheduled onto this cpu.
66 * This tells how many entries in the arrays below
67 * are valid.
68 */
69 int n_events;
70
71 /* Number of new events added since the last hw_perf_disable().
72 * This works because the perf event layer always adds new
73 * events inside of a perf_{disable,enable}() sequence.
74 */
75 int n_added;
76
77 /* Array of events current scheduled on this cpu. */
78 struct perf_event *event[MAX_HWEVENTS];
79
80 /* Array of encoded longs, specifying the %pcr register
81 * encoding and the mask of PIC counters this even can
82 * be scheduled on. See perf_event_encode() et al.
83 */
84 unsigned long events[MAX_HWEVENTS];
85
86 /* The current counter index assigned to an event. When the
87 * event hasn't been programmed into the cpu yet, this will
88 * hold PIC_NO_INDEX. The event->hw.idx value tells us where
89 * we ought to schedule the event.
90 */
91 int current_idx[MAX_HWEVENTS];
92
93 /* Software copy of %pcr register on this cpu. */
94 u64 pcr;
95
96 /* Enabled/disable state. */
97 int enabled;
98
99 unsigned int group_flag;
100};
101DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { .enabled = 1, };
102
103/* An event map describes the characteristics of a performance
104 * counter event. In particular it gives the encoding as well as
105 * a mask telling which counters the event can be measured on.
106 */
107struct perf_event_map {
108 u16 encoding;
109 u8 pic_mask;
110#define PIC_NONE 0x00
111#define PIC_UPPER 0x01
112#define PIC_LOWER 0x02
113};
114
115/* Encode a perf_event_map entry into a long. */
116static unsigned long perf_event_encode(const struct perf_event_map *pmap)
117{
118 return ((unsigned long) pmap->encoding << 16) | pmap->pic_mask;
119}
120
121static u8 perf_event_get_msk(unsigned long val)
122{
123 return val & 0xff;
124}
125
126static u64 perf_event_get_enc(unsigned long val)
127{
128 return val >> 16;
129}
130
131#define C(x) PERF_COUNT_HW_CACHE_##x
132
133#define CACHE_OP_UNSUPPORTED 0xfffe
134#define CACHE_OP_NONSENSE 0xffff
135
136typedef struct perf_event_map cache_map_t
137 [PERF_COUNT_HW_CACHE_MAX]
138 [PERF_COUNT_HW_CACHE_OP_MAX]
139 [PERF_COUNT_HW_CACHE_RESULT_MAX];
140
141struct sparc_pmu {
142 const struct perf_event_map *(*event_map)(int);
143 const cache_map_t *cache_map;
144 int max_events;
145 int upper_shift;
146 int lower_shift;
147 int event_mask;
148 int hv_bit;
149 int irq_bit;
150 int upper_nop;
151 int lower_nop;
152};
153
154static const struct perf_event_map ultra3_perfmon_event_map[] = {
155 [PERF_COUNT_HW_CPU_CYCLES] = { 0x0000, PIC_UPPER | PIC_LOWER },
156 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x0001, PIC_UPPER | PIC_LOWER },
157 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0009, PIC_LOWER },
158 [PERF_COUNT_HW_CACHE_MISSES] = { 0x0009, PIC_UPPER },
159};
160
161static const struct perf_event_map *ultra3_event_map(int event_id)
162{
163 return &ultra3_perfmon_event_map[event_id];
164}
165
166static const cache_map_t ultra3_cache_map = {
167[C(L1D)] = {
168 [C(OP_READ)] = {
169 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
170 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
171 },
172 [C(OP_WRITE)] = {
173 [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER },
174 [C(RESULT_MISS)] = { 0x0a, PIC_UPPER },
175 },
176 [C(OP_PREFETCH)] = {
177 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
178 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
179 },
180},
181[C(L1I)] = {
182 [C(OP_READ)] = {
183 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
184 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
185 },
186 [ C(OP_WRITE) ] = {
187 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
188 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE },
189 },
190 [ C(OP_PREFETCH) ] = {
191 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
192 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
193 },
194},
195[C(LL)] = {
196 [C(OP_READ)] = {
197 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER, },
198 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER, },
199 },
200 [C(OP_WRITE)] = {
201 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER },
202 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER },
203 },
204 [C(OP_PREFETCH)] = {
205 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
206 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
207 },
208},
209[C(DTLB)] = {
210 [C(OP_READ)] = {
211 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
212 [C(RESULT_MISS)] = { 0x12, PIC_UPPER, },
213 },
214 [ C(OP_WRITE) ] = {
215 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
216 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
217 },
218 [ C(OP_PREFETCH) ] = {
219 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
220 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
221 },
222},
223[C(ITLB)] = {
224 [C(OP_READ)] = {
225 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
226 [C(RESULT_MISS)] = { 0x11, PIC_UPPER, },
227 },
228 [ C(OP_WRITE) ] = {
229 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
230 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
231 },
232 [ C(OP_PREFETCH) ] = {
233 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
234 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
235 },
236},
237[C(BPU)] = {
238 [C(OP_READ)] = {
239 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
240 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
241 },
242 [ C(OP_WRITE) ] = {
243 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
244 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
245 },
246 [ C(OP_PREFETCH) ] = {
247 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
248 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
249 },
250},
251[C(NODE)] = {
252 [C(OP_READ)] = {
253 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
254 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
255 },
256 [ C(OP_WRITE) ] = {
257 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
258 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
259 },
260 [ C(OP_PREFETCH) ] = {
261 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
262 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
263 },
264},
265};
266
267static const struct sparc_pmu ultra3_pmu = {
268 .event_map = ultra3_event_map,
269 .cache_map = &ultra3_cache_map,
270 .max_events = ARRAY_SIZE(ultra3_perfmon_event_map),
271 .upper_shift = 11,
272 .lower_shift = 4,
273 .event_mask = 0x3f,
274 .upper_nop = 0x1c,
275 .lower_nop = 0x14,
276};
277
278/* Niagara1 is very limited. The upper PIC is hard-locked to count
279 * only instructions, so it is free running which creates all kinds of
280 * problems. Some hardware designs make one wonder if the creator
281 * even looked at how this stuff gets used by software.
282 */
283static const struct perf_event_map niagara1_perfmon_event_map[] = {
284 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, PIC_UPPER },
285 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, PIC_UPPER },
286 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0, PIC_NONE },
287 [PERF_COUNT_HW_CACHE_MISSES] = { 0x03, PIC_LOWER },
288};
289
290static const struct perf_event_map *niagara1_event_map(int event_id)
291{
292 return &niagara1_perfmon_event_map[event_id];
293}
294
295static const cache_map_t niagara1_cache_map = {
296[C(L1D)] = {
297 [C(OP_READ)] = {
298 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
299 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
300 },
301 [C(OP_WRITE)] = {
302 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
303 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
304 },
305 [C(OP_PREFETCH)] = {
306 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
307 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
308 },
309},
310[C(L1I)] = {
311 [C(OP_READ)] = {
312 [C(RESULT_ACCESS)] = { 0x00, PIC_UPPER },
313 [C(RESULT_MISS)] = { 0x02, PIC_LOWER, },
314 },
315 [ C(OP_WRITE) ] = {
316 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
317 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE },
318 },
319 [ C(OP_PREFETCH) ] = {
320 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
321 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
322 },
323},
324[C(LL)] = {
325 [C(OP_READ)] = {
326 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
327 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
328 },
329 [C(OP_WRITE)] = {
330 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
331 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
332 },
333 [C(OP_PREFETCH)] = {
334 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
335 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
336 },
337},
338[C(DTLB)] = {
339 [C(OP_READ)] = {
340 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
341 [C(RESULT_MISS)] = { 0x05, PIC_LOWER, },
342 },
343 [ C(OP_WRITE) ] = {
344 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
345 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
346 },
347 [ C(OP_PREFETCH) ] = {
348 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
349 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
350 },
351},
352[C(ITLB)] = {
353 [C(OP_READ)] = {
354 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
355 [C(RESULT_MISS)] = { 0x04, PIC_LOWER, },
356 },
357 [ C(OP_WRITE) ] = {
358 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
359 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
360 },
361 [ C(OP_PREFETCH) ] = {
362 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
363 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
364 },
365},
366[C(BPU)] = {
367 [C(OP_READ)] = {
368 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
369 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
370 },
371 [ C(OP_WRITE) ] = {
372 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
373 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
374 },
375 [ C(OP_PREFETCH) ] = {
376 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
377 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
378 },
379},
380[C(NODE)] = {
381 [C(OP_READ)] = {
382 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
383 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
384 },
385 [ C(OP_WRITE) ] = {
386 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
387 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
388 },
389 [ C(OP_PREFETCH) ] = {
390 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
391 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
392 },
393},
394};
395
396static const struct sparc_pmu niagara1_pmu = {
397 .event_map = niagara1_event_map,
398 .cache_map = &niagara1_cache_map,
399 .max_events = ARRAY_SIZE(niagara1_perfmon_event_map),
400 .upper_shift = 0,
401 .lower_shift = 4,
402 .event_mask = 0x7,
403 .upper_nop = 0x0,
404 .lower_nop = 0x0,
405};
406
407static const struct perf_event_map niagara2_perfmon_event_map[] = {
408 [PERF_COUNT_HW_CPU_CYCLES] = { 0x02ff, PIC_UPPER | PIC_LOWER },
409 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x02ff, PIC_UPPER | PIC_LOWER },
410 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0208, PIC_UPPER | PIC_LOWER },
411 [PERF_COUNT_HW_CACHE_MISSES] = { 0x0302, PIC_UPPER | PIC_LOWER },
412 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x0201, PIC_UPPER | PIC_LOWER },
413 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x0202, PIC_UPPER | PIC_LOWER },
414};
415
416static const struct perf_event_map *niagara2_event_map(int event_id)
417{
418 return &niagara2_perfmon_event_map[event_id];
419}
420
421static const cache_map_t niagara2_cache_map = {
422[C(L1D)] = {
423 [C(OP_READ)] = {
424 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
425 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
426 },
427 [C(OP_WRITE)] = {
428 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
429 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
430 },
431 [C(OP_PREFETCH)] = {
432 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
433 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
434 },
435},
436[C(L1I)] = {
437 [C(OP_READ)] = {
438 [C(RESULT_ACCESS)] = { 0x02ff, PIC_UPPER | PIC_LOWER, },
439 [C(RESULT_MISS)] = { 0x0301, PIC_UPPER | PIC_LOWER, },
440 },
441 [ C(OP_WRITE) ] = {
442 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
443 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE },
444 },
445 [ C(OP_PREFETCH) ] = {
446 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
447 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
448 },
449},
450[C(LL)] = {
451 [C(OP_READ)] = {
452 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
453 [C(RESULT_MISS)] = { 0x0330, PIC_UPPER | PIC_LOWER, },
454 },
455 [C(OP_WRITE)] = {
456 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
457 [C(RESULT_MISS)] = { 0x0320, PIC_UPPER | PIC_LOWER, },
458 },
459 [C(OP_PREFETCH)] = {
460 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
461 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
462 },
463},
464[C(DTLB)] = {
465 [C(OP_READ)] = {
466 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
467 [C(RESULT_MISS)] = { 0x0b08, PIC_UPPER | PIC_LOWER, },
468 },
469 [ C(OP_WRITE) ] = {
470 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
471 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
472 },
473 [ C(OP_PREFETCH) ] = {
474 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
475 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
476 },
477},
478[C(ITLB)] = {
479 [C(OP_READ)] = {
480 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
481 [C(RESULT_MISS)] = { 0xb04, PIC_UPPER | PIC_LOWER, },
482 },
483 [ C(OP_WRITE) ] = {
484 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
485 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
486 },
487 [ C(OP_PREFETCH) ] = {
488 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
489 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
490 },
491},
492[C(BPU)] = {
493 [C(OP_READ)] = {
494 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
495 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
496 },
497 [ C(OP_WRITE) ] = {
498 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
499 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
500 },
501 [ C(OP_PREFETCH) ] = {
502 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
503 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
504 },
505},
506[C(NODE)] = {
507 [C(OP_READ)] = {
508 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
509 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
510 },
511 [ C(OP_WRITE) ] = {
512 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
513 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
514 },
515 [ C(OP_PREFETCH) ] = {
516 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
517 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
518 },
519},
520};
521
522static const struct sparc_pmu niagara2_pmu = {
523 .event_map = niagara2_event_map,
524 .cache_map = &niagara2_cache_map,
525 .max_events = ARRAY_SIZE(niagara2_perfmon_event_map),
526 .upper_shift = 19,
527 .lower_shift = 6,
528 .event_mask = 0xfff,
529 .hv_bit = 0x8,
530 .irq_bit = 0x30,
531 .upper_nop = 0x220,
532 .lower_nop = 0x220,
533};
534
535static const struct sparc_pmu *sparc_pmu __read_mostly;
536
537static u64 event_encoding(u64 event_id, int idx)
538{
539 if (idx == PIC_UPPER_INDEX)
540 event_id <<= sparc_pmu->upper_shift;
541 else
542 event_id <<= sparc_pmu->lower_shift;
543 return event_id;
544}
545
546static u64 mask_for_index(int idx)
547{
548 return event_encoding(sparc_pmu->event_mask, idx);
549}
550
551static u64 nop_for_index(int idx)
552{
553 return event_encoding(idx == PIC_UPPER_INDEX ?
554 sparc_pmu->upper_nop :
555 sparc_pmu->lower_nop, idx);
556}
557
558static inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
559{
560 u64 val, mask = mask_for_index(idx);
561
562 val = cpuc->pcr;
563 val &= ~mask;
564 val |= hwc->config;
565 cpuc->pcr = val;
566
567 pcr_ops->write(cpuc->pcr);
568}
569
570static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
571{
572 u64 mask = mask_for_index(idx);
573 u64 nop = nop_for_index(idx);
574 u64 val;
575
576 val = cpuc->pcr;
577 val &= ~mask;
578 val |= nop;
579 cpuc->pcr = val;
580
581 pcr_ops->write(cpuc->pcr);
582}
583
584static u32 read_pmc(int idx)
585{
586 u64 val;
587
588 read_pic(val);
589 if (idx == PIC_UPPER_INDEX)
590 val >>= 32;
591
592 return val & 0xffffffff;
593}
594
595static void write_pmc(int idx, u64 val)
596{
597 u64 shift, mask, pic;
598
599 shift = 0;
600 if (idx == PIC_UPPER_INDEX)
601 shift = 32;
602
603 mask = ((u64) 0xffffffff) << shift;
604 val <<= shift;
605
606 read_pic(pic);
607 pic &= ~mask;
608 pic |= val;
609 write_pic(pic);
610}
611
612static u64 sparc_perf_event_update(struct perf_event *event,
613 struct hw_perf_event *hwc, int idx)
614{
615 int shift = 64 - 32;
616 u64 prev_raw_count, new_raw_count;
617 s64 delta;
618
619again:
620 prev_raw_count = local64_read(&hwc->prev_count);
621 new_raw_count = read_pmc(idx);
622
623 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
624 new_raw_count) != prev_raw_count)
625 goto again;
626
627 delta = (new_raw_count << shift) - (prev_raw_count << shift);
628 delta >>= shift;
629
630 local64_add(delta, &event->count);
631 local64_sub(delta, &hwc->period_left);
632
633 return new_raw_count;
634}
635
636static int sparc_perf_event_set_period(struct perf_event *event,
637 struct hw_perf_event *hwc, int idx)
638{
639 s64 left = local64_read(&hwc->period_left);
640 s64 period = hwc->sample_period;
641 int ret = 0;
642
643 if (unlikely(left <= -period)) {
644 left = period;
645 local64_set(&hwc->period_left, left);
646 hwc->last_period = period;
647 ret = 1;
648 }
649
650 if (unlikely(left <= 0)) {
651 left += period;
652 local64_set(&hwc->period_left, left);
653 hwc->last_period = period;
654 ret = 1;
655 }
656 if (left > MAX_PERIOD)
657 left = MAX_PERIOD;
658
659 local64_set(&hwc->prev_count, (u64)-left);
660
661 write_pmc(idx, (u64)(-left) & 0xffffffff);
662
663 perf_event_update_userpage(event);
664
665 return ret;
666}
667
668/* If performance event entries have been added, move existing
669 * events around (if necessary) and then assign new entries to
670 * counters.
671 */
672static u64 maybe_change_configuration(struct cpu_hw_events *cpuc, u64 pcr)
673{
674 int i;
675
676 if (!cpuc->n_added)
677 goto out;
678
679 /* Read in the counters which are moving. */
680 for (i = 0; i < cpuc->n_events; i++) {
681 struct perf_event *cp = cpuc->event[i];
682
683 if (cpuc->current_idx[i] != PIC_NO_INDEX &&
684 cpuc->current_idx[i] != cp->hw.idx) {
685 sparc_perf_event_update(cp, &cp->hw,
686 cpuc->current_idx[i]);
687 cpuc->current_idx[i] = PIC_NO_INDEX;
688 }
689 }
690
691 /* Assign to counters all unassigned events. */
692 for (i = 0; i < cpuc->n_events; i++) {
693 struct perf_event *cp = cpuc->event[i];
694 struct hw_perf_event *hwc = &cp->hw;
695 int idx = hwc->idx;
696 u64 enc;
697
698 if (cpuc->current_idx[i] != PIC_NO_INDEX)
699 continue;
700
701 sparc_perf_event_set_period(cp, hwc, idx);
702 cpuc->current_idx[i] = idx;
703
704 enc = perf_event_get_enc(cpuc->events[i]);
705 pcr &= ~mask_for_index(idx);
706 if (hwc->state & PERF_HES_STOPPED)
707 pcr |= nop_for_index(idx);
708 else
709 pcr |= event_encoding(enc, idx);
710 }
711out:
712 return pcr;
713}
714
715static void sparc_pmu_enable(struct pmu *pmu)
716{
717 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
718 u64 pcr;
719
720 if (cpuc->enabled)
721 return;
722
723 cpuc->enabled = 1;
724 barrier();
725
726 pcr = cpuc->pcr;
727 if (!cpuc->n_events) {
728 pcr = 0;
729 } else {
730 pcr = maybe_change_configuration(cpuc, pcr);
731
732 /* We require that all of the events have the same
733 * configuration, so just fetch the settings from the
734 * first entry.
735 */
736 cpuc->pcr = pcr | cpuc->event[0]->hw.config_base;
737 }
738
739 pcr_ops->write(cpuc->pcr);
740}
741
742static void sparc_pmu_disable(struct pmu *pmu)
743{
744 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
745 u64 val;
746
747 if (!cpuc->enabled)
748 return;
749
750 cpuc->enabled = 0;
751 cpuc->n_added = 0;
752
753 val = cpuc->pcr;
754 val &= ~(PCR_UTRACE | PCR_STRACE |
755 sparc_pmu->hv_bit | sparc_pmu->irq_bit);
756 cpuc->pcr = val;
757
758 pcr_ops->write(cpuc->pcr);
759}
760
761static int active_event_index(struct cpu_hw_events *cpuc,
762 struct perf_event *event)
763{
764 int i;
765
766 for (i = 0; i < cpuc->n_events; i++) {
767 if (cpuc->event[i] == event)
768 break;
769 }
770 BUG_ON(i == cpuc->n_events);
771 return cpuc->current_idx[i];
772}
773
774static void sparc_pmu_start(struct perf_event *event, int flags)
775{
776 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
777 int idx = active_event_index(cpuc, event);
778
779 if (flags & PERF_EF_RELOAD) {
780 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
781 sparc_perf_event_set_period(event, &event->hw, idx);
782 }
783
784 event->hw.state = 0;
785
786 sparc_pmu_enable_event(cpuc, &event->hw, idx);
787}
788
789static void sparc_pmu_stop(struct perf_event *event, int flags)
790{
791 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
792 int idx = active_event_index(cpuc, event);
793
794 if (!(event->hw.state & PERF_HES_STOPPED)) {
795 sparc_pmu_disable_event(cpuc, &event->hw, idx);
796 event->hw.state |= PERF_HES_STOPPED;
797 }
798
799 if (!(event->hw.state & PERF_HES_UPTODATE) && (flags & PERF_EF_UPDATE)) {
800 sparc_perf_event_update(event, &event->hw, idx);
801 event->hw.state |= PERF_HES_UPTODATE;
802 }
803}
804
805static void sparc_pmu_del(struct perf_event *event, int _flags)
806{
807 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
808 unsigned long flags;
809 int i;
810
811 local_irq_save(flags);
812 perf_pmu_disable(event->pmu);
813
814 for (i = 0; i < cpuc->n_events; i++) {
815 if (event == cpuc->event[i]) {
816 /* Absorb the final count and turn off the
817 * event.
818 */
819 sparc_pmu_stop(event, PERF_EF_UPDATE);
820
821 /* Shift remaining entries down into
822 * the existing slot.
823 */
824 while (++i < cpuc->n_events) {
825 cpuc->event[i - 1] = cpuc->event[i];
826 cpuc->events[i - 1] = cpuc->events[i];
827 cpuc->current_idx[i - 1] =
828 cpuc->current_idx[i];
829 }
830
831 perf_event_update_userpage(event);
832
833 cpuc->n_events--;
834 break;
835 }
836 }
837
838 perf_pmu_enable(event->pmu);
839 local_irq_restore(flags);
840}
841
842static void sparc_pmu_read(struct perf_event *event)
843{
844 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
845 int idx = active_event_index(cpuc, event);
846 struct hw_perf_event *hwc = &event->hw;
847
848 sparc_perf_event_update(event, hwc, idx);
849}
850
851static atomic_t active_events = ATOMIC_INIT(0);
852static DEFINE_MUTEX(pmc_grab_mutex);
853
854static void perf_stop_nmi_watchdog(void *unused)
855{
856 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
857
858 stop_nmi_watchdog(NULL);
859 cpuc->pcr = pcr_ops->read();
860}
861
862void perf_event_grab_pmc(void)
863{
864 if (atomic_inc_not_zero(&active_events))
865 return;
866
867 mutex_lock(&pmc_grab_mutex);
868 if (atomic_read(&active_events) == 0) {
869 if (atomic_read(&nmi_active) > 0) {
870 on_each_cpu(perf_stop_nmi_watchdog, NULL, 1);
871 BUG_ON(atomic_read(&nmi_active) != 0);
872 }
873 atomic_inc(&active_events);
874 }
875 mutex_unlock(&pmc_grab_mutex);
876}
877
878void perf_event_release_pmc(void)
879{
880 if (atomic_dec_and_mutex_lock(&active_events, &pmc_grab_mutex)) {
881 if (atomic_read(&nmi_active) == 0)
882 on_each_cpu(start_nmi_watchdog, NULL, 1);
883 mutex_unlock(&pmc_grab_mutex);
884 }
885}
886
887static const struct perf_event_map *sparc_map_cache_event(u64 config)
888{
889 unsigned int cache_type, cache_op, cache_result;
890 const struct perf_event_map *pmap;
891
892 if (!sparc_pmu->cache_map)
893 return ERR_PTR(-ENOENT);
894
895 cache_type = (config >> 0) & 0xff;
896 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
897 return ERR_PTR(-EINVAL);
898
899 cache_op = (config >> 8) & 0xff;
900 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
901 return ERR_PTR(-EINVAL);
902
903 cache_result = (config >> 16) & 0xff;
904 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
905 return ERR_PTR(-EINVAL);
906
907 pmap = &((*sparc_pmu->cache_map)[cache_type][cache_op][cache_result]);
908
909 if (pmap->encoding == CACHE_OP_UNSUPPORTED)
910 return ERR_PTR(-ENOENT);
911
912 if (pmap->encoding == CACHE_OP_NONSENSE)
913 return ERR_PTR(-EINVAL);
914
915 return pmap;
916}
917
918static void hw_perf_event_destroy(struct perf_event *event)
919{
920 perf_event_release_pmc();
921}
922
923/* Make sure all events can be scheduled into the hardware at
924 * the same time. This is simplified by the fact that we only
925 * need to support 2 simultaneous HW events.
926 *
927 * As a side effect, the evts[]->hw.idx values will be assigned
928 * on success. These are pending indexes. When the events are
929 * actually programmed into the chip, these values will propagate
930 * to the per-cpu cpuc->current_idx[] slots, see the code in
931 * maybe_change_configuration() for details.
932 */
933static int sparc_check_constraints(struct perf_event **evts,
934 unsigned long *events, int n_ev)
935{
936 u8 msk0 = 0, msk1 = 0;
937 int idx0 = 0;
938
939 /* This case is possible when we are invoked from
940 * hw_perf_group_sched_in().
941 */
942 if (!n_ev)
943 return 0;
944
945 if (n_ev > MAX_HWEVENTS)
946 return -1;
947
948 msk0 = perf_event_get_msk(events[0]);
949 if (n_ev == 1) {
950 if (msk0 & PIC_LOWER)
951 idx0 = 1;
952 goto success;
953 }
954 BUG_ON(n_ev != 2);
955 msk1 = perf_event_get_msk(events[1]);
956
957 /* If both events can go on any counter, OK. */
958 if (msk0 == (PIC_UPPER | PIC_LOWER) &&
959 msk1 == (PIC_UPPER | PIC_LOWER))
960 goto success;
961
962 /* If one event is limited to a specific counter,
963 * and the other can go on both, OK.
964 */
965 if ((msk0 == PIC_UPPER || msk0 == PIC_LOWER) &&
966 msk1 == (PIC_UPPER | PIC_LOWER)) {
967 if (msk0 & PIC_LOWER)
968 idx0 = 1;
969 goto success;
970 }
971
972 if ((msk1 == PIC_UPPER || msk1 == PIC_LOWER) &&
973 msk0 == (PIC_UPPER | PIC_LOWER)) {
974 if (msk1 & PIC_UPPER)
975 idx0 = 1;
976 goto success;
977 }
978
979 /* If the events are fixed to different counters, OK. */
980 if ((msk0 == PIC_UPPER && msk1 == PIC_LOWER) ||
981 (msk0 == PIC_LOWER && msk1 == PIC_UPPER)) {
982 if (msk0 & PIC_LOWER)
983 idx0 = 1;
984 goto success;
985 }
986
987 /* Otherwise, there is a conflict. */
988 return -1;
989
990success:
991 evts[0]->hw.idx = idx0;
992 if (n_ev == 2)
993 evts[1]->hw.idx = idx0 ^ 1;
994 return 0;
995}
996
997static int check_excludes(struct perf_event **evts, int n_prev, int n_new)
998{
999 int eu = 0, ek = 0, eh = 0;
1000 struct perf_event *event;
1001 int i, n, first;
1002
1003 n = n_prev + n_new;
1004 if (n <= 1)
1005 return 0;
1006
1007 first = 1;
1008 for (i = 0; i < n; i++) {
1009 event = evts[i];
1010 if (first) {
1011 eu = event->attr.exclude_user;
1012 ek = event->attr.exclude_kernel;
1013 eh = event->attr.exclude_hv;
1014 first = 0;
1015 } else if (event->attr.exclude_user != eu ||
1016 event->attr.exclude_kernel != ek ||
1017 event->attr.exclude_hv != eh) {
1018 return -EAGAIN;
1019 }
1020 }
1021
1022 return 0;
1023}
1024
1025static int collect_events(struct perf_event *group, int max_count,
1026 struct perf_event *evts[], unsigned long *events,
1027 int *current_idx)
1028{
1029 struct perf_event *event;
1030 int n = 0;
1031
1032 if (!is_software_event(group)) {
1033 if (n >= max_count)
1034 return -1;
1035 evts[n] = group;
1036 events[n] = group->hw.event_base;
1037 current_idx[n++] = PIC_NO_INDEX;
1038 }
1039 list_for_each_entry(event, &group->sibling_list, group_entry) {
1040 if (!is_software_event(event) &&
1041 event->state != PERF_EVENT_STATE_OFF) {
1042 if (n >= max_count)
1043 return -1;
1044 evts[n] = event;
1045 events[n] = event->hw.event_base;
1046 current_idx[n++] = PIC_NO_INDEX;
1047 }
1048 }
1049 return n;
1050}
1051
1052static int sparc_pmu_add(struct perf_event *event, int ef_flags)
1053{
1054 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1055 int n0, ret = -EAGAIN;
1056 unsigned long flags;
1057
1058 local_irq_save(flags);
1059 perf_pmu_disable(event->pmu);
1060
1061 n0 = cpuc->n_events;
1062 if (n0 >= MAX_HWEVENTS)
1063 goto out;
1064
1065 cpuc->event[n0] = event;
1066 cpuc->events[n0] = event->hw.event_base;
1067 cpuc->current_idx[n0] = PIC_NO_INDEX;
1068
1069 event->hw.state = PERF_HES_UPTODATE;
1070 if (!(ef_flags & PERF_EF_START))
1071 event->hw.state |= PERF_HES_STOPPED;
1072
1073 /*
1074 * If group events scheduling transaction was started,
1075 * skip the schedulability test here, it will be performed
1076 * at commit time(->commit_txn) as a whole
1077 */
1078 if (cpuc->group_flag & PERF_EVENT_TXN)
1079 goto nocheck;
1080
1081 if (check_excludes(cpuc->event, n0, 1))
1082 goto out;
1083 if (sparc_check_constraints(cpuc->event, cpuc->events, n0 + 1))
1084 goto out;
1085
1086nocheck:
1087 cpuc->n_events++;
1088 cpuc->n_added++;
1089
1090 ret = 0;
1091out:
1092 perf_pmu_enable(event->pmu);
1093 local_irq_restore(flags);
1094 return ret;
1095}
1096
1097static int sparc_pmu_event_init(struct perf_event *event)
1098{
1099 struct perf_event_attr *attr = &event->attr;
1100 struct perf_event *evts[MAX_HWEVENTS];
1101 struct hw_perf_event *hwc = &event->hw;
1102 unsigned long events[MAX_HWEVENTS];
1103 int current_idx_dmy[MAX_HWEVENTS];
1104 const struct perf_event_map *pmap;
1105 int n;
1106
1107 if (atomic_read(&nmi_active) < 0)
1108 return -ENODEV;
1109
1110 /* does not support taken branch sampling */
1111 if (has_branch_stack(event))
1112 return -EOPNOTSUPP;
1113
1114 switch (attr->type) {
1115 case PERF_TYPE_HARDWARE:
1116 if (attr->config >= sparc_pmu->max_events)
1117 return -EINVAL;
1118 pmap = sparc_pmu->event_map(attr->config);
1119 break;
1120
1121 case PERF_TYPE_HW_CACHE:
1122 pmap = sparc_map_cache_event(attr->config);
1123 if (IS_ERR(pmap))
1124 return PTR_ERR(pmap);
1125 break;
1126
1127 case PERF_TYPE_RAW:
1128 pmap = NULL;
1129 break;
1130
1131 default:
1132 return -ENOENT;
1133
1134 }
1135
1136 if (pmap) {
1137 hwc->event_base = perf_event_encode(pmap);
1138 } else {
1139 /*
1140 * User gives us "(encoding << 16) | pic_mask" for
1141 * PERF_TYPE_RAW events.
1142 */
1143 hwc->event_base = attr->config;
1144 }
1145
1146 /* We save the enable bits in the config_base. */
1147 hwc->config_base = sparc_pmu->irq_bit;
1148 if (!attr->exclude_user)
1149 hwc->config_base |= PCR_UTRACE;
1150 if (!attr->exclude_kernel)
1151 hwc->config_base |= PCR_STRACE;
1152 if (!attr->exclude_hv)
1153 hwc->config_base |= sparc_pmu->hv_bit;
1154
1155 n = 0;
1156 if (event->group_leader != event) {
1157 n = collect_events(event->group_leader,
1158 MAX_HWEVENTS - 1,
1159 evts, events, current_idx_dmy);
1160 if (n < 0)
1161 return -EINVAL;
1162 }
1163 events[n] = hwc->event_base;
1164 evts[n] = event;
1165
1166 if (check_excludes(evts, n, 1))
1167 return -EINVAL;
1168
1169 if (sparc_check_constraints(evts, events, n + 1))
1170 return -EINVAL;
1171
1172 hwc->idx = PIC_NO_INDEX;
1173
1174 /* Try to do all error checking before this point, as unwinding
1175 * state after grabbing the PMC is difficult.
1176 */
1177 perf_event_grab_pmc();
1178 event->destroy = hw_perf_event_destroy;
1179
1180 if (!hwc->sample_period) {
1181 hwc->sample_period = MAX_PERIOD;
1182 hwc->last_period = hwc->sample_period;
1183 local64_set(&hwc->period_left, hwc->sample_period);
1184 }
1185
1186 return 0;
1187}
1188
1189/*
1190 * Start group events scheduling transaction
1191 * Set the flag to make pmu::enable() not perform the
1192 * schedulability test, it will be performed at commit time
1193 */
1194static void sparc_pmu_start_txn(struct pmu *pmu)
1195{
1196 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
1197
1198 perf_pmu_disable(pmu);
1199 cpuhw->group_flag |= PERF_EVENT_TXN;
1200}
1201
1202/*
1203 * Stop group events scheduling transaction
1204 * Clear the flag and pmu::enable() will perform the
1205 * schedulability test.
1206 */
1207static void sparc_pmu_cancel_txn(struct pmu *pmu)
1208{
1209 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
1210
1211 cpuhw->group_flag &= ~PERF_EVENT_TXN;
1212 perf_pmu_enable(pmu);
1213}
1214
1215/*
1216 * Commit group events scheduling transaction
1217 * Perform the group schedulability test as a whole
1218 * Return 0 if success
1219 */
1220static int sparc_pmu_commit_txn(struct pmu *pmu)
1221{
1222 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1223 int n;
1224
1225 if (!sparc_pmu)
1226 return -EINVAL;
1227
1228 cpuc = &__get_cpu_var(cpu_hw_events);
1229 n = cpuc->n_events;
1230 if (check_excludes(cpuc->event, 0, n))
1231 return -EINVAL;
1232 if (sparc_check_constraints(cpuc->event, cpuc->events, n))
1233 return -EAGAIN;
1234
1235 cpuc->group_flag &= ~PERF_EVENT_TXN;
1236 perf_pmu_enable(pmu);
1237 return 0;
1238}
1239
1240static struct pmu pmu = {
1241 .pmu_enable = sparc_pmu_enable,
1242 .pmu_disable = sparc_pmu_disable,
1243 .event_init = sparc_pmu_event_init,
1244 .add = sparc_pmu_add,
1245 .del = sparc_pmu_del,
1246 .start = sparc_pmu_start,
1247 .stop = sparc_pmu_stop,
1248 .read = sparc_pmu_read,
1249 .start_txn = sparc_pmu_start_txn,
1250 .cancel_txn = sparc_pmu_cancel_txn,
1251 .commit_txn = sparc_pmu_commit_txn,
1252};
1253
1254void perf_event_print_debug(void)
1255{
1256 unsigned long flags;
1257 u64 pcr, pic;
1258 int cpu;
1259
1260 if (!sparc_pmu)
1261 return;
1262
1263 local_irq_save(flags);
1264
1265 cpu = smp_processor_id();
1266
1267 pcr = pcr_ops->read();
1268 read_pic(pic);
1269
1270 pr_info("\n");
1271 pr_info("CPU#%d: PCR[%016llx] PIC[%016llx]\n",
1272 cpu, pcr, pic);
1273
1274 local_irq_restore(flags);
1275}
1276
1277static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
1278 unsigned long cmd, void *__args)
1279{
1280 struct die_args *args = __args;
1281 struct perf_sample_data data;
1282 struct cpu_hw_events *cpuc;
1283 struct pt_regs *regs;
1284 int i;
1285
1286 if (!atomic_read(&active_events))
1287 return NOTIFY_DONE;
1288
1289 switch (cmd) {
1290 case DIE_NMI:
1291 break;
1292
1293 default:
1294 return NOTIFY_DONE;
1295 }
1296
1297 regs = args->regs;
1298
1299 cpuc = &__get_cpu_var(cpu_hw_events);
1300
1301 /* If the PMU has the TOE IRQ enable bits, we need to do a
1302 * dummy write to the %pcr to clear the overflow bits and thus
1303 * the interrupt.
1304 *
1305 * Do this before we peek at the counters to determine
1306 * overflow so we don't lose any events.
1307 */
1308 if (sparc_pmu->irq_bit)
1309 pcr_ops->write(cpuc->pcr);
1310
1311 for (i = 0; i < cpuc->n_events; i++) {
1312 struct perf_event *event = cpuc->event[i];
1313 int idx = cpuc->current_idx[i];
1314 struct hw_perf_event *hwc;
1315 u64 val;
1316
1317 hwc = &event->hw;
1318 val = sparc_perf_event_update(event, hwc, idx);
1319 if (val & (1ULL << 31))
1320 continue;
1321
1322 perf_sample_data_init(&data, 0, hwc->last_period);
1323 if (!sparc_perf_event_set_period(event, hwc, idx))
1324 continue;
1325
1326 if (perf_event_overflow(event, &data, regs))
1327 sparc_pmu_stop(event, 0);
1328 }
1329
1330 return NOTIFY_STOP;
1331}
1332
1333static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1334 .notifier_call = perf_event_nmi_handler,
1335};
1336
1337static bool __init supported_pmu(void)
1338{
1339 if (!strcmp(sparc_pmu_type, "ultra3") ||
1340 !strcmp(sparc_pmu_type, "ultra3+") ||
1341 !strcmp(sparc_pmu_type, "ultra3i") ||
1342 !strcmp(sparc_pmu_type, "ultra4+")) {
1343 sparc_pmu = &ultra3_pmu;
1344 return true;
1345 }
1346 if (!strcmp(sparc_pmu_type, "niagara")) {
1347 sparc_pmu = &niagara1_pmu;
1348 return true;
1349 }
1350 if (!strcmp(sparc_pmu_type, "niagara2") ||
1351 !strcmp(sparc_pmu_type, "niagara3")) {
1352 sparc_pmu = &niagara2_pmu;
1353 return true;
1354 }
1355 return false;
1356}
1357
1358int __init init_hw_perf_events(void)
1359{
1360 pr_info("Performance events: ");
1361
1362 if (!supported_pmu()) {
1363 pr_cont("No support for PMU type '%s'\n", sparc_pmu_type);
1364 return 0;
1365 }
1366
1367 pr_cont("Supported PMU type is '%s'\n", sparc_pmu_type);
1368
1369 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1370 register_die_notifier(&perf_event_nmi_notifier);
1371
1372 return 0;
1373}
1374early_initcall(init_hw_perf_events);
1375
1376void perf_callchain_kernel(struct perf_callchain_entry *entry,
1377 struct pt_regs *regs)
1378{
1379 unsigned long ksp, fp;
1380#ifdef CONFIG_FUNCTION_GRAPH_TRACER
1381 int graph = 0;
1382#endif
1383
1384 stack_trace_flush();
1385
1386 perf_callchain_store(entry, regs->tpc);
1387
1388 ksp = regs->u_regs[UREG_I6];
1389 fp = ksp + STACK_BIAS;
1390 do {
1391 struct sparc_stackf *sf;
1392 struct pt_regs *regs;
1393 unsigned long pc;
1394
1395 if (!kstack_valid(current_thread_info(), fp))
1396 break;
1397
1398 sf = (struct sparc_stackf *) fp;
1399 regs = (struct pt_regs *) (sf + 1);
1400
1401 if (kstack_is_trap_frame(current_thread_info(), regs)) {
1402 if (user_mode(regs))
1403 break;
1404 pc = regs->tpc;
1405 fp = regs->u_regs[UREG_I6] + STACK_BIAS;
1406 } else {
1407 pc = sf->callers_pc;
1408 fp = (unsigned long)sf->fp + STACK_BIAS;
1409 }
1410 perf_callchain_store(entry, pc);
1411#ifdef CONFIG_FUNCTION_GRAPH_TRACER
1412 if ((pc + 8UL) == (unsigned long) &return_to_handler) {
1413 int index = current->curr_ret_stack;
1414 if (current->ret_stack && index >= graph) {
1415 pc = current->ret_stack[index - graph].ret;
1416 perf_callchain_store(entry, pc);
1417 graph++;
1418 }
1419 }
1420#endif
1421 } while (entry->nr < PERF_MAX_STACK_DEPTH);
1422}
1423
1424static void perf_callchain_user_64(struct perf_callchain_entry *entry,
1425 struct pt_regs *regs)
1426{
1427 unsigned long ufp;
1428
1429 perf_callchain_store(entry, regs->tpc);
1430
1431 ufp = regs->u_regs[UREG_I6] + STACK_BIAS;
1432 do {
1433 struct sparc_stackf *usf, sf;
1434 unsigned long pc;
1435
1436 usf = (struct sparc_stackf *) ufp;
1437 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1438 break;
1439
1440 pc = sf.callers_pc;
1441 ufp = (unsigned long)sf.fp + STACK_BIAS;
1442 perf_callchain_store(entry, pc);
1443 } while (entry->nr < PERF_MAX_STACK_DEPTH);
1444}
1445
1446static void perf_callchain_user_32(struct perf_callchain_entry *entry,
1447 struct pt_regs *regs)
1448{
1449 unsigned long ufp;
1450
1451 perf_callchain_store(entry, regs->tpc);
1452
1453 ufp = regs->u_regs[UREG_I6] & 0xffffffffUL;
1454 do {
1455 struct sparc_stackf32 *usf, sf;
1456 unsigned long pc;
1457
1458 usf = (struct sparc_stackf32 *) ufp;
1459 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1460 break;
1461
1462 pc = sf.callers_pc;
1463 ufp = (unsigned long)sf.fp;
1464 perf_callchain_store(entry, pc);
1465 } while (entry->nr < PERF_MAX_STACK_DEPTH);
1466}
1467
1468void
1469perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1470{
1471 flushw_user();
1472 if (test_thread_flag(TIF_32BIT))
1473 perf_callchain_user_32(entry, regs);
1474 else
1475 perf_callchain_user_64(entry, regs);
1476}
1/* Performance event support for sparc64.
2 *
3 * Copyright (C) 2009, 2010 David S. Miller <davem@davemloft.net>
4 *
5 * This code is based almost entirely upon the x86 perf event
6 * code, which is:
7 *
8 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
9 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
10 * Copyright (C) 2009 Jaswinder Singh Rajput
11 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
12 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
13 */
14
15#include <linux/perf_event.h>
16#include <linux/kprobes.h>
17#include <linux/ftrace.h>
18#include <linux/kernel.h>
19#include <linux/kdebug.h>
20#include <linux/mutex.h>
21
22#include <asm/stacktrace.h>
23#include <asm/cpudata.h>
24#include <linux/uaccess.h>
25#include <linux/atomic.h>
26#include <asm/nmi.h>
27#include <asm/pcr.h>
28#include <asm/cacheflush.h>
29
30#include "kernel.h"
31#include "kstack.h"
32
33/* Two classes of sparc64 chips currently exist. All of which have
34 * 32-bit counters which can generate overflow interrupts on the
35 * transition from 0xffffffff to 0.
36 *
37 * All chips upto and including SPARC-T3 have two performance
38 * counters. The two 32-bit counters are accessed in one go using a
39 * single 64-bit register.
40 *
41 * On these older chips both counters are controlled using a single
42 * control register. The only way to stop all sampling is to clear
43 * all of the context (user, supervisor, hypervisor) sampling enable
44 * bits. But these bits apply to both counters, thus the two counters
45 * can't be enabled/disabled individually.
46 *
47 * Furthermore, the control register on these older chips have two
48 * event fields, one for each of the two counters. It's thus nearly
49 * impossible to have one counter going while keeping the other one
50 * stopped. Therefore it is possible to get overflow interrupts for
51 * counters not currently "in use" and that condition must be checked
52 * in the overflow interrupt handler.
53 *
54 * So we use a hack, in that we program inactive counters with the
55 * "sw_count0" and "sw_count1" events. These count how many times
56 * the instruction "sethi %hi(0xfc000), %g0" is executed. It's an
57 * unusual way to encode a NOP and therefore will not trigger in
58 * normal code.
59 *
60 * Starting with SPARC-T4 we have one control register per counter.
61 * And the counters are stored in individual registers. The registers
62 * for the counters are 64-bit but only a 32-bit counter is
63 * implemented. The event selections on SPARC-T4 lack any
64 * restrictions, therefore we can elide all of the complicated
65 * conflict resolution code we have for SPARC-T3 and earlier chips.
66 */
67
68#define MAX_HWEVENTS 4
69#define MAX_PCRS 4
70#define MAX_PERIOD ((1UL << 32) - 1)
71
72#define PIC_UPPER_INDEX 0
73#define PIC_LOWER_INDEX 1
74#define PIC_NO_INDEX -1
75
76struct cpu_hw_events {
77 /* Number of events currently scheduled onto this cpu.
78 * This tells how many entries in the arrays below
79 * are valid.
80 */
81 int n_events;
82
83 /* Number of new events added since the last hw_perf_disable().
84 * This works because the perf event layer always adds new
85 * events inside of a perf_{disable,enable}() sequence.
86 */
87 int n_added;
88
89 /* Array of events current scheduled on this cpu. */
90 struct perf_event *event[MAX_HWEVENTS];
91
92 /* Array of encoded longs, specifying the %pcr register
93 * encoding and the mask of PIC counters this even can
94 * be scheduled on. See perf_event_encode() et al.
95 */
96 unsigned long events[MAX_HWEVENTS];
97
98 /* The current counter index assigned to an event. When the
99 * event hasn't been programmed into the cpu yet, this will
100 * hold PIC_NO_INDEX. The event->hw.idx value tells us where
101 * we ought to schedule the event.
102 */
103 int current_idx[MAX_HWEVENTS];
104
105 /* Software copy of %pcr register(s) on this cpu. */
106 u64 pcr[MAX_HWEVENTS];
107
108 /* Enabled/disable state. */
109 int enabled;
110
111 unsigned int txn_flags;
112};
113static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { .enabled = 1, };
114
115/* An event map describes the characteristics of a performance
116 * counter event. In particular it gives the encoding as well as
117 * a mask telling which counters the event can be measured on.
118 *
119 * The mask is unused on SPARC-T4 and later.
120 */
121struct perf_event_map {
122 u16 encoding;
123 u8 pic_mask;
124#define PIC_NONE 0x00
125#define PIC_UPPER 0x01
126#define PIC_LOWER 0x02
127};
128
129/* Encode a perf_event_map entry into a long. */
130static unsigned long perf_event_encode(const struct perf_event_map *pmap)
131{
132 return ((unsigned long) pmap->encoding << 16) | pmap->pic_mask;
133}
134
135static u8 perf_event_get_msk(unsigned long val)
136{
137 return val & 0xff;
138}
139
140static u64 perf_event_get_enc(unsigned long val)
141{
142 return val >> 16;
143}
144
145#define C(x) PERF_COUNT_HW_CACHE_##x
146
147#define CACHE_OP_UNSUPPORTED 0xfffe
148#define CACHE_OP_NONSENSE 0xffff
149
150typedef struct perf_event_map cache_map_t
151 [PERF_COUNT_HW_CACHE_MAX]
152 [PERF_COUNT_HW_CACHE_OP_MAX]
153 [PERF_COUNT_HW_CACHE_RESULT_MAX];
154
155struct sparc_pmu {
156 const struct perf_event_map *(*event_map)(int);
157 const cache_map_t *cache_map;
158 int max_events;
159 u32 (*read_pmc)(int);
160 void (*write_pmc)(int, u64);
161 int upper_shift;
162 int lower_shift;
163 int event_mask;
164 int user_bit;
165 int priv_bit;
166 int hv_bit;
167 int irq_bit;
168 int upper_nop;
169 int lower_nop;
170 unsigned int flags;
171#define SPARC_PMU_ALL_EXCLUDES_SAME 0x00000001
172#define SPARC_PMU_HAS_CONFLICTS 0x00000002
173 int max_hw_events;
174 int num_pcrs;
175 int num_pic_regs;
176};
177
178static u32 sparc_default_read_pmc(int idx)
179{
180 u64 val;
181
182 val = pcr_ops->read_pic(0);
183 if (idx == PIC_UPPER_INDEX)
184 val >>= 32;
185
186 return val & 0xffffffff;
187}
188
189static void sparc_default_write_pmc(int idx, u64 val)
190{
191 u64 shift, mask, pic;
192
193 shift = 0;
194 if (idx == PIC_UPPER_INDEX)
195 shift = 32;
196
197 mask = ((u64) 0xffffffff) << shift;
198 val <<= shift;
199
200 pic = pcr_ops->read_pic(0);
201 pic &= ~mask;
202 pic |= val;
203 pcr_ops->write_pic(0, pic);
204}
205
206static const struct perf_event_map ultra3_perfmon_event_map[] = {
207 [PERF_COUNT_HW_CPU_CYCLES] = { 0x0000, PIC_UPPER | PIC_LOWER },
208 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x0001, PIC_UPPER | PIC_LOWER },
209 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0009, PIC_LOWER },
210 [PERF_COUNT_HW_CACHE_MISSES] = { 0x0009, PIC_UPPER },
211};
212
213static const struct perf_event_map *ultra3_event_map(int event_id)
214{
215 return &ultra3_perfmon_event_map[event_id];
216}
217
218static const cache_map_t ultra3_cache_map = {
219[C(L1D)] = {
220 [C(OP_READ)] = {
221 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
222 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
223 },
224 [C(OP_WRITE)] = {
225 [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER },
226 [C(RESULT_MISS)] = { 0x0a, PIC_UPPER },
227 },
228 [C(OP_PREFETCH)] = {
229 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
230 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
231 },
232},
233[C(L1I)] = {
234 [C(OP_READ)] = {
235 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
236 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
237 },
238 [ C(OP_WRITE) ] = {
239 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
240 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE },
241 },
242 [ C(OP_PREFETCH) ] = {
243 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
244 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
245 },
246},
247[C(LL)] = {
248 [C(OP_READ)] = {
249 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER, },
250 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER, },
251 },
252 [C(OP_WRITE)] = {
253 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER },
254 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER },
255 },
256 [C(OP_PREFETCH)] = {
257 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
258 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
259 },
260},
261[C(DTLB)] = {
262 [C(OP_READ)] = {
263 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
264 [C(RESULT_MISS)] = { 0x12, PIC_UPPER, },
265 },
266 [ C(OP_WRITE) ] = {
267 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
268 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
269 },
270 [ C(OP_PREFETCH) ] = {
271 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
272 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
273 },
274},
275[C(ITLB)] = {
276 [C(OP_READ)] = {
277 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
278 [C(RESULT_MISS)] = { 0x11, PIC_UPPER, },
279 },
280 [ C(OP_WRITE) ] = {
281 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
282 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
283 },
284 [ C(OP_PREFETCH) ] = {
285 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
286 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
287 },
288},
289[C(BPU)] = {
290 [C(OP_READ)] = {
291 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
292 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
293 },
294 [ C(OP_WRITE) ] = {
295 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
296 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
297 },
298 [ C(OP_PREFETCH) ] = {
299 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
300 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
301 },
302},
303[C(NODE)] = {
304 [C(OP_READ)] = {
305 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
306 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
307 },
308 [ C(OP_WRITE) ] = {
309 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
310 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
311 },
312 [ C(OP_PREFETCH) ] = {
313 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
314 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
315 },
316},
317};
318
319static const struct sparc_pmu ultra3_pmu = {
320 .event_map = ultra3_event_map,
321 .cache_map = &ultra3_cache_map,
322 .max_events = ARRAY_SIZE(ultra3_perfmon_event_map),
323 .read_pmc = sparc_default_read_pmc,
324 .write_pmc = sparc_default_write_pmc,
325 .upper_shift = 11,
326 .lower_shift = 4,
327 .event_mask = 0x3f,
328 .user_bit = PCR_UTRACE,
329 .priv_bit = PCR_STRACE,
330 .upper_nop = 0x1c,
331 .lower_nop = 0x14,
332 .flags = (SPARC_PMU_ALL_EXCLUDES_SAME |
333 SPARC_PMU_HAS_CONFLICTS),
334 .max_hw_events = 2,
335 .num_pcrs = 1,
336 .num_pic_regs = 1,
337};
338
339/* Niagara1 is very limited. The upper PIC is hard-locked to count
340 * only instructions, so it is free running which creates all kinds of
341 * problems. Some hardware designs make one wonder if the creator
342 * even looked at how this stuff gets used by software.
343 */
344static const struct perf_event_map niagara1_perfmon_event_map[] = {
345 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, PIC_UPPER },
346 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, PIC_UPPER },
347 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0, PIC_NONE },
348 [PERF_COUNT_HW_CACHE_MISSES] = { 0x03, PIC_LOWER },
349};
350
351static const struct perf_event_map *niagara1_event_map(int event_id)
352{
353 return &niagara1_perfmon_event_map[event_id];
354}
355
356static const cache_map_t niagara1_cache_map = {
357[C(L1D)] = {
358 [C(OP_READ)] = {
359 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
360 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
361 },
362 [C(OP_WRITE)] = {
363 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
364 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
365 },
366 [C(OP_PREFETCH)] = {
367 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
368 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
369 },
370},
371[C(L1I)] = {
372 [C(OP_READ)] = {
373 [C(RESULT_ACCESS)] = { 0x00, PIC_UPPER },
374 [C(RESULT_MISS)] = { 0x02, PIC_LOWER, },
375 },
376 [ C(OP_WRITE) ] = {
377 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
378 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE },
379 },
380 [ C(OP_PREFETCH) ] = {
381 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
382 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
383 },
384},
385[C(LL)] = {
386 [C(OP_READ)] = {
387 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
388 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
389 },
390 [C(OP_WRITE)] = {
391 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
392 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
393 },
394 [C(OP_PREFETCH)] = {
395 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
396 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
397 },
398},
399[C(DTLB)] = {
400 [C(OP_READ)] = {
401 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
402 [C(RESULT_MISS)] = { 0x05, PIC_LOWER, },
403 },
404 [ C(OP_WRITE) ] = {
405 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
406 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
407 },
408 [ C(OP_PREFETCH) ] = {
409 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
410 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
411 },
412},
413[C(ITLB)] = {
414 [C(OP_READ)] = {
415 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
416 [C(RESULT_MISS)] = { 0x04, PIC_LOWER, },
417 },
418 [ C(OP_WRITE) ] = {
419 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
420 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
421 },
422 [ C(OP_PREFETCH) ] = {
423 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
424 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
425 },
426},
427[C(BPU)] = {
428 [C(OP_READ)] = {
429 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
430 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
431 },
432 [ C(OP_WRITE) ] = {
433 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
434 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
435 },
436 [ C(OP_PREFETCH) ] = {
437 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
438 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
439 },
440},
441[C(NODE)] = {
442 [C(OP_READ)] = {
443 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
444 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
445 },
446 [ C(OP_WRITE) ] = {
447 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
448 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
449 },
450 [ C(OP_PREFETCH) ] = {
451 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
452 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
453 },
454},
455};
456
457static const struct sparc_pmu niagara1_pmu = {
458 .event_map = niagara1_event_map,
459 .cache_map = &niagara1_cache_map,
460 .max_events = ARRAY_SIZE(niagara1_perfmon_event_map),
461 .read_pmc = sparc_default_read_pmc,
462 .write_pmc = sparc_default_write_pmc,
463 .upper_shift = 0,
464 .lower_shift = 4,
465 .event_mask = 0x7,
466 .user_bit = PCR_UTRACE,
467 .priv_bit = PCR_STRACE,
468 .upper_nop = 0x0,
469 .lower_nop = 0x0,
470 .flags = (SPARC_PMU_ALL_EXCLUDES_SAME |
471 SPARC_PMU_HAS_CONFLICTS),
472 .max_hw_events = 2,
473 .num_pcrs = 1,
474 .num_pic_regs = 1,
475};
476
477static const struct perf_event_map niagara2_perfmon_event_map[] = {
478 [PERF_COUNT_HW_CPU_CYCLES] = { 0x02ff, PIC_UPPER | PIC_LOWER },
479 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x02ff, PIC_UPPER | PIC_LOWER },
480 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0208, PIC_UPPER | PIC_LOWER },
481 [PERF_COUNT_HW_CACHE_MISSES] = { 0x0302, PIC_UPPER | PIC_LOWER },
482 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x0201, PIC_UPPER | PIC_LOWER },
483 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x0202, PIC_UPPER | PIC_LOWER },
484};
485
486static const struct perf_event_map *niagara2_event_map(int event_id)
487{
488 return &niagara2_perfmon_event_map[event_id];
489}
490
491static const cache_map_t niagara2_cache_map = {
492[C(L1D)] = {
493 [C(OP_READ)] = {
494 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
495 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
496 },
497 [C(OP_WRITE)] = {
498 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
499 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
500 },
501 [C(OP_PREFETCH)] = {
502 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
503 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
504 },
505},
506[C(L1I)] = {
507 [C(OP_READ)] = {
508 [C(RESULT_ACCESS)] = { 0x02ff, PIC_UPPER | PIC_LOWER, },
509 [C(RESULT_MISS)] = { 0x0301, PIC_UPPER | PIC_LOWER, },
510 },
511 [ C(OP_WRITE) ] = {
512 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
513 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE },
514 },
515 [ C(OP_PREFETCH) ] = {
516 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
517 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
518 },
519},
520[C(LL)] = {
521 [C(OP_READ)] = {
522 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
523 [C(RESULT_MISS)] = { 0x0330, PIC_UPPER | PIC_LOWER, },
524 },
525 [C(OP_WRITE)] = {
526 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
527 [C(RESULT_MISS)] = { 0x0320, PIC_UPPER | PIC_LOWER, },
528 },
529 [C(OP_PREFETCH)] = {
530 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
531 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
532 },
533},
534[C(DTLB)] = {
535 [C(OP_READ)] = {
536 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
537 [C(RESULT_MISS)] = { 0x0b08, PIC_UPPER | PIC_LOWER, },
538 },
539 [ C(OP_WRITE) ] = {
540 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
541 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
542 },
543 [ C(OP_PREFETCH) ] = {
544 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
545 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
546 },
547},
548[C(ITLB)] = {
549 [C(OP_READ)] = {
550 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
551 [C(RESULT_MISS)] = { 0xb04, PIC_UPPER | PIC_LOWER, },
552 },
553 [ C(OP_WRITE) ] = {
554 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
555 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
556 },
557 [ C(OP_PREFETCH) ] = {
558 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
559 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
560 },
561},
562[C(BPU)] = {
563 [C(OP_READ)] = {
564 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
565 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
566 },
567 [ C(OP_WRITE) ] = {
568 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
569 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
570 },
571 [ C(OP_PREFETCH) ] = {
572 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
573 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
574 },
575},
576[C(NODE)] = {
577 [C(OP_READ)] = {
578 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
579 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
580 },
581 [ C(OP_WRITE) ] = {
582 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
583 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
584 },
585 [ C(OP_PREFETCH) ] = {
586 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
587 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
588 },
589},
590};
591
592static const struct sparc_pmu niagara2_pmu = {
593 .event_map = niagara2_event_map,
594 .cache_map = &niagara2_cache_map,
595 .max_events = ARRAY_SIZE(niagara2_perfmon_event_map),
596 .read_pmc = sparc_default_read_pmc,
597 .write_pmc = sparc_default_write_pmc,
598 .upper_shift = 19,
599 .lower_shift = 6,
600 .event_mask = 0xfff,
601 .user_bit = PCR_UTRACE,
602 .priv_bit = PCR_STRACE,
603 .hv_bit = PCR_N2_HTRACE,
604 .irq_bit = 0x30,
605 .upper_nop = 0x220,
606 .lower_nop = 0x220,
607 .flags = (SPARC_PMU_ALL_EXCLUDES_SAME |
608 SPARC_PMU_HAS_CONFLICTS),
609 .max_hw_events = 2,
610 .num_pcrs = 1,
611 .num_pic_regs = 1,
612};
613
614static const struct perf_event_map niagara4_perfmon_event_map[] = {
615 [PERF_COUNT_HW_CPU_CYCLES] = { (26 << 6) },
616 [PERF_COUNT_HW_INSTRUCTIONS] = { (3 << 6) | 0x3f },
617 [PERF_COUNT_HW_CACHE_REFERENCES] = { (3 << 6) | 0x04 },
618 [PERF_COUNT_HW_CACHE_MISSES] = { (16 << 6) | 0x07 },
619 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { (4 << 6) | 0x01 },
620 [PERF_COUNT_HW_BRANCH_MISSES] = { (25 << 6) | 0x0f },
621};
622
623static const struct perf_event_map *niagara4_event_map(int event_id)
624{
625 return &niagara4_perfmon_event_map[event_id];
626}
627
628static const cache_map_t niagara4_cache_map = {
629[C(L1D)] = {
630 [C(OP_READ)] = {
631 [C(RESULT_ACCESS)] = { (3 << 6) | 0x04 },
632 [C(RESULT_MISS)] = { (16 << 6) | 0x07 },
633 },
634 [C(OP_WRITE)] = {
635 [C(RESULT_ACCESS)] = { (3 << 6) | 0x08 },
636 [C(RESULT_MISS)] = { (16 << 6) | 0x07 },
637 },
638 [C(OP_PREFETCH)] = {
639 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
640 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
641 },
642},
643[C(L1I)] = {
644 [C(OP_READ)] = {
645 [C(RESULT_ACCESS)] = { (3 << 6) | 0x3f },
646 [C(RESULT_MISS)] = { (11 << 6) | 0x03 },
647 },
648 [ C(OP_WRITE) ] = {
649 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
650 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE },
651 },
652 [ C(OP_PREFETCH) ] = {
653 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
654 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
655 },
656},
657[C(LL)] = {
658 [C(OP_READ)] = {
659 [C(RESULT_ACCESS)] = { (3 << 6) | 0x04 },
660 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
661 },
662 [C(OP_WRITE)] = {
663 [C(RESULT_ACCESS)] = { (3 << 6) | 0x08 },
664 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
665 },
666 [C(OP_PREFETCH)] = {
667 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
668 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
669 },
670},
671[C(DTLB)] = {
672 [C(OP_READ)] = {
673 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
674 [C(RESULT_MISS)] = { (17 << 6) | 0x3f },
675 },
676 [ C(OP_WRITE) ] = {
677 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
678 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
679 },
680 [ C(OP_PREFETCH) ] = {
681 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
682 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
683 },
684},
685[C(ITLB)] = {
686 [C(OP_READ)] = {
687 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
688 [C(RESULT_MISS)] = { (6 << 6) | 0x3f },
689 },
690 [ C(OP_WRITE) ] = {
691 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
692 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
693 },
694 [ C(OP_PREFETCH) ] = {
695 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
696 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
697 },
698},
699[C(BPU)] = {
700 [C(OP_READ)] = {
701 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
702 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
703 },
704 [ C(OP_WRITE) ] = {
705 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
706 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
707 },
708 [ C(OP_PREFETCH) ] = {
709 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
710 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
711 },
712},
713[C(NODE)] = {
714 [C(OP_READ)] = {
715 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
716 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
717 },
718 [ C(OP_WRITE) ] = {
719 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
720 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
721 },
722 [ C(OP_PREFETCH) ] = {
723 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
724 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
725 },
726},
727};
728
729static u32 sparc_vt_read_pmc(int idx)
730{
731 u64 val = pcr_ops->read_pic(idx);
732
733 return val & 0xffffffff;
734}
735
736static void sparc_vt_write_pmc(int idx, u64 val)
737{
738 u64 pcr;
739
740 pcr = pcr_ops->read_pcr(idx);
741 /* ensure ov and ntc are reset */
742 pcr &= ~(PCR_N4_OV | PCR_N4_NTC);
743
744 pcr_ops->write_pic(idx, val & 0xffffffff);
745
746 pcr_ops->write_pcr(idx, pcr);
747}
748
749static const struct sparc_pmu niagara4_pmu = {
750 .event_map = niagara4_event_map,
751 .cache_map = &niagara4_cache_map,
752 .max_events = ARRAY_SIZE(niagara4_perfmon_event_map),
753 .read_pmc = sparc_vt_read_pmc,
754 .write_pmc = sparc_vt_write_pmc,
755 .upper_shift = 5,
756 .lower_shift = 5,
757 .event_mask = 0x7ff,
758 .user_bit = PCR_N4_UTRACE,
759 .priv_bit = PCR_N4_STRACE,
760
761 /* We explicitly don't support hypervisor tracing. The T4
762 * generates the overflow event for precise events via a trap
763 * which will not be generated (ie. it's completely lost) if
764 * we happen to be in the hypervisor when the event triggers.
765 * Essentially, the overflow event reporting is completely
766 * unusable when you have hypervisor mode tracing enabled.
767 */
768 .hv_bit = 0,
769
770 .irq_bit = PCR_N4_TOE,
771 .upper_nop = 0,
772 .lower_nop = 0,
773 .flags = 0,
774 .max_hw_events = 4,
775 .num_pcrs = 4,
776 .num_pic_regs = 4,
777};
778
779static const struct sparc_pmu sparc_m7_pmu = {
780 .event_map = niagara4_event_map,
781 .cache_map = &niagara4_cache_map,
782 .max_events = ARRAY_SIZE(niagara4_perfmon_event_map),
783 .read_pmc = sparc_vt_read_pmc,
784 .write_pmc = sparc_vt_write_pmc,
785 .upper_shift = 5,
786 .lower_shift = 5,
787 .event_mask = 0x7ff,
788 .user_bit = PCR_N4_UTRACE,
789 .priv_bit = PCR_N4_STRACE,
790
791 /* We explicitly don't support hypervisor tracing. */
792 .hv_bit = 0,
793
794 .irq_bit = PCR_N4_TOE,
795 .upper_nop = 0,
796 .lower_nop = 0,
797 .flags = 0,
798 .max_hw_events = 4,
799 .num_pcrs = 4,
800 .num_pic_regs = 4,
801};
802static const struct sparc_pmu *sparc_pmu __read_mostly;
803
804static u64 event_encoding(u64 event_id, int idx)
805{
806 if (idx == PIC_UPPER_INDEX)
807 event_id <<= sparc_pmu->upper_shift;
808 else
809 event_id <<= sparc_pmu->lower_shift;
810 return event_id;
811}
812
813static u64 mask_for_index(int idx)
814{
815 return event_encoding(sparc_pmu->event_mask, idx);
816}
817
818static u64 nop_for_index(int idx)
819{
820 return event_encoding(idx == PIC_UPPER_INDEX ?
821 sparc_pmu->upper_nop :
822 sparc_pmu->lower_nop, idx);
823}
824
825static inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
826{
827 u64 enc, val, mask = mask_for_index(idx);
828 int pcr_index = 0;
829
830 if (sparc_pmu->num_pcrs > 1)
831 pcr_index = idx;
832
833 enc = perf_event_get_enc(cpuc->events[idx]);
834
835 val = cpuc->pcr[pcr_index];
836 val &= ~mask;
837 val |= event_encoding(enc, idx);
838 cpuc->pcr[pcr_index] = val;
839
840 pcr_ops->write_pcr(pcr_index, cpuc->pcr[pcr_index]);
841}
842
843static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
844{
845 u64 mask = mask_for_index(idx);
846 u64 nop = nop_for_index(idx);
847 int pcr_index = 0;
848 u64 val;
849
850 if (sparc_pmu->num_pcrs > 1)
851 pcr_index = idx;
852
853 val = cpuc->pcr[pcr_index];
854 val &= ~mask;
855 val |= nop;
856 cpuc->pcr[pcr_index] = val;
857
858 pcr_ops->write_pcr(pcr_index, cpuc->pcr[pcr_index]);
859}
860
861static u64 sparc_perf_event_update(struct perf_event *event,
862 struct hw_perf_event *hwc, int idx)
863{
864 int shift = 64 - 32;
865 u64 prev_raw_count, new_raw_count;
866 s64 delta;
867
868again:
869 prev_raw_count = local64_read(&hwc->prev_count);
870 new_raw_count = sparc_pmu->read_pmc(idx);
871
872 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
873 new_raw_count) != prev_raw_count)
874 goto again;
875
876 delta = (new_raw_count << shift) - (prev_raw_count << shift);
877 delta >>= shift;
878
879 local64_add(delta, &event->count);
880 local64_sub(delta, &hwc->period_left);
881
882 return new_raw_count;
883}
884
885static int sparc_perf_event_set_period(struct perf_event *event,
886 struct hw_perf_event *hwc, int idx)
887{
888 s64 left = local64_read(&hwc->period_left);
889 s64 period = hwc->sample_period;
890 int ret = 0;
891
892 if (unlikely(left <= -period)) {
893 left = period;
894 local64_set(&hwc->period_left, left);
895 hwc->last_period = period;
896 ret = 1;
897 }
898
899 if (unlikely(left <= 0)) {
900 left += period;
901 local64_set(&hwc->period_left, left);
902 hwc->last_period = period;
903 ret = 1;
904 }
905 if (left > MAX_PERIOD)
906 left = MAX_PERIOD;
907
908 local64_set(&hwc->prev_count, (u64)-left);
909
910 sparc_pmu->write_pmc(idx, (u64)(-left) & 0xffffffff);
911
912 perf_event_update_userpage(event);
913
914 return ret;
915}
916
917static void read_in_all_counters(struct cpu_hw_events *cpuc)
918{
919 int i;
920
921 for (i = 0; i < cpuc->n_events; i++) {
922 struct perf_event *cp = cpuc->event[i];
923
924 if (cpuc->current_idx[i] != PIC_NO_INDEX &&
925 cpuc->current_idx[i] != cp->hw.idx) {
926 sparc_perf_event_update(cp, &cp->hw,
927 cpuc->current_idx[i]);
928 cpuc->current_idx[i] = PIC_NO_INDEX;
929 }
930 }
931}
932
933/* On this PMU all PICs are programmed using a single PCR. Calculate
934 * the combined control register value.
935 *
936 * For such chips we require that all of the events have the same
937 * configuration, so just fetch the settings from the first entry.
938 */
939static void calculate_single_pcr(struct cpu_hw_events *cpuc)
940{
941 int i;
942
943 if (!cpuc->n_added)
944 goto out;
945
946 /* Assign to counters all unassigned events. */
947 for (i = 0; i < cpuc->n_events; i++) {
948 struct perf_event *cp = cpuc->event[i];
949 struct hw_perf_event *hwc = &cp->hw;
950 int idx = hwc->idx;
951 u64 enc;
952
953 if (cpuc->current_idx[i] != PIC_NO_INDEX)
954 continue;
955
956 sparc_perf_event_set_period(cp, hwc, idx);
957 cpuc->current_idx[i] = idx;
958
959 enc = perf_event_get_enc(cpuc->events[i]);
960 cpuc->pcr[0] &= ~mask_for_index(idx);
961 if (hwc->state & PERF_HES_STOPPED)
962 cpuc->pcr[0] |= nop_for_index(idx);
963 else
964 cpuc->pcr[0] |= event_encoding(enc, idx);
965 }
966out:
967 cpuc->pcr[0] |= cpuc->event[0]->hw.config_base;
968}
969
970static void sparc_pmu_start(struct perf_event *event, int flags);
971
972/* On this PMU each PIC has it's own PCR control register. */
973static void calculate_multiple_pcrs(struct cpu_hw_events *cpuc)
974{
975 int i;
976
977 if (!cpuc->n_added)
978 goto out;
979
980 for (i = 0; i < cpuc->n_events; i++) {
981 struct perf_event *cp = cpuc->event[i];
982 struct hw_perf_event *hwc = &cp->hw;
983 int idx = hwc->idx;
984
985 if (cpuc->current_idx[i] != PIC_NO_INDEX)
986 continue;
987
988 cpuc->current_idx[i] = idx;
989
990 sparc_pmu_start(cp, PERF_EF_RELOAD);
991 }
992out:
993 for (i = 0; i < cpuc->n_events; i++) {
994 struct perf_event *cp = cpuc->event[i];
995 int idx = cp->hw.idx;
996
997 cpuc->pcr[idx] |= cp->hw.config_base;
998 }
999}
1000
1001/* If performance event entries have been added, move existing events
1002 * around (if necessary) and then assign new entries to counters.
1003 */
1004static void update_pcrs_for_enable(struct cpu_hw_events *cpuc)
1005{
1006 if (cpuc->n_added)
1007 read_in_all_counters(cpuc);
1008
1009 if (sparc_pmu->num_pcrs == 1) {
1010 calculate_single_pcr(cpuc);
1011 } else {
1012 calculate_multiple_pcrs(cpuc);
1013 }
1014}
1015
1016static void sparc_pmu_enable(struct pmu *pmu)
1017{
1018 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1019 int i;
1020
1021 if (cpuc->enabled)
1022 return;
1023
1024 cpuc->enabled = 1;
1025 barrier();
1026
1027 if (cpuc->n_events)
1028 update_pcrs_for_enable(cpuc);
1029
1030 for (i = 0; i < sparc_pmu->num_pcrs; i++)
1031 pcr_ops->write_pcr(i, cpuc->pcr[i]);
1032}
1033
1034static void sparc_pmu_disable(struct pmu *pmu)
1035{
1036 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1037 int i;
1038
1039 if (!cpuc->enabled)
1040 return;
1041
1042 cpuc->enabled = 0;
1043 cpuc->n_added = 0;
1044
1045 for (i = 0; i < sparc_pmu->num_pcrs; i++) {
1046 u64 val = cpuc->pcr[i];
1047
1048 val &= ~(sparc_pmu->user_bit | sparc_pmu->priv_bit |
1049 sparc_pmu->hv_bit | sparc_pmu->irq_bit);
1050 cpuc->pcr[i] = val;
1051 pcr_ops->write_pcr(i, cpuc->pcr[i]);
1052 }
1053}
1054
1055static int active_event_index(struct cpu_hw_events *cpuc,
1056 struct perf_event *event)
1057{
1058 int i;
1059
1060 for (i = 0; i < cpuc->n_events; i++) {
1061 if (cpuc->event[i] == event)
1062 break;
1063 }
1064 BUG_ON(i == cpuc->n_events);
1065 return cpuc->current_idx[i];
1066}
1067
1068static void sparc_pmu_start(struct perf_event *event, int flags)
1069{
1070 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1071 int idx = active_event_index(cpuc, event);
1072
1073 if (flags & PERF_EF_RELOAD) {
1074 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1075 sparc_perf_event_set_period(event, &event->hw, idx);
1076 }
1077
1078 event->hw.state = 0;
1079
1080 sparc_pmu_enable_event(cpuc, &event->hw, idx);
1081}
1082
1083static void sparc_pmu_stop(struct perf_event *event, int flags)
1084{
1085 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1086 int idx = active_event_index(cpuc, event);
1087
1088 if (!(event->hw.state & PERF_HES_STOPPED)) {
1089 sparc_pmu_disable_event(cpuc, &event->hw, idx);
1090 event->hw.state |= PERF_HES_STOPPED;
1091 }
1092
1093 if (!(event->hw.state & PERF_HES_UPTODATE) && (flags & PERF_EF_UPDATE)) {
1094 sparc_perf_event_update(event, &event->hw, idx);
1095 event->hw.state |= PERF_HES_UPTODATE;
1096 }
1097}
1098
1099static void sparc_pmu_del(struct perf_event *event, int _flags)
1100{
1101 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1102 unsigned long flags;
1103 int i;
1104
1105 local_irq_save(flags);
1106
1107 for (i = 0; i < cpuc->n_events; i++) {
1108 if (event == cpuc->event[i]) {
1109 /* Absorb the final count and turn off the
1110 * event.
1111 */
1112 sparc_pmu_stop(event, PERF_EF_UPDATE);
1113
1114 /* Shift remaining entries down into
1115 * the existing slot.
1116 */
1117 while (++i < cpuc->n_events) {
1118 cpuc->event[i - 1] = cpuc->event[i];
1119 cpuc->events[i - 1] = cpuc->events[i];
1120 cpuc->current_idx[i - 1] =
1121 cpuc->current_idx[i];
1122 }
1123
1124 perf_event_update_userpage(event);
1125
1126 cpuc->n_events--;
1127 break;
1128 }
1129 }
1130
1131 local_irq_restore(flags);
1132}
1133
1134static void sparc_pmu_read(struct perf_event *event)
1135{
1136 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1137 int idx = active_event_index(cpuc, event);
1138 struct hw_perf_event *hwc = &event->hw;
1139
1140 sparc_perf_event_update(event, hwc, idx);
1141}
1142
1143static atomic_t active_events = ATOMIC_INIT(0);
1144static DEFINE_MUTEX(pmc_grab_mutex);
1145
1146static void perf_stop_nmi_watchdog(void *unused)
1147{
1148 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1149 int i;
1150
1151 stop_nmi_watchdog(NULL);
1152 for (i = 0; i < sparc_pmu->num_pcrs; i++)
1153 cpuc->pcr[i] = pcr_ops->read_pcr(i);
1154}
1155
1156static void perf_event_grab_pmc(void)
1157{
1158 if (atomic_inc_not_zero(&active_events))
1159 return;
1160
1161 mutex_lock(&pmc_grab_mutex);
1162 if (atomic_read(&active_events) == 0) {
1163 if (atomic_read(&nmi_active) > 0) {
1164 on_each_cpu(perf_stop_nmi_watchdog, NULL, 1);
1165 BUG_ON(atomic_read(&nmi_active) != 0);
1166 }
1167 atomic_inc(&active_events);
1168 }
1169 mutex_unlock(&pmc_grab_mutex);
1170}
1171
1172static void perf_event_release_pmc(void)
1173{
1174 if (atomic_dec_and_mutex_lock(&active_events, &pmc_grab_mutex)) {
1175 if (atomic_read(&nmi_active) == 0)
1176 on_each_cpu(start_nmi_watchdog, NULL, 1);
1177 mutex_unlock(&pmc_grab_mutex);
1178 }
1179}
1180
1181static const struct perf_event_map *sparc_map_cache_event(u64 config)
1182{
1183 unsigned int cache_type, cache_op, cache_result;
1184 const struct perf_event_map *pmap;
1185
1186 if (!sparc_pmu->cache_map)
1187 return ERR_PTR(-ENOENT);
1188
1189 cache_type = (config >> 0) & 0xff;
1190 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
1191 return ERR_PTR(-EINVAL);
1192
1193 cache_op = (config >> 8) & 0xff;
1194 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
1195 return ERR_PTR(-EINVAL);
1196
1197 cache_result = (config >> 16) & 0xff;
1198 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
1199 return ERR_PTR(-EINVAL);
1200
1201 pmap = &((*sparc_pmu->cache_map)[cache_type][cache_op][cache_result]);
1202
1203 if (pmap->encoding == CACHE_OP_UNSUPPORTED)
1204 return ERR_PTR(-ENOENT);
1205
1206 if (pmap->encoding == CACHE_OP_NONSENSE)
1207 return ERR_PTR(-EINVAL);
1208
1209 return pmap;
1210}
1211
1212static void hw_perf_event_destroy(struct perf_event *event)
1213{
1214 perf_event_release_pmc();
1215}
1216
1217/* Make sure all events can be scheduled into the hardware at
1218 * the same time. This is simplified by the fact that we only
1219 * need to support 2 simultaneous HW events.
1220 *
1221 * As a side effect, the evts[]->hw.idx values will be assigned
1222 * on success. These are pending indexes. When the events are
1223 * actually programmed into the chip, these values will propagate
1224 * to the per-cpu cpuc->current_idx[] slots, see the code in
1225 * maybe_change_configuration() for details.
1226 */
1227static int sparc_check_constraints(struct perf_event **evts,
1228 unsigned long *events, int n_ev)
1229{
1230 u8 msk0 = 0, msk1 = 0;
1231 int idx0 = 0;
1232
1233 /* This case is possible when we are invoked from
1234 * hw_perf_group_sched_in().
1235 */
1236 if (!n_ev)
1237 return 0;
1238
1239 if (n_ev > sparc_pmu->max_hw_events)
1240 return -1;
1241
1242 if (!(sparc_pmu->flags & SPARC_PMU_HAS_CONFLICTS)) {
1243 int i;
1244
1245 for (i = 0; i < n_ev; i++)
1246 evts[i]->hw.idx = i;
1247 return 0;
1248 }
1249
1250 msk0 = perf_event_get_msk(events[0]);
1251 if (n_ev == 1) {
1252 if (msk0 & PIC_LOWER)
1253 idx0 = 1;
1254 goto success;
1255 }
1256 BUG_ON(n_ev != 2);
1257 msk1 = perf_event_get_msk(events[1]);
1258
1259 /* If both events can go on any counter, OK. */
1260 if (msk0 == (PIC_UPPER | PIC_LOWER) &&
1261 msk1 == (PIC_UPPER | PIC_LOWER))
1262 goto success;
1263
1264 /* If one event is limited to a specific counter,
1265 * and the other can go on both, OK.
1266 */
1267 if ((msk0 == PIC_UPPER || msk0 == PIC_LOWER) &&
1268 msk1 == (PIC_UPPER | PIC_LOWER)) {
1269 if (msk0 & PIC_LOWER)
1270 idx0 = 1;
1271 goto success;
1272 }
1273
1274 if ((msk1 == PIC_UPPER || msk1 == PIC_LOWER) &&
1275 msk0 == (PIC_UPPER | PIC_LOWER)) {
1276 if (msk1 & PIC_UPPER)
1277 idx0 = 1;
1278 goto success;
1279 }
1280
1281 /* If the events are fixed to different counters, OK. */
1282 if ((msk0 == PIC_UPPER && msk1 == PIC_LOWER) ||
1283 (msk0 == PIC_LOWER && msk1 == PIC_UPPER)) {
1284 if (msk0 & PIC_LOWER)
1285 idx0 = 1;
1286 goto success;
1287 }
1288
1289 /* Otherwise, there is a conflict. */
1290 return -1;
1291
1292success:
1293 evts[0]->hw.idx = idx0;
1294 if (n_ev == 2)
1295 evts[1]->hw.idx = idx0 ^ 1;
1296 return 0;
1297}
1298
1299static int check_excludes(struct perf_event **evts, int n_prev, int n_new)
1300{
1301 int eu = 0, ek = 0, eh = 0;
1302 struct perf_event *event;
1303 int i, n, first;
1304
1305 if (!(sparc_pmu->flags & SPARC_PMU_ALL_EXCLUDES_SAME))
1306 return 0;
1307
1308 n = n_prev + n_new;
1309 if (n <= 1)
1310 return 0;
1311
1312 first = 1;
1313 for (i = 0; i < n; i++) {
1314 event = evts[i];
1315 if (first) {
1316 eu = event->attr.exclude_user;
1317 ek = event->attr.exclude_kernel;
1318 eh = event->attr.exclude_hv;
1319 first = 0;
1320 } else if (event->attr.exclude_user != eu ||
1321 event->attr.exclude_kernel != ek ||
1322 event->attr.exclude_hv != eh) {
1323 return -EAGAIN;
1324 }
1325 }
1326
1327 return 0;
1328}
1329
1330static int collect_events(struct perf_event *group, int max_count,
1331 struct perf_event *evts[], unsigned long *events,
1332 int *current_idx)
1333{
1334 struct perf_event *event;
1335 int n = 0;
1336
1337 if (!is_software_event(group)) {
1338 if (n >= max_count)
1339 return -1;
1340 evts[n] = group;
1341 events[n] = group->hw.event_base;
1342 current_idx[n++] = PIC_NO_INDEX;
1343 }
1344 list_for_each_entry(event, &group->sibling_list, group_entry) {
1345 if (!is_software_event(event) &&
1346 event->state != PERF_EVENT_STATE_OFF) {
1347 if (n >= max_count)
1348 return -1;
1349 evts[n] = event;
1350 events[n] = event->hw.event_base;
1351 current_idx[n++] = PIC_NO_INDEX;
1352 }
1353 }
1354 return n;
1355}
1356
1357static int sparc_pmu_add(struct perf_event *event, int ef_flags)
1358{
1359 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1360 int n0, ret = -EAGAIN;
1361 unsigned long flags;
1362
1363 local_irq_save(flags);
1364
1365 n0 = cpuc->n_events;
1366 if (n0 >= sparc_pmu->max_hw_events)
1367 goto out;
1368
1369 cpuc->event[n0] = event;
1370 cpuc->events[n0] = event->hw.event_base;
1371 cpuc->current_idx[n0] = PIC_NO_INDEX;
1372
1373 event->hw.state = PERF_HES_UPTODATE;
1374 if (!(ef_flags & PERF_EF_START))
1375 event->hw.state |= PERF_HES_STOPPED;
1376
1377 /*
1378 * If group events scheduling transaction was started,
1379 * skip the schedulability test here, it will be performed
1380 * at commit time(->commit_txn) as a whole
1381 */
1382 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1383 goto nocheck;
1384
1385 if (check_excludes(cpuc->event, n0, 1))
1386 goto out;
1387 if (sparc_check_constraints(cpuc->event, cpuc->events, n0 + 1))
1388 goto out;
1389
1390nocheck:
1391 cpuc->n_events++;
1392 cpuc->n_added++;
1393
1394 ret = 0;
1395out:
1396 local_irq_restore(flags);
1397 return ret;
1398}
1399
1400static int sparc_pmu_event_init(struct perf_event *event)
1401{
1402 struct perf_event_attr *attr = &event->attr;
1403 struct perf_event *evts[MAX_HWEVENTS];
1404 struct hw_perf_event *hwc = &event->hw;
1405 unsigned long events[MAX_HWEVENTS];
1406 int current_idx_dmy[MAX_HWEVENTS];
1407 const struct perf_event_map *pmap;
1408 int n;
1409
1410 if (atomic_read(&nmi_active) < 0)
1411 return -ENODEV;
1412
1413 /* does not support taken branch sampling */
1414 if (has_branch_stack(event))
1415 return -EOPNOTSUPP;
1416
1417 switch (attr->type) {
1418 case PERF_TYPE_HARDWARE:
1419 if (attr->config >= sparc_pmu->max_events)
1420 return -EINVAL;
1421 pmap = sparc_pmu->event_map(attr->config);
1422 break;
1423
1424 case PERF_TYPE_HW_CACHE:
1425 pmap = sparc_map_cache_event(attr->config);
1426 if (IS_ERR(pmap))
1427 return PTR_ERR(pmap);
1428 break;
1429
1430 case PERF_TYPE_RAW:
1431 pmap = NULL;
1432 break;
1433
1434 default:
1435 return -ENOENT;
1436
1437 }
1438
1439 if (pmap) {
1440 hwc->event_base = perf_event_encode(pmap);
1441 } else {
1442 /*
1443 * User gives us "(encoding << 16) | pic_mask" for
1444 * PERF_TYPE_RAW events.
1445 */
1446 hwc->event_base = attr->config;
1447 }
1448
1449 /* We save the enable bits in the config_base. */
1450 hwc->config_base = sparc_pmu->irq_bit;
1451 if (!attr->exclude_user)
1452 hwc->config_base |= sparc_pmu->user_bit;
1453 if (!attr->exclude_kernel)
1454 hwc->config_base |= sparc_pmu->priv_bit;
1455 if (!attr->exclude_hv)
1456 hwc->config_base |= sparc_pmu->hv_bit;
1457
1458 n = 0;
1459 if (event->group_leader != event) {
1460 n = collect_events(event->group_leader,
1461 sparc_pmu->max_hw_events - 1,
1462 evts, events, current_idx_dmy);
1463 if (n < 0)
1464 return -EINVAL;
1465 }
1466 events[n] = hwc->event_base;
1467 evts[n] = event;
1468
1469 if (check_excludes(evts, n, 1))
1470 return -EINVAL;
1471
1472 if (sparc_check_constraints(evts, events, n + 1))
1473 return -EINVAL;
1474
1475 hwc->idx = PIC_NO_INDEX;
1476
1477 /* Try to do all error checking before this point, as unwinding
1478 * state after grabbing the PMC is difficult.
1479 */
1480 perf_event_grab_pmc();
1481 event->destroy = hw_perf_event_destroy;
1482
1483 if (!hwc->sample_period) {
1484 hwc->sample_period = MAX_PERIOD;
1485 hwc->last_period = hwc->sample_period;
1486 local64_set(&hwc->period_left, hwc->sample_period);
1487 }
1488
1489 return 0;
1490}
1491
1492/*
1493 * Start group events scheduling transaction
1494 * Set the flag to make pmu::enable() not perform the
1495 * schedulability test, it will be performed at commit time
1496 */
1497static void sparc_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
1498{
1499 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1500
1501 WARN_ON_ONCE(cpuhw->txn_flags); /* txn already in flight */
1502
1503 cpuhw->txn_flags = txn_flags;
1504 if (txn_flags & ~PERF_PMU_TXN_ADD)
1505 return;
1506
1507 perf_pmu_disable(pmu);
1508}
1509
1510/*
1511 * Stop group events scheduling transaction
1512 * Clear the flag and pmu::enable() will perform the
1513 * schedulability test.
1514 */
1515static void sparc_pmu_cancel_txn(struct pmu *pmu)
1516{
1517 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1518 unsigned int txn_flags;
1519
1520 WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */
1521
1522 txn_flags = cpuhw->txn_flags;
1523 cpuhw->txn_flags = 0;
1524 if (txn_flags & ~PERF_PMU_TXN_ADD)
1525 return;
1526
1527 perf_pmu_enable(pmu);
1528}
1529
1530/*
1531 * Commit group events scheduling transaction
1532 * Perform the group schedulability test as a whole
1533 * Return 0 if success
1534 */
1535static int sparc_pmu_commit_txn(struct pmu *pmu)
1536{
1537 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1538 int n;
1539
1540 if (!sparc_pmu)
1541 return -EINVAL;
1542
1543 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
1544
1545 if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) {
1546 cpuc->txn_flags = 0;
1547 return 0;
1548 }
1549
1550 n = cpuc->n_events;
1551 if (check_excludes(cpuc->event, 0, n))
1552 return -EINVAL;
1553 if (sparc_check_constraints(cpuc->event, cpuc->events, n))
1554 return -EAGAIN;
1555
1556 cpuc->txn_flags = 0;
1557 perf_pmu_enable(pmu);
1558 return 0;
1559}
1560
1561static struct pmu pmu = {
1562 .pmu_enable = sparc_pmu_enable,
1563 .pmu_disable = sparc_pmu_disable,
1564 .event_init = sparc_pmu_event_init,
1565 .add = sparc_pmu_add,
1566 .del = sparc_pmu_del,
1567 .start = sparc_pmu_start,
1568 .stop = sparc_pmu_stop,
1569 .read = sparc_pmu_read,
1570 .start_txn = sparc_pmu_start_txn,
1571 .cancel_txn = sparc_pmu_cancel_txn,
1572 .commit_txn = sparc_pmu_commit_txn,
1573};
1574
1575void perf_event_print_debug(void)
1576{
1577 unsigned long flags;
1578 int cpu, i;
1579
1580 if (!sparc_pmu)
1581 return;
1582
1583 local_irq_save(flags);
1584
1585 cpu = smp_processor_id();
1586
1587 pr_info("\n");
1588 for (i = 0; i < sparc_pmu->num_pcrs; i++)
1589 pr_info("CPU#%d: PCR%d[%016llx]\n",
1590 cpu, i, pcr_ops->read_pcr(i));
1591 for (i = 0; i < sparc_pmu->num_pic_regs; i++)
1592 pr_info("CPU#%d: PIC%d[%016llx]\n",
1593 cpu, i, pcr_ops->read_pic(i));
1594
1595 local_irq_restore(flags);
1596}
1597
1598static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
1599 unsigned long cmd, void *__args)
1600{
1601 struct die_args *args = __args;
1602 struct perf_sample_data data;
1603 struct cpu_hw_events *cpuc;
1604 struct pt_regs *regs;
1605 int i;
1606
1607 if (!atomic_read(&active_events))
1608 return NOTIFY_DONE;
1609
1610 switch (cmd) {
1611 case DIE_NMI:
1612 break;
1613
1614 default:
1615 return NOTIFY_DONE;
1616 }
1617
1618 regs = args->regs;
1619
1620 cpuc = this_cpu_ptr(&cpu_hw_events);
1621
1622 /* If the PMU has the TOE IRQ enable bits, we need to do a
1623 * dummy write to the %pcr to clear the overflow bits and thus
1624 * the interrupt.
1625 *
1626 * Do this before we peek at the counters to determine
1627 * overflow so we don't lose any events.
1628 */
1629 if (sparc_pmu->irq_bit &&
1630 sparc_pmu->num_pcrs == 1)
1631 pcr_ops->write_pcr(0, cpuc->pcr[0]);
1632
1633 for (i = 0; i < cpuc->n_events; i++) {
1634 struct perf_event *event = cpuc->event[i];
1635 int idx = cpuc->current_idx[i];
1636 struct hw_perf_event *hwc;
1637 u64 val;
1638
1639 if (sparc_pmu->irq_bit &&
1640 sparc_pmu->num_pcrs > 1)
1641 pcr_ops->write_pcr(idx, cpuc->pcr[idx]);
1642
1643 hwc = &event->hw;
1644 val = sparc_perf_event_update(event, hwc, idx);
1645 if (val & (1ULL << 31))
1646 continue;
1647
1648 perf_sample_data_init(&data, 0, hwc->last_period);
1649 if (!sparc_perf_event_set_period(event, hwc, idx))
1650 continue;
1651
1652 if (perf_event_overflow(event, &data, regs))
1653 sparc_pmu_stop(event, 0);
1654 }
1655
1656 return NOTIFY_STOP;
1657}
1658
1659static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1660 .notifier_call = perf_event_nmi_handler,
1661};
1662
1663static bool __init supported_pmu(void)
1664{
1665 if (!strcmp(sparc_pmu_type, "ultra3") ||
1666 !strcmp(sparc_pmu_type, "ultra3+") ||
1667 !strcmp(sparc_pmu_type, "ultra3i") ||
1668 !strcmp(sparc_pmu_type, "ultra4+")) {
1669 sparc_pmu = &ultra3_pmu;
1670 return true;
1671 }
1672 if (!strcmp(sparc_pmu_type, "niagara")) {
1673 sparc_pmu = &niagara1_pmu;
1674 return true;
1675 }
1676 if (!strcmp(sparc_pmu_type, "niagara2") ||
1677 !strcmp(sparc_pmu_type, "niagara3")) {
1678 sparc_pmu = &niagara2_pmu;
1679 return true;
1680 }
1681 if (!strcmp(sparc_pmu_type, "niagara4") ||
1682 !strcmp(sparc_pmu_type, "niagara5")) {
1683 sparc_pmu = &niagara4_pmu;
1684 return true;
1685 }
1686 if (!strcmp(sparc_pmu_type, "sparc-m7")) {
1687 sparc_pmu = &sparc_m7_pmu;
1688 return true;
1689 }
1690 return false;
1691}
1692
1693static int __init init_hw_perf_events(void)
1694{
1695 int err;
1696
1697 pr_info("Performance events: ");
1698
1699 err = pcr_arch_init();
1700 if (err || !supported_pmu()) {
1701 pr_cont("No support for PMU type '%s'\n", sparc_pmu_type);
1702 return 0;
1703 }
1704
1705 pr_cont("Supported PMU type is '%s'\n", sparc_pmu_type);
1706
1707 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1708 register_die_notifier(&perf_event_nmi_notifier);
1709
1710 return 0;
1711}
1712pure_initcall(init_hw_perf_events);
1713
1714void perf_callchain_kernel(struct perf_callchain_entry *entry,
1715 struct pt_regs *regs)
1716{
1717 unsigned long ksp, fp;
1718#ifdef CONFIG_FUNCTION_GRAPH_TRACER
1719 int graph = 0;
1720#endif
1721
1722 stack_trace_flush();
1723
1724 perf_callchain_store(entry, regs->tpc);
1725
1726 ksp = regs->u_regs[UREG_I6];
1727 fp = ksp + STACK_BIAS;
1728 do {
1729 struct sparc_stackf *sf;
1730 struct pt_regs *regs;
1731 unsigned long pc;
1732
1733 if (!kstack_valid(current_thread_info(), fp))
1734 break;
1735
1736 sf = (struct sparc_stackf *) fp;
1737 regs = (struct pt_regs *) (sf + 1);
1738
1739 if (kstack_is_trap_frame(current_thread_info(), regs)) {
1740 if (user_mode(regs))
1741 break;
1742 pc = regs->tpc;
1743 fp = regs->u_regs[UREG_I6] + STACK_BIAS;
1744 } else {
1745 pc = sf->callers_pc;
1746 fp = (unsigned long)sf->fp + STACK_BIAS;
1747 }
1748 perf_callchain_store(entry, pc);
1749#ifdef CONFIG_FUNCTION_GRAPH_TRACER
1750 if ((pc + 8UL) == (unsigned long) &return_to_handler) {
1751 int index = current->curr_ret_stack;
1752 if (current->ret_stack && index >= graph) {
1753 pc = current->ret_stack[index - graph].ret;
1754 perf_callchain_store(entry, pc);
1755 graph++;
1756 }
1757 }
1758#endif
1759 } while (entry->nr < PERF_MAX_STACK_DEPTH);
1760}
1761
1762static inline int
1763valid_user_frame(const void __user *fp, unsigned long size)
1764{
1765 /* addresses should be at least 4-byte aligned */
1766 if (((unsigned long) fp) & 3)
1767 return 0;
1768
1769 return (__range_not_ok(fp, size, TASK_SIZE) == 0);
1770}
1771
1772static void perf_callchain_user_64(struct perf_callchain_entry *entry,
1773 struct pt_regs *regs)
1774{
1775 unsigned long ufp;
1776
1777 ufp = regs->u_regs[UREG_FP] + STACK_BIAS;
1778 do {
1779 struct sparc_stackf __user *usf;
1780 struct sparc_stackf sf;
1781 unsigned long pc;
1782
1783 usf = (struct sparc_stackf __user *)ufp;
1784 if (!valid_user_frame(usf, sizeof(sf)))
1785 break;
1786
1787 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1788 break;
1789
1790 pc = sf.callers_pc;
1791 ufp = (unsigned long)sf.fp + STACK_BIAS;
1792 perf_callchain_store(entry, pc);
1793 } while (entry->nr < PERF_MAX_STACK_DEPTH);
1794}
1795
1796static void perf_callchain_user_32(struct perf_callchain_entry *entry,
1797 struct pt_regs *regs)
1798{
1799 unsigned long ufp;
1800
1801 ufp = regs->u_regs[UREG_FP] & 0xffffffffUL;
1802 do {
1803 unsigned long pc;
1804
1805 if (thread32_stack_is_64bit(ufp)) {
1806 struct sparc_stackf __user *usf;
1807 struct sparc_stackf sf;
1808
1809 ufp += STACK_BIAS;
1810 usf = (struct sparc_stackf __user *)ufp;
1811 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1812 break;
1813 pc = sf.callers_pc & 0xffffffff;
1814 ufp = ((unsigned long) sf.fp) & 0xffffffff;
1815 } else {
1816 struct sparc_stackf32 __user *usf;
1817 struct sparc_stackf32 sf;
1818 usf = (struct sparc_stackf32 __user *)ufp;
1819 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1820 break;
1821 pc = sf.callers_pc;
1822 ufp = (unsigned long)sf.fp;
1823 }
1824 perf_callchain_store(entry, pc);
1825 } while (entry->nr < PERF_MAX_STACK_DEPTH);
1826}
1827
1828void
1829perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1830{
1831 u64 saved_fault_address = current_thread_info()->fault_address;
1832 u8 saved_fault_code = get_thread_fault_code();
1833 mm_segment_t old_fs;
1834
1835 perf_callchain_store(entry, regs->tpc);
1836
1837 if (!current->mm)
1838 return;
1839
1840 old_fs = get_fs();
1841 set_fs(USER_DS);
1842
1843 flushw_user();
1844
1845 pagefault_disable();
1846
1847 if (test_thread_flag(TIF_32BIT))
1848 perf_callchain_user_32(entry, regs);
1849 else
1850 perf_callchain_user_64(entry, regs);
1851
1852 pagefault_enable();
1853
1854 set_fs(old_fs);
1855 set_thread_fault_code(saved_fault_code);
1856 current_thread_info()->fault_address = saved_fault_address;
1857}