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1#ifndef __ASM_SH_PCI_H
2#define __ASM_SH_PCI_H
3
4#ifdef __KERNEL__
5
6/* Can be used to override the logic in pci_scan_bus for skipping
7 already-configured bus numbers - to be used for buggy BIOSes
8 or architectures with incomplete PCI setup by the loader */
9
10#define pcibios_assign_all_busses() 1
11
12/*
13 * A board can define one or more PCI channels that represent built-in (or
14 * external) PCI controllers.
15 */
16struct pci_channel {
17 struct pci_channel *next;
18 struct pci_bus *bus;
19
20 struct pci_ops *pci_ops;
21
22 struct resource *resources;
23 unsigned int nr_resources;
24
25 unsigned long io_offset;
26 unsigned long mem_offset;
27
28 unsigned long reg_base;
29 unsigned long io_map_base;
30
31 unsigned int index;
32 unsigned int need_domain_info;
33
34 /* Optional error handling */
35 struct timer_list err_timer, serr_timer;
36 unsigned int err_irq, serr_irq;
37};
38
39/* arch/sh/drivers/pci/pci.c */
40extern raw_spinlock_t pci_config_lock;
41
42extern int register_pci_controller(struct pci_channel *hose);
43extern void pcibios_report_status(unsigned int status_mask, int warn);
44
45/* arch/sh/drivers/pci/common.c */
46extern int early_read_config_byte(struct pci_channel *hose, int top_bus,
47 int bus, int devfn, int offset, u8 *value);
48extern int early_read_config_word(struct pci_channel *hose, int top_bus,
49 int bus, int devfn, int offset, u16 *value);
50extern int early_read_config_dword(struct pci_channel *hose, int top_bus,
51 int bus, int devfn, int offset, u32 *value);
52extern int early_write_config_byte(struct pci_channel *hose, int top_bus,
53 int bus, int devfn, int offset, u8 value);
54extern int early_write_config_word(struct pci_channel *hose, int top_bus,
55 int bus, int devfn, int offset, u16 value);
56extern int early_write_config_dword(struct pci_channel *hose, int top_bus,
57 int bus, int devfn, int offset, u32 value);
58extern void pcibios_enable_timers(struct pci_channel *hose);
59extern unsigned int pcibios_handle_status_errors(unsigned long addr,
60 unsigned int status, struct pci_channel *hose);
61extern int pci_is_66mhz_capable(struct pci_channel *hose,
62 int top_bus, int current_bus);
63
64extern unsigned long PCIBIOS_MIN_IO, PCIBIOS_MIN_MEM;
65
66struct pci_dev;
67
68#define HAVE_PCI_MMAP
69extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
70 enum pci_mmap_state mmap_state, int write_combine);
71extern void pcibios_set_master(struct pci_dev *dev);
72
73static inline void pcibios_penalize_isa_irq(int irq, int active)
74{
75 /* We don't do dynamic PCI IRQ allocation */
76}
77
78/* Dynamic DMA mapping stuff.
79 * SuperH has everything mapped statically like x86.
80 */
81
82/* The PCI address space does equal the physical memory
83 * address space. The networking and block device layers use
84 * this boolean for bounce buffer decisions.
85 */
86#define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys)
87
88#ifdef CONFIG_PCI
89/*
90 * None of the SH PCI controllers support MWI, it is always treated as a
91 * direct memory write.
92 */
93#define PCI_DISABLE_MWI
94
95static inline void pci_dma_burst_advice(struct pci_dev *pdev,
96 enum pci_dma_burst_strategy *strat,
97 unsigned long *strategy_parameter)
98{
99 unsigned long cacheline_size;
100 u8 byte;
101
102 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
103
104 if (byte == 0)
105 cacheline_size = L1_CACHE_BYTES;
106 else
107 cacheline_size = byte << 2;
108
109 *strat = PCI_DMA_BURST_MULTIPLE;
110 *strategy_parameter = cacheline_size;
111}
112#endif
113
114/* Board-specific fixup routines. */
115int pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin);
116
117#define pci_domain_nr(bus) ((struct pci_channel *)(bus)->sysdata)->index
118
119static inline int pci_proc_domain(struct pci_bus *bus)
120{
121 struct pci_channel *hose = bus->sysdata;
122 return hose->need_domain_info;
123}
124
125/* Chances are this interrupt is wired PC-style ... */
126static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
127{
128 return channel ? 15 : 14;
129}
130
131/* generic DMA-mapping stuff */
132#include <asm-generic/pci-dma-compat.h>
133
134#endif /* __KERNEL__ */
135#endif /* __ASM_SH_PCI_H */
136
1#ifndef __ASM_SH_PCI_H
2#define __ASM_SH_PCI_H
3
4#ifdef __KERNEL__
5
6/* Can be used to override the logic in pci_scan_bus for skipping
7 already-configured bus numbers - to be used for buggy BIOSes
8 or architectures with incomplete PCI setup by the loader */
9
10#define pcibios_assign_all_busses() 1
11
12/*
13 * A board can define one or more PCI channels that represent built-in (or
14 * external) PCI controllers.
15 */
16struct pci_channel {
17 struct pci_channel *next;
18 struct pci_bus *bus;
19
20 struct pci_ops *pci_ops;
21
22 struct resource *resources;
23 unsigned int nr_resources;
24
25 unsigned long io_offset;
26 unsigned long mem_offset;
27
28 unsigned long reg_base;
29 unsigned long io_map_base;
30
31 unsigned int index;
32 unsigned int need_domain_info;
33
34 /* Optional error handling */
35 struct timer_list err_timer, serr_timer;
36 unsigned int err_irq, serr_irq;
37};
38
39/* arch/sh/drivers/pci/pci.c */
40extern raw_spinlock_t pci_config_lock;
41
42extern int register_pci_controller(struct pci_channel *hose);
43extern void pcibios_report_status(unsigned int status_mask, int warn);
44
45/* arch/sh/drivers/pci/common.c */
46extern int early_read_config_byte(struct pci_channel *hose, int top_bus,
47 int bus, int devfn, int offset, u8 *value);
48extern int early_read_config_word(struct pci_channel *hose, int top_bus,
49 int bus, int devfn, int offset, u16 *value);
50extern int early_read_config_dword(struct pci_channel *hose, int top_bus,
51 int bus, int devfn, int offset, u32 *value);
52extern int early_write_config_byte(struct pci_channel *hose, int top_bus,
53 int bus, int devfn, int offset, u8 value);
54extern int early_write_config_word(struct pci_channel *hose, int top_bus,
55 int bus, int devfn, int offset, u16 value);
56extern int early_write_config_dword(struct pci_channel *hose, int top_bus,
57 int bus, int devfn, int offset, u32 value);
58extern void pcibios_enable_timers(struct pci_channel *hose);
59extern unsigned int pcibios_handle_status_errors(unsigned long addr,
60 unsigned int status, struct pci_channel *hose);
61extern int pci_is_66mhz_capable(struct pci_channel *hose,
62 int top_bus, int current_bus);
63
64extern unsigned long PCIBIOS_MIN_IO, PCIBIOS_MIN_MEM;
65
66struct pci_dev;
67
68#define HAVE_PCI_MMAP
69extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
70 enum pci_mmap_state mmap_state, int write_combine);
71extern void pcibios_set_master(struct pci_dev *dev);
72
73/* Dynamic DMA mapping stuff.
74 * SuperH has everything mapped statically like x86.
75 */
76
77/* The PCI address space does equal the physical memory
78 * address space. The networking and block device layers use
79 * this boolean for bounce buffer decisions.
80 */
81#define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys)
82
83#ifdef CONFIG_PCI
84/*
85 * None of the SH PCI controllers support MWI, it is always treated as a
86 * direct memory write.
87 */
88#define PCI_DISABLE_MWI
89#endif
90
91/* Board-specific fixup routines. */
92int pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin);
93
94#define pci_domain_nr(bus) ((struct pci_channel *)(bus)->sysdata)->index
95
96static inline int pci_proc_domain(struct pci_bus *bus)
97{
98 struct pci_channel *hose = bus->sysdata;
99 return hose->need_domain_info;
100}
101
102/* Chances are this interrupt is wired PC-style ... */
103static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
104{
105 return channel ? 15 : 14;
106}
107
108#endif /* __KERNEL__ */
109#endif /* __ASM_SH_PCI_H */
110