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1/*
2 * OpenRISC head.S
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * Modifications for the OpenRISC architecture:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
16 */
17
18#include <linux/linkage.h>
19#include <linux/threads.h>
20#include <linux/errno.h>
21#include <linux/init.h>
22#include <asm/processor.h>
23#include <asm/page.h>
24#include <asm/mmu.h>
25#include <asm/pgtable.h>
26#include <asm/cache.h>
27#include <asm/spr_defs.h>
28#include <asm/asm-offsets.h>
29#include <linux/of_fdt.h>
30
31#define tophys(rd,rs) \
32 l.movhi rd,hi(-KERNELBASE) ;\
33 l.add rd,rd,rs
34
35#define CLEAR_GPR(gpr) \
36 l.or gpr,r0,r0
37
38#define LOAD_SYMBOL_2_GPR(gpr,symbol) \
39 l.movhi gpr,hi(symbol) ;\
40 l.ori gpr,gpr,lo(symbol)
41
42
43#define UART_BASE_ADD 0x90000000
44
45#define EXCEPTION_SR (SPR_SR_DME | SPR_SR_IME | SPR_SR_DCE | SPR_SR_ICE | SPR_SR_SM)
46#define SYSCALL_SR (SPR_SR_DME | SPR_SR_IME | SPR_SR_DCE | SPR_SR_ICE | SPR_SR_IEE | SPR_SR_TEE | SPR_SR_SM)
47
48/* ============================================[ tmp store locations ]=== */
49
50/*
51 * emergency_print temporary stores
52 */
53#define EMERGENCY_PRINT_STORE_GPR4 l.sw 0x20(r0),r4
54#define EMERGENCY_PRINT_LOAD_GPR4 l.lwz r4,0x20(r0)
55
56#define EMERGENCY_PRINT_STORE_GPR5 l.sw 0x24(r0),r5
57#define EMERGENCY_PRINT_LOAD_GPR5 l.lwz r5,0x24(r0)
58
59#define EMERGENCY_PRINT_STORE_GPR6 l.sw 0x28(r0),r6
60#define EMERGENCY_PRINT_LOAD_GPR6 l.lwz r6,0x28(r0)
61
62#define EMERGENCY_PRINT_STORE_GPR7 l.sw 0x2c(r0),r7
63#define EMERGENCY_PRINT_LOAD_GPR7 l.lwz r7,0x2c(r0)
64
65#define EMERGENCY_PRINT_STORE_GPR8 l.sw 0x30(r0),r8
66#define EMERGENCY_PRINT_LOAD_GPR8 l.lwz r8,0x30(r0)
67
68#define EMERGENCY_PRINT_STORE_GPR9 l.sw 0x34(r0),r9
69#define EMERGENCY_PRINT_LOAD_GPR9 l.lwz r9,0x34(r0)
70
71
72/*
73 * TLB miss handlers temorary stores
74 */
75#define EXCEPTION_STORE_GPR9 l.sw 0x10(r0),r9
76#define EXCEPTION_LOAD_GPR9 l.lwz r9,0x10(r0)
77
78#define EXCEPTION_STORE_GPR2 l.sw 0x64(r0),r2
79#define EXCEPTION_LOAD_GPR2 l.lwz r2,0x64(r0)
80
81#define EXCEPTION_STORE_GPR3 l.sw 0x68(r0),r3
82#define EXCEPTION_LOAD_GPR3 l.lwz r3,0x68(r0)
83
84#define EXCEPTION_STORE_GPR4 l.sw 0x6c(r0),r4
85#define EXCEPTION_LOAD_GPR4 l.lwz r4,0x6c(r0)
86
87#define EXCEPTION_STORE_GPR5 l.sw 0x70(r0),r5
88#define EXCEPTION_LOAD_GPR5 l.lwz r5,0x70(r0)
89
90#define EXCEPTION_STORE_GPR6 l.sw 0x74(r0),r6
91#define EXCEPTION_LOAD_GPR6 l.lwz r6,0x74(r0)
92
93
94/*
95 * EXCEPTION_HANDLE temporary stores
96 */
97
98#define EXCEPTION_T_STORE_GPR30 l.sw 0x78(r0),r30
99#define EXCEPTION_T_LOAD_GPR30(reg) l.lwz reg,0x78(r0)
100
101#define EXCEPTION_T_STORE_GPR10 l.sw 0x7c(r0),r10
102#define EXCEPTION_T_LOAD_GPR10(reg) l.lwz reg,0x7c(r0)
103
104#define EXCEPTION_T_STORE_SP l.sw 0x80(r0),r1
105#define EXCEPTION_T_LOAD_SP(reg) l.lwz reg,0x80(r0)
106
107/*
108 * For UNHANLDED_EXCEPTION
109 */
110
111#define EXCEPTION_T_STORE_GPR31 l.sw 0x84(r0),r31
112#define EXCEPTION_T_LOAD_GPR31(reg) l.lwz reg,0x84(r0)
113
114/* =========================================================[ macros ]=== */
115
116
117#define GET_CURRENT_PGD(reg,t1) \
118 LOAD_SYMBOL_2_GPR(reg,current_pgd) ;\
119 tophys (t1,reg) ;\
120 l.lwz reg,0(t1)
121
122
123/*
124 * DSCR: this is a common hook for handling exceptions. it will save
125 * the needed registers, set up stack and pointer to current
126 * then jump to the handler while enabling MMU
127 *
128 * PRMS: handler - a function to jump to. it has to save the
129 * remaining registers to kernel stack, call
130 * appropriate arch-independant exception handler
131 * and finaly jump to ret_from_except
132 *
133 * PREQ: unchanged state from the time exception happened
134 *
135 * POST: SAVED the following registers original value
136 * to the new created exception frame pointed to by r1
137 *
138 * r1 - ksp pointing to the new (exception) frame
139 * r4 - EEAR exception EA
140 * r10 - current pointing to current_thread_info struct
141 * r12 - syscall 0, since we didn't come from syscall
142 * r13 - temp it actually contains new SR, not needed anymore
143 * r31 - handler address of the handler we'll jump to
144 *
145 * handler has to save remaining registers to the exception
146 * ksp frame *before* tainting them!
147 *
148 * NOTE: this function is not reentrant per se. reentrancy is guaranteed
149 * by processor disabling all exceptions/interrupts when exception
150 * accours.
151 *
152 * OPTM: no need to make it so wasteful to extract ksp when in user mode
153 */
154
155#define EXCEPTION_HANDLE(handler) \
156 EXCEPTION_T_STORE_GPR30 ;\
157 l.mfspr r30,r0,SPR_ESR_BASE ;\
158 l.andi r30,r30,SPR_SR_SM ;\
159 l.sfeqi r30,0 ;\
160 EXCEPTION_T_STORE_GPR10 ;\
161 l.bnf 2f /* kernel_mode */ ;\
162 EXCEPTION_T_STORE_SP /* delay slot */ ;\
1631: /* user_mode: */ ;\
164 LOAD_SYMBOL_2_GPR(r1,current_thread_info_set) ;\
165 tophys (r30,r1) ;\
166 /* r10: current_thread_info */ ;\
167 l.lwz r10,0(r30) ;\
168 tophys (r30,r10) ;\
169 l.lwz r1,(TI_KSP)(r30) ;\
170 /* fall through */ ;\
1712: /* kernel_mode: */ ;\
172 /* create new stack frame, save only needed gprs */ ;\
173 /* r1: KSP, r10: current, r4: EEAR, r31: __pa(KSP) */ ;\
174 /* r12: temp, syscall indicator */ ;\
175 l.addi r1,r1,-(INT_FRAME_SIZE) ;\
176 /* r1 is KSP, r30 is __pa(KSP) */ ;\
177 tophys (r30,r1) ;\
178 l.sw PT_GPR12(r30),r12 ;\
179 l.mfspr r12,r0,SPR_EPCR_BASE ;\
180 l.sw PT_PC(r30),r12 ;\
181 l.mfspr r12,r0,SPR_ESR_BASE ;\
182 l.sw PT_SR(r30),r12 ;\
183 /* save r30 */ ;\
184 EXCEPTION_T_LOAD_GPR30(r12) ;\
185 l.sw PT_GPR30(r30),r12 ;\
186 /* save r10 as was prior to exception */ ;\
187 EXCEPTION_T_LOAD_GPR10(r12) ;\
188 l.sw PT_GPR10(r30),r12 ;\
189 /* save PT_SP as was prior to exception */ ;\
190 EXCEPTION_T_LOAD_SP(r12) ;\
191 l.sw PT_SP(r30),r12 ;\
192 /* save exception r4, set r4 = EA */ ;\
193 l.sw PT_GPR4(r30),r4 ;\
194 l.mfspr r4,r0,SPR_EEAR_BASE ;\
195 /* r12 == 1 if we come from syscall */ ;\
196 CLEAR_GPR(r12) ;\
197 /* ----- turn on MMU ----- */ ;\
198 l.ori r30,r0,(EXCEPTION_SR) ;\
199 l.mtspr r0,r30,SPR_ESR_BASE ;\
200 /* r30: EA address of handler */ ;\
201 LOAD_SYMBOL_2_GPR(r30,handler) ;\
202 l.mtspr r0,r30,SPR_EPCR_BASE ;\
203 l.rfe
204
205/*
206 * this doesn't work
207 *
208 *
209 * #ifdef CONFIG_JUMP_UPON_UNHANDLED_EXCEPTION
210 * #define UNHANDLED_EXCEPTION(handler) \
211 * l.ori r3,r0,0x1 ;\
212 * l.mtspr r0,r3,SPR_SR ;\
213 * l.movhi r3,hi(0xf0000100) ;\
214 * l.ori r3,r3,lo(0xf0000100) ;\
215 * l.jr r3 ;\
216 * l.nop 1
217 *
218 * #endif
219 */
220
221/* DSCR: this is the same as EXCEPTION_HANDLE(), we are just
222 * a bit more carefull (if we have a PT_SP or current pointer
223 * corruption) and set them up from 'current_set'
224 *
225 */
226#define UNHANDLED_EXCEPTION(handler) \
227 EXCEPTION_T_STORE_GPR31 ;\
228 EXCEPTION_T_STORE_GPR10 ;\
229 EXCEPTION_T_STORE_SP ;\
230 /* temporary store r3, r9 into r1, r10 */ ;\
231 l.addi r1,r3,0x0 ;\
232 l.addi r10,r9,0x0 ;\
233 /* the string referenced by r3 must be low enough */ ;\
234 l.jal _emergency_print ;\
235 l.ori r3,r0,lo(_string_unhandled_exception) ;\
236 l.mfspr r3,r0,SPR_NPC ;\
237 l.jal _emergency_print_nr ;\
238 l.andi r3,r3,0x1f00 ;\
239 /* the string referenced by r3 must be low enough */ ;\
240 l.jal _emergency_print ;\
241 l.ori r3,r0,lo(_string_epc_prefix) ;\
242 l.jal _emergency_print_nr ;\
243 l.mfspr r3,r0,SPR_EPCR_BASE ;\
244 l.jal _emergency_print ;\
245 l.ori r3,r0,lo(_string_nl) ;\
246 /* end of printing */ ;\
247 l.addi r3,r1,0x0 ;\
248 l.addi r9,r10,0x0 ;\
249 /* extract current, ksp from current_set */ ;\
250 LOAD_SYMBOL_2_GPR(r1,_unhandled_stack_top) ;\
251 LOAD_SYMBOL_2_GPR(r10,init_thread_union) ;\
252 /* create new stack frame, save only needed gprs */ ;\
253 /* r1: KSP, r10: current, r31: __pa(KSP) */ ;\
254 /* r12: temp, syscall indicator, r13 temp */ ;\
255 l.addi r1,r1,-(INT_FRAME_SIZE) ;\
256 /* r1 is KSP, r31 is __pa(KSP) */ ;\
257 tophys (r31,r1) ;\
258 l.sw PT_GPR12(r31),r12 ;\
259 l.mfspr r12,r0,SPR_EPCR_BASE ;\
260 l.sw PT_PC(r31),r12 ;\
261 l.mfspr r12,r0,SPR_ESR_BASE ;\
262 l.sw PT_SR(r31),r12 ;\
263 /* save r31 */ ;\
264 EXCEPTION_T_LOAD_GPR31(r12) ;\
265 l.sw PT_GPR31(r31),r12 ;\
266 /* save r10 as was prior to exception */ ;\
267 EXCEPTION_T_LOAD_GPR10(r12) ;\
268 l.sw PT_GPR10(r31),r12 ;\
269 /* save PT_SP as was prior to exception */ ;\
270 EXCEPTION_T_LOAD_SP(r12) ;\
271 l.sw PT_SP(r31),r12 ;\
272 l.sw PT_GPR13(r31),r13 ;\
273 /* --> */ ;\
274 /* save exception r4, set r4 = EA */ ;\
275 l.sw PT_GPR4(r31),r4 ;\
276 l.mfspr r4,r0,SPR_EEAR_BASE ;\
277 /* r12 == 1 if we come from syscall */ ;\
278 CLEAR_GPR(r12) ;\
279 /* ----- play a MMU trick ----- */ ;\
280 l.ori r31,r0,(EXCEPTION_SR) ;\
281 l.mtspr r0,r31,SPR_ESR_BASE ;\
282 /* r31: EA address of handler */ ;\
283 LOAD_SYMBOL_2_GPR(r31,handler) ;\
284 l.mtspr r0,r31,SPR_EPCR_BASE ;\
285 l.rfe
286
287/* =====================================================[ exceptions] === */
288
289/* ---[ 0x100: RESET exception ]----------------------------------------- */
290 .org 0x100
291 /* Jump to .init code at _start which lives in the .head section
292 * and will be discarded after boot.
293 */
294 LOAD_SYMBOL_2_GPR(r4, _start)
295 tophys (r3,r4) /* MMU disabled */
296 l.jr r3
297 l.nop
298
299/* ---[ 0x200: BUS exception ]------------------------------------------- */
300 .org 0x200
301_dispatch_bus_fault:
302 EXCEPTION_HANDLE(_bus_fault_handler)
303
304/* ---[ 0x300: Data Page Fault exception ]------------------------------- */
305 .org 0x300
306_dispatch_do_dpage_fault:
307// totaly disable timer interrupt
308// l.mtspr r0,r0,SPR_TTMR
309// DEBUG_TLB_PROBE(0x300)
310// EXCEPTION_DEBUG_VALUE_ER_ENABLED(0x300)
311 EXCEPTION_HANDLE(_data_page_fault_handler)
312
313/* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
314 .org 0x400
315_dispatch_do_ipage_fault:
316// totaly disable timer interrupt
317// l.mtspr r0,r0,SPR_TTMR
318// DEBUG_TLB_PROBE(0x400)
319// EXCEPTION_DEBUG_VALUE_ER_ENABLED(0x400)
320 EXCEPTION_HANDLE(_insn_page_fault_handler)
321
322/* ---[ 0x500: Timer exception ]----------------------------------------- */
323 .org 0x500
324 EXCEPTION_HANDLE(_timer_handler)
325
326/* ---[ 0x600: Aligment exception ]-------------------------------------- */
327 .org 0x600
328 EXCEPTION_HANDLE(_alignment_handler)
329
330/* ---[ 0x700: Illegal insn exception ]---------------------------------- */
331 .org 0x700
332 EXCEPTION_HANDLE(_illegal_instruction_handler)
333
334/* ---[ 0x800: External interrupt exception ]---------------------------- */
335 .org 0x800
336 EXCEPTION_HANDLE(_external_irq_handler)
337
338/* ---[ 0x900: DTLB miss exception ]------------------------------------- */
339 .org 0x900
340 l.j boot_dtlb_miss_handler
341 l.nop
342
343/* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
344 .org 0xa00
345 l.j boot_itlb_miss_handler
346 l.nop
347
348/* ---[ 0xb00: Range exception ]----------------------------------------- */
349 .org 0xb00
350 UNHANDLED_EXCEPTION(_vector_0xb00)
351
352/* ---[ 0xc00: Syscall exception ]--------------------------------------- */
353 .org 0xc00
354 EXCEPTION_HANDLE(_sys_call_handler)
355
356/* ---[ 0xd00: Trap exception ]------------------------------------------ */
357 .org 0xd00
358 UNHANDLED_EXCEPTION(_vector_0xd00)
359
360/* ---[ 0xe00: Trap exception ]------------------------------------------ */
361 .org 0xe00
362// UNHANDLED_EXCEPTION(_vector_0xe00)
363 EXCEPTION_HANDLE(_trap_handler)
364
365/* ---[ 0xf00: Reserved exception ]-------------------------------------- */
366 .org 0xf00
367 UNHANDLED_EXCEPTION(_vector_0xf00)
368
369/* ---[ 0x1000: Reserved exception ]------------------------------------- */
370 .org 0x1000
371 UNHANDLED_EXCEPTION(_vector_0x1000)
372
373/* ---[ 0x1100: Reserved exception ]------------------------------------- */
374 .org 0x1100
375 UNHANDLED_EXCEPTION(_vector_0x1100)
376
377/* ---[ 0x1200: Reserved exception ]------------------------------------- */
378 .org 0x1200
379 UNHANDLED_EXCEPTION(_vector_0x1200)
380
381/* ---[ 0x1300: Reserved exception ]------------------------------------- */
382 .org 0x1300
383 UNHANDLED_EXCEPTION(_vector_0x1300)
384
385/* ---[ 0x1400: Reserved exception ]------------------------------------- */
386 .org 0x1400
387 UNHANDLED_EXCEPTION(_vector_0x1400)
388
389/* ---[ 0x1500: Reserved exception ]------------------------------------- */
390 .org 0x1500
391 UNHANDLED_EXCEPTION(_vector_0x1500)
392
393/* ---[ 0x1600: Reserved exception ]------------------------------------- */
394 .org 0x1600
395 UNHANDLED_EXCEPTION(_vector_0x1600)
396
397/* ---[ 0x1700: Reserved exception ]------------------------------------- */
398 .org 0x1700
399 UNHANDLED_EXCEPTION(_vector_0x1700)
400
401/* ---[ 0x1800: Reserved exception ]------------------------------------- */
402 .org 0x1800
403 UNHANDLED_EXCEPTION(_vector_0x1800)
404
405/* ---[ 0x1900: Reserved exception ]------------------------------------- */
406 .org 0x1900
407 UNHANDLED_EXCEPTION(_vector_0x1900)
408
409/* ---[ 0x1a00: Reserved exception ]------------------------------------- */
410 .org 0x1a00
411 UNHANDLED_EXCEPTION(_vector_0x1a00)
412
413/* ---[ 0x1b00: Reserved exception ]------------------------------------- */
414 .org 0x1b00
415 UNHANDLED_EXCEPTION(_vector_0x1b00)
416
417/* ---[ 0x1c00: Reserved exception ]------------------------------------- */
418 .org 0x1c00
419 UNHANDLED_EXCEPTION(_vector_0x1c00)
420
421/* ---[ 0x1d00: Reserved exception ]------------------------------------- */
422 .org 0x1d00
423 UNHANDLED_EXCEPTION(_vector_0x1d00)
424
425/* ---[ 0x1e00: Reserved exception ]------------------------------------- */
426 .org 0x1e00
427 UNHANDLED_EXCEPTION(_vector_0x1e00)
428
429/* ---[ 0x1f00: Reserved exception ]------------------------------------- */
430 .org 0x1f00
431 UNHANDLED_EXCEPTION(_vector_0x1f00)
432
433 .org 0x2000
434/* ===================================================[ kernel start ]=== */
435
436/* .text*/
437
438/* This early stuff belongs in HEAD, but some of the functions below definitely
439 * don't... */
440
441 __HEAD
442 .global _start
443_start:
444 /* save kernel parameters */
445 l.or r25,r0,r3 /* pointer to fdt */
446
447 /*
448 * ensure a deterministic start
449 */
450
451 l.ori r3,r0,0x1
452 l.mtspr r0,r3,SPR_SR
453
454 CLEAR_GPR(r1)
455 CLEAR_GPR(r2)
456 CLEAR_GPR(r3)
457 CLEAR_GPR(r4)
458 CLEAR_GPR(r5)
459 CLEAR_GPR(r6)
460 CLEAR_GPR(r7)
461 CLEAR_GPR(r8)
462 CLEAR_GPR(r9)
463 CLEAR_GPR(r10)
464 CLEAR_GPR(r11)
465 CLEAR_GPR(r12)
466 CLEAR_GPR(r13)
467 CLEAR_GPR(r14)
468 CLEAR_GPR(r15)
469 CLEAR_GPR(r16)
470 CLEAR_GPR(r17)
471 CLEAR_GPR(r18)
472 CLEAR_GPR(r19)
473 CLEAR_GPR(r20)
474 CLEAR_GPR(r21)
475 CLEAR_GPR(r22)
476 CLEAR_GPR(r23)
477 CLEAR_GPR(r24)
478 CLEAR_GPR(r26)
479 CLEAR_GPR(r27)
480 CLEAR_GPR(r28)
481 CLEAR_GPR(r29)
482 CLEAR_GPR(r30)
483 CLEAR_GPR(r31)
484
485 /*
486 * set up initial ksp and current
487 */
488 LOAD_SYMBOL_2_GPR(r1,init_thread_union+0x2000) // setup kernel stack
489 LOAD_SYMBOL_2_GPR(r10,init_thread_union) // setup current
490 tophys (r31,r10)
491 l.sw TI_KSP(r31), r1
492
493 l.ori r4,r0,0x0
494
495
496 /*
497 * .data contains initialized data,
498 * .bss contains uninitialized data - clear it up
499 */
500clear_bss:
501 LOAD_SYMBOL_2_GPR(r24, __bss_start)
502 LOAD_SYMBOL_2_GPR(r26, _end)
503 tophys(r28,r24)
504 tophys(r30,r26)
505 CLEAR_GPR(r24)
506 CLEAR_GPR(r26)
5071:
508 l.sw (0)(r28),r0
509 l.sfltu r28,r30
510 l.bf 1b
511 l.addi r28,r28,4
512
513enable_ic:
514 l.jal _ic_enable
515 l.nop
516
517enable_dc:
518 l.jal _dc_enable
519 l.nop
520
521flush_tlb:
522 /*
523 * I N V A L I D A T E T L B e n t r i e s
524 */
525 LOAD_SYMBOL_2_GPR(r5,SPR_DTLBMR_BASE(0))
526 LOAD_SYMBOL_2_GPR(r6,SPR_ITLBMR_BASE(0))
527 l.addi r7,r0,128 /* Maximum number of sets */
5281:
529 l.mtspr r5,r0,0x0
530 l.mtspr r6,r0,0x0
531
532 l.addi r5,r5,1
533 l.addi r6,r6,1
534 l.sfeq r7,r0
535 l.bnf 1b
536 l.addi r7,r7,-1
537
538
539/* The MMU needs to be enabled before or32_early_setup is called */
540
541enable_mmu:
542 /*
543 * enable dmmu & immu
544 * SR[5] = 0, SR[6] = 0, 6th and 7th bit of SR set to 0
545 */
546 l.mfspr r30,r0,SPR_SR
547 l.movhi r28,hi(SPR_SR_DME | SPR_SR_IME)
548 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
549 l.or r30,r30,r28
550 l.mtspr r0,r30,SPR_SR
551 l.nop
552 l.nop
553 l.nop
554 l.nop
555 l.nop
556 l.nop
557 l.nop
558 l.nop
559 l.nop
560 l.nop
561 l.nop
562 l.nop
563 l.nop
564 l.nop
565 l.nop
566 l.nop
567
568 // reset the simulation counters
569 l.nop 5
570
571 /* check fdt header magic word */
572 l.lwz r3,0(r25) /* load magic from fdt into r3 */
573 l.movhi r4,hi(OF_DT_HEADER)
574 l.ori r4,r4,lo(OF_DT_HEADER)
575 l.sfeq r3,r4
576 l.bf _fdt_found
577 l.nop
578 /* magic number mismatch, set fdt pointer to null */
579 l.or r25,r0,r0
580_fdt_found:
581 /* pass fdt pointer to or32_early_setup in r3 */
582 l.or r3,r0,r25
583 LOAD_SYMBOL_2_GPR(r24, or32_early_setup)
584 l.jalr r24
585 l.nop
586
587clear_regs:
588 /*
589 * clear all GPRS to increase determinism
590 */
591 CLEAR_GPR(r2)
592 CLEAR_GPR(r3)
593 CLEAR_GPR(r4)
594 CLEAR_GPR(r5)
595 CLEAR_GPR(r6)
596 CLEAR_GPR(r7)
597 CLEAR_GPR(r8)
598 CLEAR_GPR(r9)
599 CLEAR_GPR(r11)
600 CLEAR_GPR(r12)
601 CLEAR_GPR(r13)
602 CLEAR_GPR(r14)
603 CLEAR_GPR(r15)
604 CLEAR_GPR(r16)
605 CLEAR_GPR(r17)
606 CLEAR_GPR(r18)
607 CLEAR_GPR(r19)
608 CLEAR_GPR(r20)
609 CLEAR_GPR(r21)
610 CLEAR_GPR(r22)
611 CLEAR_GPR(r23)
612 CLEAR_GPR(r24)
613 CLEAR_GPR(r25)
614 CLEAR_GPR(r26)
615 CLEAR_GPR(r27)
616 CLEAR_GPR(r28)
617 CLEAR_GPR(r29)
618 CLEAR_GPR(r30)
619 CLEAR_GPR(r31)
620
621jump_start_kernel:
622 /*
623 * jump to kernel entry (start_kernel)
624 */
625 LOAD_SYMBOL_2_GPR(r30, start_kernel)
626 l.jr r30
627 l.nop
628
629/* ========================================[ cache ]=== */
630
631 /* aligment here so we don't change memory offsets with
632 * memory controler defined
633 */
634 .align 0x2000
635
636_ic_enable:
637 /* Check if IC present and skip enabling otherwise */
638 l.mfspr r24,r0,SPR_UPR
639 l.andi r26,r24,SPR_UPR_ICP
640 l.sfeq r26,r0
641 l.bf 9f
642 l.nop
643
644 /* Disable IC */
645 l.mfspr r6,r0,SPR_SR
646 l.addi r5,r0,-1
647 l.xori r5,r5,SPR_SR_ICE
648 l.and r5,r6,r5
649 l.mtspr r0,r5,SPR_SR
650
651 /* Establish cache block size
652 If BS=0, 16;
653 If BS=1, 32;
654 r14 contain block size
655 */
656 l.mfspr r24,r0,SPR_ICCFGR
657 l.andi r26,r24,SPR_ICCFGR_CBS
658 l.srli r28,r26,7
659 l.ori r30,r0,16
660 l.sll r14,r30,r28
661
662 /* Establish number of cache sets
663 r16 contains number of cache sets
664 r28 contains log(# of cache sets)
665 */
666 l.andi r26,r24,SPR_ICCFGR_NCS
667 l.srli r28,r26,3
668 l.ori r30,r0,1
669 l.sll r16,r30,r28
670
671 /* Invalidate IC */
672 l.addi r6,r0,0
673 l.sll r5,r14,r28
674// l.mul r5,r14,r16
675// l.trap 1
676// l.addi r5,r0,IC_SIZE
6771:
678 l.mtspr r0,r6,SPR_ICBIR
679 l.sfne r6,r5
680 l.bf 1b
681 l.add r6,r6,r14
682 // l.addi r6,r6,IC_LINE
683
684 /* Enable IC */
685 l.mfspr r6,r0,SPR_SR
686 l.ori r6,r6,SPR_SR_ICE
687 l.mtspr r0,r6,SPR_SR
688 l.nop
689 l.nop
690 l.nop
691 l.nop
692 l.nop
693 l.nop
694 l.nop
695 l.nop
696 l.nop
697 l.nop
6989:
699 l.jr r9
700 l.nop
701
702_dc_enable:
703 /* Check if DC present and skip enabling otherwise */
704 l.mfspr r24,r0,SPR_UPR
705 l.andi r26,r24,SPR_UPR_DCP
706 l.sfeq r26,r0
707 l.bf 9f
708 l.nop
709
710 /* Disable DC */
711 l.mfspr r6,r0,SPR_SR
712 l.addi r5,r0,-1
713 l.xori r5,r5,SPR_SR_DCE
714 l.and r5,r6,r5
715 l.mtspr r0,r5,SPR_SR
716
717 /* Establish cache block size
718 If BS=0, 16;
719 If BS=1, 32;
720 r14 contain block size
721 */
722 l.mfspr r24,r0,SPR_DCCFGR
723 l.andi r26,r24,SPR_DCCFGR_CBS
724 l.srli r28,r26,7
725 l.ori r30,r0,16
726 l.sll r14,r30,r28
727
728 /* Establish number of cache sets
729 r16 contains number of cache sets
730 r28 contains log(# of cache sets)
731 */
732 l.andi r26,r24,SPR_DCCFGR_NCS
733 l.srli r28,r26,3
734 l.ori r30,r0,1
735 l.sll r16,r30,r28
736
737 /* Invalidate DC */
738 l.addi r6,r0,0
739 l.sll r5,r14,r28
7401:
741 l.mtspr r0,r6,SPR_DCBIR
742 l.sfne r6,r5
743 l.bf 1b
744 l.add r6,r6,r14
745
746 /* Enable DC */
747 l.mfspr r6,r0,SPR_SR
748 l.ori r6,r6,SPR_SR_DCE
749 l.mtspr r0,r6,SPR_SR
7509:
751 l.jr r9
752 l.nop
753
754/* ===============================================[ page table masks ]=== */
755
756/* bit 4 is used in hardware as write back cache bit. we never use this bit
757 * explicitly, so we can reuse it as _PAGE_FILE bit and mask it out when
758 * writing into hardware pte's
759 */
760
761#define DTLB_UP_CONVERT_MASK 0x3fa
762#define ITLB_UP_CONVERT_MASK 0x3a
763
764/* for SMP we'd have (this is a bit subtle, CC must be always set
765 * for SMP, but since we have _PAGE_PRESENT bit always defined
766 * we can just modify the mask)
767 */
768#define DTLB_SMP_CONVERT_MASK 0x3fb
769#define ITLB_SMP_CONVERT_MASK 0x3b
770
771/* ---[ boot dtlb miss handler ]----------------------------------------- */
772
773boot_dtlb_miss_handler:
774
775/* mask for DTLB_MR register: - (0) sets V (valid) bit,
776 * - (31-12) sets bits belonging to VPN (31-12)
777 */
778#define DTLB_MR_MASK 0xfffff001
779
780/* mask for DTLB_TR register: - (2) sets CI (cache inhibit) bit,
781 * - (4) sets A (access) bit,
782 * - (5) sets D (dirty) bit,
783 * - (8) sets SRE (superuser read) bit
784 * - (9) sets SWE (superuser write) bit
785 * - (31-12) sets bits belonging to VPN (31-12)
786 */
787#define DTLB_TR_MASK 0xfffff332
788
789/* These are for masking out the VPN/PPN value from the MR/TR registers...
790 * it's not the same as the PFN */
791#define VPN_MASK 0xfffff000
792#define PPN_MASK 0xfffff000
793
794
795 EXCEPTION_STORE_GPR6
796
797#if 0
798 l.mfspr r6,r0,SPR_ESR_BASE //
799 l.andi r6,r6,SPR_SR_SM // are we in kernel mode ?
800 l.sfeqi r6,0 // r6 == 0x1 --> SM
801 l.bf exit_with_no_dtranslation //
802 l.nop
803#endif
804
805 /* this could be optimized by moving storing of
806 * non r6 registers here, and jumping r6 restore
807 * if not in supervisor mode
808 */
809
810 EXCEPTION_STORE_GPR2
811 EXCEPTION_STORE_GPR3
812 EXCEPTION_STORE_GPR4
813 EXCEPTION_STORE_GPR5
814
815 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA
816
817immediate_translation:
818 CLEAR_GPR(r6)
819
820 l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN size (4Kb)
821
822 l.mfspr r6, r0, SPR_DMMUCFGR
823 l.andi r6, r6, SPR_DMMUCFGR_NTS
824 l.srli r6, r6, SPR_DMMUCFGR_NTS_OFF
825 l.ori r5, r0, 0x1
826 l.sll r5, r5, r6 // r5 = number DMMU sets
827 l.addi r6, r5, -1 // r6 = nsets mask
828 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
829
830 l.or r6,r6,r4 // r6 <- r4
831 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
832 l.movhi r5,hi(DTLB_MR_MASK) // r5 <- ffff:0000.x000
833 l.ori r5,r5,lo(DTLB_MR_MASK) // r5 <- ffff:1111.x001 - apply DTLB_MR_MASK
834 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have DTLBMR entry
835 l.mtspr r2,r5,SPR_DTLBMR_BASE(0) // set DTLBMR
836
837 /* set up DTLB with no translation for EA <= 0xbfffffff */
838 LOAD_SYMBOL_2_GPR(r6,0xbfffffff)
839 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xbfffffff >= EA)
840 l.bf 1f // goto out
841 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
842
843 tophys(r3,r4) // r3 <- PA
8441:
845 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
846 l.movhi r5,hi(DTLB_TR_MASK) // r5 <- ffff:0000.x000
847 l.ori r5,r5,lo(DTLB_TR_MASK) // r5 <- ffff:1111.x330 - apply DTLB_MR_MASK
848 l.and r5,r5,r3 // r5 <- PPN :PPN .x330 - we have DTLBTR entry
849 l.mtspr r2,r5,SPR_DTLBTR_BASE(0) // set DTLBTR
850
851 EXCEPTION_LOAD_GPR6
852 EXCEPTION_LOAD_GPR5
853 EXCEPTION_LOAD_GPR4
854 EXCEPTION_LOAD_GPR3
855 EXCEPTION_LOAD_GPR2
856
857 l.rfe // SR <- ESR, PC <- EPC
858
859exit_with_no_dtranslation:
860 /* EA out of memory or not in supervisor mode */
861 EXCEPTION_LOAD_GPR6
862 EXCEPTION_LOAD_GPR4
863 l.j _dispatch_bus_fault
864
865/* ---[ boot itlb miss handler ]----------------------------------------- */
866
867boot_itlb_miss_handler:
868
869/* mask for ITLB_MR register: - sets V (valid) bit,
870 * - sets bits belonging to VPN (15-12)
871 */
872#define ITLB_MR_MASK 0xfffff001
873
874/* mask for ITLB_TR register: - sets A (access) bit,
875 * - sets SXE (superuser execute) bit
876 * - sets bits belonging to VPN (15-12)
877 */
878#define ITLB_TR_MASK 0xfffff050
879
880/*
881#define VPN_MASK 0xffffe000
882#define PPN_MASK 0xffffe000
883*/
884
885
886
887 EXCEPTION_STORE_GPR2
888 EXCEPTION_STORE_GPR3
889 EXCEPTION_STORE_GPR4
890 EXCEPTION_STORE_GPR5
891 EXCEPTION_STORE_GPR6
892
893#if 0
894 l.mfspr r6,r0,SPR_ESR_BASE //
895 l.andi r6,r6,SPR_SR_SM // are we in kernel mode ?
896 l.sfeqi r6,0 // r6 == 0x1 --> SM
897 l.bf exit_with_no_itranslation
898 l.nop
899#endif
900
901
902 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA
903
904earlyearly:
905 CLEAR_GPR(r6)
906
907 l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN size (4Kb)
908
909 l.mfspr r6, r0, SPR_IMMUCFGR
910 l.andi r6, r6, SPR_IMMUCFGR_NTS
911 l.srli r6, r6, SPR_IMMUCFGR_NTS_OFF
912 l.ori r5, r0, 0x1
913 l.sll r5, r5, r6 // r5 = number IMMU sets from IMMUCFGR
914 l.addi r6, r5, -1 // r6 = nsets mask
915 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
916
917 l.or r6,r6,r4 // r6 <- r4
918 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
919 l.movhi r5,hi(ITLB_MR_MASK) // r5 <- ffff:0000.x000
920 l.ori r5,r5,lo(ITLB_MR_MASK) // r5 <- ffff:1111.x001 - apply ITLB_MR_MASK
921 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have ITLBMR entry
922 l.mtspr r2,r5,SPR_ITLBMR_BASE(0) // set ITLBMR
923
924 /*
925 * set up ITLB with no translation for EA <= 0x0fffffff
926 *
927 * we need this for head.S mapping (EA = PA). if we move all functions
928 * which run with mmu enabled into entry.S, we might be able to eliminate this.
929 *
930 */
931 LOAD_SYMBOL_2_GPR(r6,0x0fffffff)
932 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xb0ffffff >= EA)
933 l.bf 1f // goto out
934 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
935
936 tophys(r3,r4) // r3 <- PA
9371:
938 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
939 l.movhi r5,hi(ITLB_TR_MASK) // r5 <- ffff:0000.x000
940 l.ori r5,r5,lo(ITLB_TR_MASK) // r5 <- ffff:1111.x050 - apply ITLB_MR_MASK
941 l.and r5,r5,r3 // r5 <- PPN :PPN .x050 - we have ITLBTR entry
942 l.mtspr r2,r5,SPR_ITLBTR_BASE(0) // set ITLBTR
943
944 EXCEPTION_LOAD_GPR6
945 EXCEPTION_LOAD_GPR5
946 EXCEPTION_LOAD_GPR4
947 EXCEPTION_LOAD_GPR3
948 EXCEPTION_LOAD_GPR2
949
950 l.rfe // SR <- ESR, PC <- EPC
951
952exit_with_no_itranslation:
953 EXCEPTION_LOAD_GPR4
954 EXCEPTION_LOAD_GPR6
955 l.j _dispatch_bus_fault
956 l.nop
957
958/* ====================================================================== */
959/*
960 * Stuff below here shouldn't go into .head section... maybe this stuff
961 * can be moved to entry.S ???
962 */
963
964/* ==============================================[ DTLB miss handler ]=== */
965
966/*
967 * Comments:
968 * Exception handlers are entered with MMU off so the following handler
969 * needs to use physical addressing
970 *
971 */
972
973 .text
974ENTRY(dtlb_miss_handler)
975 EXCEPTION_STORE_GPR2
976 EXCEPTION_STORE_GPR3
977 EXCEPTION_STORE_GPR4
978 EXCEPTION_STORE_GPR5
979 EXCEPTION_STORE_GPR6
980 /*
981 * get EA of the miss
982 */
983 l.mfspr r2,r0,SPR_EEAR_BASE
984 /*
985 * pmd = (pmd_t *)(current_pgd + pgd_index(daddr));
986 */
987 GET_CURRENT_PGD(r3,r5) // r3 is current_pgd, r5 is temp
988 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
989 l.slli r4,r4,0x2 // to get address << 2
990 l.add r5,r4,r3 // r4 is pgd_index(daddr)
991 /*
992 * if (pmd_none(*pmd))
993 * goto pmd_none:
994 */
995 tophys (r4,r5)
996 l.lwz r3,0x0(r4) // get *pmd value
997 l.sfne r3,r0
998 l.bnf d_pmd_none
999 l.andi r3,r3,~PAGE_MASK //0x1fff // ~PAGE_MASK
1000 /*
1001 * if (pmd_bad(*pmd))
1002 * pmd_clear(pmd)
1003 * goto pmd_bad:
1004 */
1005// l.sfeq r3,r0 // check *pmd value
1006// l.bf d_pmd_good
1007 l.addi r3,r0,0xffffe000 // PAGE_MASK
1008// l.j d_pmd_bad
1009// l.sw 0x0(r4),r0 // clear pmd
1010d_pmd_good:
1011 /*
1012 * pte = *pte_offset(pmd, daddr);
1013 */
1014 l.lwz r4,0x0(r4) // get **pmd value
1015 l.and r4,r4,r3 // & PAGE_MASK
1016 l.srli r5,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
1017 l.andi r3,r5,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1018 l.slli r3,r3,0x2 // to get address << 2
1019 l.add r3,r3,r4
1020 l.lwz r2,0x0(r3) // this is pte at last
1021 /*
1022 * if (!pte_present(pte))
1023 */
1024 l.andi r4,r2,0x1
1025 l.sfne r4,r0 // is pte present
1026 l.bnf d_pte_not_present
1027 l.addi r3,r0,0xffffe3fa // PAGE_MASK | DTLB_UP_CONVERT_MASK
1028 /*
1029 * fill DTLB TR register
1030 */
1031 l.and r4,r2,r3 // apply the mask
1032 // Determine number of DMMU sets
1033 l.mfspr r6, r0, SPR_DMMUCFGR
1034 l.andi r6, r6, SPR_DMMUCFGR_NTS
1035 l.srli r6, r6, SPR_DMMUCFGR_NTS_OFF
1036 l.ori r3, r0, 0x1
1037 l.sll r3, r3, r6 // r3 = number DMMU sets DMMUCFGR
1038 l.addi r6, r3, -1 // r6 = nsets mask
1039 l.and r5, r5, r6 // calc offset: & (NUM_TLB_ENTRIES-1)
1040 //NUM_TLB_ENTRIES
1041 l.mtspr r5,r4,SPR_DTLBTR_BASE(0)
1042 /*
1043 * fill DTLB MR register
1044 */
1045 l.mfspr r2,r0,SPR_EEAR_BASE
1046 l.addi r3,r0,0xffffe000 // PAGE_MASK
1047 l.and r4,r2,r3 // apply PAGE_MASK to EA (__PHX__ do we really need this?)
1048 l.ori r4,r4,0x1 // set hardware valid bit: DTBL_MR entry
1049 l.mtspr r5,r4,SPR_DTLBMR_BASE(0)
1050
1051 EXCEPTION_LOAD_GPR2
1052 EXCEPTION_LOAD_GPR3
1053 EXCEPTION_LOAD_GPR4
1054 EXCEPTION_LOAD_GPR5
1055 EXCEPTION_LOAD_GPR6
1056 l.rfe
1057d_pmd_bad:
1058 l.nop 1
1059 EXCEPTION_LOAD_GPR2
1060 EXCEPTION_LOAD_GPR3
1061 EXCEPTION_LOAD_GPR4
1062 EXCEPTION_LOAD_GPR5
1063 EXCEPTION_LOAD_GPR6
1064 l.rfe
1065d_pmd_none:
1066d_pte_not_present:
1067 EXCEPTION_LOAD_GPR2
1068 EXCEPTION_LOAD_GPR3
1069 EXCEPTION_LOAD_GPR4
1070 EXCEPTION_LOAD_GPR5
1071 EXCEPTION_LOAD_GPR6
1072 l.j _dispatch_do_dpage_fault
1073 l.nop
1074
1075/* ==============================================[ ITLB miss handler ]=== */
1076ENTRY(itlb_miss_handler)
1077 EXCEPTION_STORE_GPR2
1078 EXCEPTION_STORE_GPR3
1079 EXCEPTION_STORE_GPR4
1080 EXCEPTION_STORE_GPR5
1081 EXCEPTION_STORE_GPR6
1082 /*
1083 * get EA of the miss
1084 */
1085 l.mfspr r2,r0,SPR_EEAR_BASE
1086
1087 /*
1088 * pmd = (pmd_t *)(current_pgd + pgd_index(daddr));
1089 *
1090 */
1091 GET_CURRENT_PGD(r3,r5) // r3 is current_pgd, r5 is temp
1092 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1093 l.slli r4,r4,0x2 // to get address << 2
1094 l.add r5,r4,r3 // r4 is pgd_index(daddr)
1095 /*
1096 * if (pmd_none(*pmd))
1097 * goto pmd_none:
1098 */
1099 tophys (r4,r5)
1100 l.lwz r3,0x0(r4) // get *pmd value
1101 l.sfne r3,r0
1102 l.bnf i_pmd_none
1103 l.andi r3,r3,0x1fff // ~PAGE_MASK
1104 /*
1105 * if (pmd_bad(*pmd))
1106 * pmd_clear(pmd)
1107 * goto pmd_bad:
1108 */
1109
1110// l.sfeq r3,r0 // check *pmd value
1111// l.bf i_pmd_good
1112 l.addi r3,r0,0xffffe000 // PAGE_MASK
1113// l.j i_pmd_bad
1114// l.sw 0x0(r4),r0 // clear pmd
1115
1116i_pmd_good:
1117 /*
1118 * pte = *pte_offset(pmd, iaddr);
1119 *
1120 */
1121 l.lwz r4,0x0(r4) // get **pmd value
1122 l.and r4,r4,r3 // & PAGE_MASK
1123 l.srli r5,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
1124 l.andi r3,r5,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1125 l.slli r3,r3,0x2 // to get address << 2
1126 l.add r3,r3,r4
1127 l.lwz r2,0x0(r3) // this is pte at last
1128 /*
1129 * if (!pte_present(pte))
1130 *
1131 */
1132 l.andi r4,r2,0x1
1133 l.sfne r4,r0 // is pte present
1134 l.bnf i_pte_not_present
1135 l.addi r3,r0,0xffffe03a // PAGE_MASK | ITLB_UP_CONVERT_MASK
1136 /*
1137 * fill ITLB TR register
1138 */
1139 l.and r4,r2,r3 // apply the mask
1140 l.andi r3,r2,0x7c0 // _PAGE_EXEC | _PAGE_SRE | _PAGE_SWE | _PAGE_URE | _PAGE_UWE
1141// l.andi r3,r2,0x400 // _PAGE_EXEC
1142 l.sfeq r3,r0
1143 l.bf itlb_tr_fill //_workaround
1144 // Determine number of IMMU sets
1145 l.mfspr r6, r0, SPR_IMMUCFGR
1146 l.andi r6, r6, SPR_IMMUCFGR_NTS
1147 l.srli r6, r6, SPR_IMMUCFGR_NTS_OFF
1148 l.ori r3, r0, 0x1
1149 l.sll r3, r3, r6 // r3 = number IMMU sets IMMUCFGR
1150 l.addi r6, r3, -1 // r6 = nsets mask
1151 l.and r5, r5, r6 // calc offset: & (NUM_TLB_ENTRIES-1)
1152
1153/*
1154 * __PHX__ :: fixme
1155 * we should not just blindly set executable flags,
1156 * but it does help with ping. the clean way would be to find out
1157 * (and fix it) why stack doesn't have execution permissions
1158 */
1159
1160itlb_tr_fill_workaround:
1161 l.ori r4,r4,0xc0 // | (SPR_ITLBTR_UXE | ITLBTR_SXE)
1162itlb_tr_fill:
1163 l.mtspr r5,r4,SPR_ITLBTR_BASE(0)
1164 /*
1165 * fill DTLB MR register
1166 */
1167 l.mfspr r2,r0,SPR_EEAR_BASE
1168 l.addi r3,r0,0xffffe000 // PAGE_MASK
1169 l.and r4,r2,r3 // apply PAGE_MASK to EA (__PHX__ do we really need this?)
1170 l.ori r4,r4,0x1 // set hardware valid bit: DTBL_MR entry
1171 l.mtspr r5,r4,SPR_ITLBMR_BASE(0)
1172
1173 EXCEPTION_LOAD_GPR2
1174 EXCEPTION_LOAD_GPR3
1175 EXCEPTION_LOAD_GPR4
1176 EXCEPTION_LOAD_GPR5
1177 EXCEPTION_LOAD_GPR6
1178 l.rfe
1179
1180i_pmd_bad:
1181 l.nop 1
1182 EXCEPTION_LOAD_GPR2
1183 EXCEPTION_LOAD_GPR3
1184 EXCEPTION_LOAD_GPR4
1185 EXCEPTION_LOAD_GPR5
1186 EXCEPTION_LOAD_GPR6
1187 l.rfe
1188i_pmd_none:
1189i_pte_not_present:
1190 EXCEPTION_LOAD_GPR2
1191 EXCEPTION_LOAD_GPR3
1192 EXCEPTION_LOAD_GPR4
1193 EXCEPTION_LOAD_GPR5
1194 EXCEPTION_LOAD_GPR6
1195 l.j _dispatch_do_ipage_fault
1196 l.nop
1197
1198/* ==============================================[ boot tlb handlers ]=== */
1199
1200
1201/* =================================================[ debugging aids ]=== */
1202
1203 .align 64
1204_immu_trampoline:
1205 .space 64
1206_immu_trampoline_top:
1207
1208#define TRAMP_SLOT_0 (0x0)
1209#define TRAMP_SLOT_1 (0x4)
1210#define TRAMP_SLOT_2 (0x8)
1211#define TRAMP_SLOT_3 (0xc)
1212#define TRAMP_SLOT_4 (0x10)
1213#define TRAMP_SLOT_5 (0x14)
1214#define TRAMP_FRAME_SIZE (0x18)
1215
1216ENTRY(_immu_trampoline_workaround)
1217 // r2 EEA
1218 // r6 is physical EEA
1219 tophys(r6,r2)
1220
1221 LOAD_SYMBOL_2_GPR(r5,_immu_trampoline)
1222 tophys (r3,r5) // r3 is trampoline (physical)
1223
1224 LOAD_SYMBOL_2_GPR(r4,0x15000000)
1225 l.sw TRAMP_SLOT_0(r3),r4
1226 l.sw TRAMP_SLOT_1(r3),r4
1227 l.sw TRAMP_SLOT_4(r3),r4
1228 l.sw TRAMP_SLOT_5(r3),r4
1229
1230 // EPC = EEA - 0x4
1231 l.lwz r4,0x0(r6) // load op @ EEA + 0x0 (fc address)
1232 l.sw TRAMP_SLOT_3(r3),r4 // store it to _immu_trampoline_data
1233 l.lwz r4,-0x4(r6) // load op @ EEA - 0x4 (f8 address)
1234 l.sw TRAMP_SLOT_2(r3),r4 // store it to _immu_trampoline_data
1235
1236 l.srli r5,r4,26 // check opcode for write access
1237 l.sfeqi r5,0 // l.j
1238 l.bf 0f
1239 l.sfeqi r5,0x11 // l.jr
1240 l.bf 1f
1241 l.sfeqi r5,1 // l.jal
1242 l.bf 2f
1243 l.sfeqi r5,0x12 // l.jalr
1244 l.bf 3f
1245 l.sfeqi r5,3 // l.bnf
1246 l.bf 4f
1247 l.sfeqi r5,4 // l.bf
1248 l.bf 5f
124999:
1250 l.nop
1251 l.j 99b // should never happen
1252 l.nop 1
1253
1254 // r2 is EEA
1255 // r3 is trampoline address (physical)
1256 // r4 is instruction
1257 // r6 is physical(EEA)
1258 //
1259 // r5
1260
12612: // l.jal
1262
1263 /* 19 20 aa aa l.movhi r9,0xaaaa
1264 * a9 29 bb bb l.ori r9,0xbbbb
1265 *
1266 * where 0xaaaabbbb is EEA + 0x4 shifted right 2
1267 */
1268
1269 l.addi r6,r2,0x4 // this is 0xaaaabbbb
1270
1271 // l.movhi r9,0xaaaa
1272 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
1273 l.sh (TRAMP_SLOT_0+0x0)(r3),r5
1274 l.srli r5,r6,16
1275 l.sh (TRAMP_SLOT_0+0x2)(r3),r5
1276
1277 // l.ori r9,0xbbbb
1278 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
1279 l.sh (TRAMP_SLOT_1+0x0)(r3),r5
1280 l.andi r5,r6,0xffff
1281 l.sh (TRAMP_SLOT_1+0x2)(r3),r5
1282
1283 /* falthrough, need to set up new jump offset */
1284
1285
12860: // l.j
1287 l.slli r6,r4,6 // original offset shifted left 6 - 2
1288// l.srli r6,r6,6 // original offset shifted right 2
1289
1290 l.slli r4,r2,4 // old jump position: EEA shifted left 4
1291// l.srli r4,r4,6 // old jump position: shifted right 2
1292
1293 l.addi r5,r3,0xc // new jump position (physical)
1294 l.slli r5,r5,4 // new jump position: shifted left 4
1295
1296 // calculate new jump offset
1297 // new_off = old_off + (old_jump - new_jump)
1298
1299 l.sub r5,r4,r5 // old_jump - new_jump
1300 l.add r5,r6,r5 // orig_off + (old_jump - new_jump)
1301 l.srli r5,r5,6 // new offset shifted right 2
1302
1303 // r5 is new jump offset
1304 // l.j has opcode 0x0...
1305 l.sw TRAMP_SLOT_2(r3),r5 // write it back
1306
1307 l.j trampoline_out
1308 l.nop
1309
1310/* ----------------------------- */
1311
13123: // l.jalr
1313
1314 /* 19 20 aa aa l.movhi r9,0xaaaa
1315 * a9 29 bb bb l.ori r9,0xbbbb
1316 *
1317 * where 0xaaaabbbb is EEA + 0x4 shifted right 2
1318 */
1319
1320 l.addi r6,r2,0x4 // this is 0xaaaabbbb
1321
1322 // l.movhi r9,0xaaaa
1323 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
1324 l.sh (TRAMP_SLOT_0+0x0)(r3),r5
1325 l.srli r5,r6,16
1326 l.sh (TRAMP_SLOT_0+0x2)(r3),r5
1327
1328 // l.ori r9,0xbbbb
1329 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
1330 l.sh (TRAMP_SLOT_1+0x0)(r3),r5
1331 l.andi r5,r6,0xffff
1332 l.sh (TRAMP_SLOT_1+0x2)(r3),r5
1333
1334 l.lhz r5,(TRAMP_SLOT_2+0x0)(r3) // load hi part of jump instruction
1335 l.andi r5,r5,0x3ff // clear out opcode part
1336 l.ori r5,r5,0x4400 // opcode changed from l.jalr -> l.jr
1337 l.sh (TRAMP_SLOT_2+0x0)(r3),r5 // write it back
1338
1339 /* falthrough */
1340
13411: // l.jr
1342 l.j trampoline_out
1343 l.nop
1344
1345/* ----------------------------- */
1346
13474: // l.bnf
13485: // l.bf
1349 l.slli r6,r4,6 // original offset shifted left 6 - 2
1350// l.srli r6,r6,6 // original offset shifted right 2
1351
1352 l.slli r4,r2,4 // old jump position: EEA shifted left 4
1353// l.srli r4,r4,6 // old jump position: shifted right 2
1354
1355 l.addi r5,r3,0xc // new jump position (physical)
1356 l.slli r5,r5,4 // new jump position: shifted left 4
1357
1358 // calculate new jump offset
1359 // new_off = old_off + (old_jump - new_jump)
1360
1361 l.add r6,r6,r4 // (orig_off + old_jump)
1362 l.sub r6,r6,r5 // (orig_off + old_jump) - new_jump
1363 l.srli r6,r6,6 // new offset shifted right 2
1364
1365 // r6 is new jump offset
1366 l.lwz r4,(TRAMP_SLOT_2+0x0)(r3) // load jump instruction
1367 l.srli r4,r4,16
1368 l.andi r4,r4,0xfc00 // get opcode part
1369 l.slli r4,r4,16
1370 l.or r6,r4,r6 // l.b(n)f new offset
1371 l.sw TRAMP_SLOT_2(r3),r6 // write it back
1372
1373 /* we need to add l.j to EEA + 0x8 */
1374 tophys (r4,r2) // may not be needed (due to shifts down_
1375 l.addi r4,r4,(0x8 - 0x8) // jump target = r2 + 0x8 (compensate for 0x8)
1376 // jump position = r5 + 0x8 (0x8 compensated)
1377 l.sub r4,r4,r5 // jump offset = target - new_position + 0x8
1378
1379 l.slli r4,r4,4 // the amount of info in imediate of jump
1380 l.srli r4,r4,6 // jump instruction with offset
1381 l.sw TRAMP_SLOT_4(r3),r4 // write it to 4th slot
1382
1383 /* fallthrough */
1384
1385trampoline_out:
1386 // set up new EPC to point to our trampoline code
1387 LOAD_SYMBOL_2_GPR(r5,_immu_trampoline)
1388 l.mtspr r0,r5,SPR_EPCR_BASE
1389
1390 // immu_trampoline is (4x) CACHE_LINE aligned
1391 // and only 6 instructions long,
1392 // so we need to invalidate only 2 lines
1393
1394 /* Establish cache block size
1395 If BS=0, 16;
1396 If BS=1, 32;
1397 r14 contain block size
1398 */
1399 l.mfspr r21,r0,SPR_ICCFGR
1400 l.andi r21,r21,SPR_ICCFGR_CBS
1401 l.srli r21,r21,7
1402 l.ori r23,r0,16
1403 l.sll r14,r23,r21
1404
1405 l.mtspr r0,r5,SPR_ICBIR
1406 l.add r5,r5,r14
1407 l.mtspr r0,r5,SPR_ICBIR
1408
1409 l.jr r9
1410 l.nop
1411
1412
1413/*
1414 * DSCR: prints a string referenced by r3.
1415 *
1416 * PRMS: r3 - address of the first character of null
1417 * terminated string to be printed
1418 *
1419 * PREQ: UART at UART_BASE_ADD has to be initialized
1420 *
1421 * POST: caller should be aware that r3, r9 are changed
1422 */
1423ENTRY(_emergency_print)
1424 EMERGENCY_PRINT_STORE_GPR4
1425 EMERGENCY_PRINT_STORE_GPR5
1426 EMERGENCY_PRINT_STORE_GPR6
1427 EMERGENCY_PRINT_STORE_GPR7
14282:
1429 l.lbz r7,0(r3)
1430 l.sfeq r7,r0
1431 l.bf 9f
1432 l.nop
1433
1434// putc:
1435 l.movhi r4,hi(UART_BASE_ADD)
1436
1437 l.addi r6,r0,0x20
14381: l.lbz r5,5(r4)
1439 l.andi r5,r5,0x20
1440 l.sfeq r5,r6
1441 l.bnf 1b
1442 l.nop
1443
1444 l.sb 0(r4),r7
1445
1446 l.addi r6,r0,0x60
14471: l.lbz r5,5(r4)
1448 l.andi r5,r5,0x60
1449 l.sfeq r5,r6
1450 l.bnf 1b
1451 l.nop
1452
1453 /* next character */
1454 l.j 2b
1455 l.addi r3,r3,0x1
1456
14579:
1458 EMERGENCY_PRINT_LOAD_GPR7
1459 EMERGENCY_PRINT_LOAD_GPR6
1460 EMERGENCY_PRINT_LOAD_GPR5
1461 EMERGENCY_PRINT_LOAD_GPR4
1462 l.jr r9
1463 l.nop
1464
1465ENTRY(_emergency_print_nr)
1466 EMERGENCY_PRINT_STORE_GPR4
1467 EMERGENCY_PRINT_STORE_GPR5
1468 EMERGENCY_PRINT_STORE_GPR6
1469 EMERGENCY_PRINT_STORE_GPR7
1470 EMERGENCY_PRINT_STORE_GPR8
1471
1472 l.addi r8,r0,32 // shift register
1473
14741: /* remove leading zeros */
1475 l.addi r8,r8,-0x4
1476 l.srl r7,r3,r8
1477 l.andi r7,r7,0xf
1478
1479 /* don't skip the last zero if number == 0x0 */
1480 l.sfeqi r8,0x4
1481 l.bf 2f
1482 l.nop
1483
1484 l.sfeq r7,r0
1485 l.bf 1b
1486 l.nop
1487
14882:
1489 l.srl r7,r3,r8
1490
1491 l.andi r7,r7,0xf
1492 l.sflts r8,r0
1493 l.bf 9f
1494
1495 l.sfgtui r7,0x9
1496 l.bnf 8f
1497 l.nop
1498 l.addi r7,r7,0x27
1499
15008:
1501 l.addi r7,r7,0x30
1502// putc:
1503 l.movhi r4,hi(UART_BASE_ADD)
1504
1505 l.addi r6,r0,0x20
15061: l.lbz r5,5(r4)
1507 l.andi r5,r5,0x20
1508 l.sfeq r5,r6
1509 l.bnf 1b
1510 l.nop
1511
1512 l.sb 0(r4),r7
1513
1514 l.addi r6,r0,0x60
15151: l.lbz r5,5(r4)
1516 l.andi r5,r5,0x60
1517 l.sfeq r5,r6
1518 l.bnf 1b
1519 l.nop
1520
1521 /* next character */
1522 l.j 2b
1523 l.addi r8,r8,-0x4
1524
15259:
1526 EMERGENCY_PRINT_LOAD_GPR8
1527 EMERGENCY_PRINT_LOAD_GPR7
1528 EMERGENCY_PRINT_LOAD_GPR6
1529 EMERGENCY_PRINT_LOAD_GPR5
1530 EMERGENCY_PRINT_LOAD_GPR4
1531 l.jr r9
1532 l.nop
1533
1534
1535/*
1536 * This should be used for debugging only.
1537 * It messes up the Linux early serial output
1538 * somehow, so use it sparingly and essentially
1539 * only if you need to debug something that goes wrong
1540 * before Linux gets the early serial going.
1541 *
1542 * Furthermore, you'll have to make sure you set the
1543 * UART_DEVISOR correctly according to the system
1544 * clock rate.
1545 *
1546 *
1547 */
1548
1549
1550
1551#define SYS_CLK 20000000
1552//#define SYS_CLK 1843200
1553#define OR32_CONSOLE_BAUD 115200
1554#define UART_DIVISOR SYS_CLK/(16*OR32_CONSOLE_BAUD)
1555
1556ENTRY(_early_uart_init)
1557 l.movhi r3,hi(UART_BASE_ADD)
1558
1559 l.addi r4,r0,0x7
1560 l.sb 0x2(r3),r4
1561
1562 l.addi r4,r0,0x0
1563 l.sb 0x1(r3),r4
1564
1565 l.addi r4,r0,0x3
1566 l.sb 0x3(r3),r4
1567
1568 l.lbz r5,3(r3)
1569 l.ori r4,r5,0x80
1570 l.sb 0x3(r3),r4
1571 l.addi r4,r0,((UART_DIVISOR>>8) & 0x000000ff)
1572 l.sb UART_DLM(r3),r4
1573 l.addi r4,r0,((UART_DIVISOR) & 0x000000ff)
1574 l.sb UART_DLL(r3),r4
1575 l.sb 0x3(r3),r5
1576
1577 l.jr r9
1578 l.nop
1579
1580_string_copying_linux:
1581 .string "\n\n\n\n\n\rCopying Linux... \0"
1582
1583_string_ok_booting:
1584 .string "Ok, booting the kernel.\n\r\0"
1585
1586_string_unhandled_exception:
1587 .string "\n\rRunarunaround: Unhandled exception 0x\0"
1588
1589_string_epc_prefix:
1590 .string ": EPC=0x\0"
1591
1592_string_nl:
1593 .string "\n\r\0"
1594
1595 .global _string_esr_irq_bug
1596_string_esr_irq_bug:
1597 .string "\n\rESR external interrupt bug, for details look into entry.S\n\r\0"
1598
1599
1600
1601/* ========================================[ page aligned structures ]=== */
1602
1603/*
1604 * .data section should be page aligned
1605 * (look into arch/or32/kernel/vmlinux.lds)
1606 */
1607 .section .data,"aw"
1608 .align 8192
1609 .global empty_zero_page
1610empty_zero_page:
1611 .space 8192
1612
1613 .global swapper_pg_dir
1614swapper_pg_dir:
1615 .space 8192
1616
1617 .global _unhandled_stack
1618_unhandled_stack:
1619 .space 8192
1620_unhandled_stack_top:
1621
1622/* ============================================================[ EOF ]=== */
1/*
2 * OpenRISC head.S
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * Modifications for the OpenRISC architecture:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
16 */
17
18#include <linux/linkage.h>
19#include <linux/threads.h>
20#include <linux/errno.h>
21#include <linux/init.h>
22#include <linux/serial_reg.h>
23#include <asm/processor.h>
24#include <asm/page.h>
25#include <asm/mmu.h>
26#include <asm/pgtable.h>
27#include <asm/cache.h>
28#include <asm/spr_defs.h>
29#include <asm/asm-offsets.h>
30#include <linux/of_fdt.h>
31
32#define tophys(rd,rs) \
33 l.movhi rd,hi(-KERNELBASE) ;\
34 l.add rd,rd,rs
35
36#define CLEAR_GPR(gpr) \
37 l.or gpr,r0,r0
38
39#define LOAD_SYMBOL_2_GPR(gpr,symbol) \
40 l.movhi gpr,hi(symbol) ;\
41 l.ori gpr,gpr,lo(symbol)
42
43
44#define UART_BASE_ADD 0x90000000
45
46#define EXCEPTION_SR (SPR_SR_DME | SPR_SR_IME | SPR_SR_DCE | SPR_SR_ICE | SPR_SR_SM)
47#define SYSCALL_SR (SPR_SR_DME | SPR_SR_IME | SPR_SR_DCE | SPR_SR_ICE | SPR_SR_IEE | SPR_SR_TEE | SPR_SR_SM)
48
49/* ============================================[ tmp store locations ]=== */
50
51/*
52 * emergency_print temporary stores
53 */
54#define EMERGENCY_PRINT_STORE_GPR4 l.sw 0x20(r0),r4
55#define EMERGENCY_PRINT_LOAD_GPR4 l.lwz r4,0x20(r0)
56
57#define EMERGENCY_PRINT_STORE_GPR5 l.sw 0x24(r0),r5
58#define EMERGENCY_PRINT_LOAD_GPR5 l.lwz r5,0x24(r0)
59
60#define EMERGENCY_PRINT_STORE_GPR6 l.sw 0x28(r0),r6
61#define EMERGENCY_PRINT_LOAD_GPR6 l.lwz r6,0x28(r0)
62
63#define EMERGENCY_PRINT_STORE_GPR7 l.sw 0x2c(r0),r7
64#define EMERGENCY_PRINT_LOAD_GPR7 l.lwz r7,0x2c(r0)
65
66#define EMERGENCY_PRINT_STORE_GPR8 l.sw 0x30(r0),r8
67#define EMERGENCY_PRINT_LOAD_GPR8 l.lwz r8,0x30(r0)
68
69#define EMERGENCY_PRINT_STORE_GPR9 l.sw 0x34(r0),r9
70#define EMERGENCY_PRINT_LOAD_GPR9 l.lwz r9,0x34(r0)
71
72
73/*
74 * TLB miss handlers temorary stores
75 */
76#define EXCEPTION_STORE_GPR9 l.sw 0x10(r0),r9
77#define EXCEPTION_LOAD_GPR9 l.lwz r9,0x10(r0)
78
79#define EXCEPTION_STORE_GPR2 l.sw 0x64(r0),r2
80#define EXCEPTION_LOAD_GPR2 l.lwz r2,0x64(r0)
81
82#define EXCEPTION_STORE_GPR3 l.sw 0x68(r0),r3
83#define EXCEPTION_LOAD_GPR3 l.lwz r3,0x68(r0)
84
85#define EXCEPTION_STORE_GPR4 l.sw 0x6c(r0),r4
86#define EXCEPTION_LOAD_GPR4 l.lwz r4,0x6c(r0)
87
88#define EXCEPTION_STORE_GPR5 l.sw 0x70(r0),r5
89#define EXCEPTION_LOAD_GPR5 l.lwz r5,0x70(r0)
90
91#define EXCEPTION_STORE_GPR6 l.sw 0x74(r0),r6
92#define EXCEPTION_LOAD_GPR6 l.lwz r6,0x74(r0)
93
94
95/*
96 * EXCEPTION_HANDLE temporary stores
97 */
98
99#define EXCEPTION_T_STORE_GPR30 l.sw 0x78(r0),r30
100#define EXCEPTION_T_LOAD_GPR30(reg) l.lwz reg,0x78(r0)
101
102#define EXCEPTION_T_STORE_GPR10 l.sw 0x7c(r0),r10
103#define EXCEPTION_T_LOAD_GPR10(reg) l.lwz reg,0x7c(r0)
104
105#define EXCEPTION_T_STORE_SP l.sw 0x80(r0),r1
106#define EXCEPTION_T_LOAD_SP(reg) l.lwz reg,0x80(r0)
107
108/*
109 * For UNHANLDED_EXCEPTION
110 */
111
112#define EXCEPTION_T_STORE_GPR31 l.sw 0x84(r0),r31
113#define EXCEPTION_T_LOAD_GPR31(reg) l.lwz reg,0x84(r0)
114
115/* =========================================================[ macros ]=== */
116
117
118#define GET_CURRENT_PGD(reg,t1) \
119 LOAD_SYMBOL_2_GPR(reg,current_pgd) ;\
120 tophys (t1,reg) ;\
121 l.lwz reg,0(t1)
122
123
124/*
125 * DSCR: this is a common hook for handling exceptions. it will save
126 * the needed registers, set up stack and pointer to current
127 * then jump to the handler while enabling MMU
128 *
129 * PRMS: handler - a function to jump to. it has to save the
130 * remaining registers to kernel stack, call
131 * appropriate arch-independant exception handler
132 * and finaly jump to ret_from_except
133 *
134 * PREQ: unchanged state from the time exception happened
135 *
136 * POST: SAVED the following registers original value
137 * to the new created exception frame pointed to by r1
138 *
139 * r1 - ksp pointing to the new (exception) frame
140 * r4 - EEAR exception EA
141 * r10 - current pointing to current_thread_info struct
142 * r12 - syscall 0, since we didn't come from syscall
143 * r13 - temp it actually contains new SR, not needed anymore
144 * r31 - handler address of the handler we'll jump to
145 *
146 * handler has to save remaining registers to the exception
147 * ksp frame *before* tainting them!
148 *
149 * NOTE: this function is not reentrant per se. reentrancy is guaranteed
150 * by processor disabling all exceptions/interrupts when exception
151 * accours.
152 *
153 * OPTM: no need to make it so wasteful to extract ksp when in user mode
154 */
155
156#define EXCEPTION_HANDLE(handler) \
157 EXCEPTION_T_STORE_GPR30 ;\
158 l.mfspr r30,r0,SPR_ESR_BASE ;\
159 l.andi r30,r30,SPR_SR_SM ;\
160 l.sfeqi r30,0 ;\
161 EXCEPTION_T_STORE_GPR10 ;\
162 l.bnf 2f /* kernel_mode */ ;\
163 EXCEPTION_T_STORE_SP /* delay slot */ ;\
1641: /* user_mode: */ ;\
165 LOAD_SYMBOL_2_GPR(r1,current_thread_info_set) ;\
166 tophys (r30,r1) ;\
167 /* r10: current_thread_info */ ;\
168 l.lwz r10,0(r30) ;\
169 tophys (r30,r10) ;\
170 l.lwz r1,(TI_KSP)(r30) ;\
171 /* fall through */ ;\
1722: /* kernel_mode: */ ;\
173 /* create new stack frame, save only needed gprs */ ;\
174 /* r1: KSP, r10: current, r4: EEAR, r31: __pa(KSP) */ ;\
175 /* r12: temp, syscall indicator */ ;\
176 l.addi r1,r1,-(INT_FRAME_SIZE) ;\
177 /* r1 is KSP, r30 is __pa(KSP) */ ;\
178 tophys (r30,r1) ;\
179 l.sw PT_GPR12(r30),r12 ;\
180 l.mfspr r12,r0,SPR_EPCR_BASE ;\
181 l.sw PT_PC(r30),r12 ;\
182 l.mfspr r12,r0,SPR_ESR_BASE ;\
183 l.sw PT_SR(r30),r12 ;\
184 /* save r30 */ ;\
185 EXCEPTION_T_LOAD_GPR30(r12) ;\
186 l.sw PT_GPR30(r30),r12 ;\
187 /* save r10 as was prior to exception */ ;\
188 EXCEPTION_T_LOAD_GPR10(r12) ;\
189 l.sw PT_GPR10(r30),r12 ;\
190 /* save PT_SP as was prior to exception */ ;\
191 EXCEPTION_T_LOAD_SP(r12) ;\
192 l.sw PT_SP(r30),r12 ;\
193 /* save exception r4, set r4 = EA */ ;\
194 l.sw PT_GPR4(r30),r4 ;\
195 l.mfspr r4,r0,SPR_EEAR_BASE ;\
196 /* r12 == 1 if we come from syscall */ ;\
197 CLEAR_GPR(r12) ;\
198 /* ----- turn on MMU ----- */ ;\
199 l.ori r30,r0,(EXCEPTION_SR) ;\
200 l.mtspr r0,r30,SPR_ESR_BASE ;\
201 /* r30: EA address of handler */ ;\
202 LOAD_SYMBOL_2_GPR(r30,handler) ;\
203 l.mtspr r0,r30,SPR_EPCR_BASE ;\
204 l.rfe
205
206/*
207 * this doesn't work
208 *
209 *
210 * #ifdef CONFIG_JUMP_UPON_UNHANDLED_EXCEPTION
211 * #define UNHANDLED_EXCEPTION(handler) \
212 * l.ori r3,r0,0x1 ;\
213 * l.mtspr r0,r3,SPR_SR ;\
214 * l.movhi r3,hi(0xf0000100) ;\
215 * l.ori r3,r3,lo(0xf0000100) ;\
216 * l.jr r3 ;\
217 * l.nop 1
218 *
219 * #endif
220 */
221
222/* DSCR: this is the same as EXCEPTION_HANDLE(), we are just
223 * a bit more carefull (if we have a PT_SP or current pointer
224 * corruption) and set them up from 'current_set'
225 *
226 */
227#define UNHANDLED_EXCEPTION(handler) \
228 EXCEPTION_T_STORE_GPR31 ;\
229 EXCEPTION_T_STORE_GPR10 ;\
230 EXCEPTION_T_STORE_SP ;\
231 /* temporary store r3, r9 into r1, r10 */ ;\
232 l.addi r1,r3,0x0 ;\
233 l.addi r10,r9,0x0 ;\
234 /* the string referenced by r3 must be low enough */ ;\
235 l.jal _emergency_print ;\
236 l.ori r3,r0,lo(_string_unhandled_exception) ;\
237 l.mfspr r3,r0,SPR_NPC ;\
238 l.jal _emergency_print_nr ;\
239 l.andi r3,r3,0x1f00 ;\
240 /* the string referenced by r3 must be low enough */ ;\
241 l.jal _emergency_print ;\
242 l.ori r3,r0,lo(_string_epc_prefix) ;\
243 l.jal _emergency_print_nr ;\
244 l.mfspr r3,r0,SPR_EPCR_BASE ;\
245 l.jal _emergency_print ;\
246 l.ori r3,r0,lo(_string_nl) ;\
247 /* end of printing */ ;\
248 l.addi r3,r1,0x0 ;\
249 l.addi r9,r10,0x0 ;\
250 /* extract current, ksp from current_set */ ;\
251 LOAD_SYMBOL_2_GPR(r1,_unhandled_stack_top) ;\
252 LOAD_SYMBOL_2_GPR(r10,init_thread_union) ;\
253 /* create new stack frame, save only needed gprs */ ;\
254 /* r1: KSP, r10: current, r31: __pa(KSP) */ ;\
255 /* r12: temp, syscall indicator, r13 temp */ ;\
256 l.addi r1,r1,-(INT_FRAME_SIZE) ;\
257 /* r1 is KSP, r31 is __pa(KSP) */ ;\
258 tophys (r31,r1) ;\
259 l.sw PT_GPR12(r31),r12 ;\
260 l.mfspr r12,r0,SPR_EPCR_BASE ;\
261 l.sw PT_PC(r31),r12 ;\
262 l.mfspr r12,r0,SPR_ESR_BASE ;\
263 l.sw PT_SR(r31),r12 ;\
264 /* save r31 */ ;\
265 EXCEPTION_T_LOAD_GPR31(r12) ;\
266 l.sw PT_GPR31(r31),r12 ;\
267 /* save r10 as was prior to exception */ ;\
268 EXCEPTION_T_LOAD_GPR10(r12) ;\
269 l.sw PT_GPR10(r31),r12 ;\
270 /* save PT_SP as was prior to exception */ ;\
271 EXCEPTION_T_LOAD_SP(r12) ;\
272 l.sw PT_SP(r31),r12 ;\
273 l.sw PT_GPR13(r31),r13 ;\
274 /* --> */ ;\
275 /* save exception r4, set r4 = EA */ ;\
276 l.sw PT_GPR4(r31),r4 ;\
277 l.mfspr r4,r0,SPR_EEAR_BASE ;\
278 /* r12 == 1 if we come from syscall */ ;\
279 CLEAR_GPR(r12) ;\
280 /* ----- play a MMU trick ----- */ ;\
281 l.ori r31,r0,(EXCEPTION_SR) ;\
282 l.mtspr r0,r31,SPR_ESR_BASE ;\
283 /* r31: EA address of handler */ ;\
284 LOAD_SYMBOL_2_GPR(r31,handler) ;\
285 l.mtspr r0,r31,SPR_EPCR_BASE ;\
286 l.rfe
287
288/* =====================================================[ exceptions] === */
289
290/* ---[ 0x100: RESET exception ]----------------------------------------- */
291 .org 0x100
292 /* Jump to .init code at _start which lives in the .head section
293 * and will be discarded after boot.
294 */
295 LOAD_SYMBOL_2_GPR(r15, _start)
296 tophys (r13,r15) /* MMU disabled */
297 l.jr r13
298 l.nop
299
300/* ---[ 0x200: BUS exception ]------------------------------------------- */
301 .org 0x200
302_dispatch_bus_fault:
303 EXCEPTION_HANDLE(_bus_fault_handler)
304
305/* ---[ 0x300: Data Page Fault exception ]------------------------------- */
306 .org 0x300
307_dispatch_do_dpage_fault:
308// totaly disable timer interrupt
309// l.mtspr r0,r0,SPR_TTMR
310// DEBUG_TLB_PROBE(0x300)
311// EXCEPTION_DEBUG_VALUE_ER_ENABLED(0x300)
312 EXCEPTION_HANDLE(_data_page_fault_handler)
313
314/* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
315 .org 0x400
316_dispatch_do_ipage_fault:
317// totaly disable timer interrupt
318// l.mtspr r0,r0,SPR_TTMR
319// DEBUG_TLB_PROBE(0x400)
320// EXCEPTION_DEBUG_VALUE_ER_ENABLED(0x400)
321 EXCEPTION_HANDLE(_insn_page_fault_handler)
322
323/* ---[ 0x500: Timer exception ]----------------------------------------- */
324 .org 0x500
325 EXCEPTION_HANDLE(_timer_handler)
326
327/* ---[ 0x600: Aligment exception ]-------------------------------------- */
328 .org 0x600
329 EXCEPTION_HANDLE(_alignment_handler)
330
331/* ---[ 0x700: Illegal insn exception ]---------------------------------- */
332 .org 0x700
333 EXCEPTION_HANDLE(_illegal_instruction_handler)
334
335/* ---[ 0x800: External interrupt exception ]---------------------------- */
336 .org 0x800
337 EXCEPTION_HANDLE(_external_irq_handler)
338
339/* ---[ 0x900: DTLB miss exception ]------------------------------------- */
340 .org 0x900
341 l.j boot_dtlb_miss_handler
342 l.nop
343
344/* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
345 .org 0xa00
346 l.j boot_itlb_miss_handler
347 l.nop
348
349/* ---[ 0xb00: Range exception ]----------------------------------------- */
350 .org 0xb00
351 UNHANDLED_EXCEPTION(_vector_0xb00)
352
353/* ---[ 0xc00: Syscall exception ]--------------------------------------- */
354 .org 0xc00
355 EXCEPTION_HANDLE(_sys_call_handler)
356
357/* ---[ 0xd00: Trap exception ]------------------------------------------ */
358 .org 0xd00
359 UNHANDLED_EXCEPTION(_vector_0xd00)
360
361/* ---[ 0xe00: Trap exception ]------------------------------------------ */
362 .org 0xe00
363// UNHANDLED_EXCEPTION(_vector_0xe00)
364 EXCEPTION_HANDLE(_trap_handler)
365
366/* ---[ 0xf00: Reserved exception ]-------------------------------------- */
367 .org 0xf00
368 UNHANDLED_EXCEPTION(_vector_0xf00)
369
370/* ---[ 0x1000: Reserved exception ]------------------------------------- */
371 .org 0x1000
372 UNHANDLED_EXCEPTION(_vector_0x1000)
373
374/* ---[ 0x1100: Reserved exception ]------------------------------------- */
375 .org 0x1100
376 UNHANDLED_EXCEPTION(_vector_0x1100)
377
378/* ---[ 0x1200: Reserved exception ]------------------------------------- */
379 .org 0x1200
380 UNHANDLED_EXCEPTION(_vector_0x1200)
381
382/* ---[ 0x1300: Reserved exception ]------------------------------------- */
383 .org 0x1300
384 UNHANDLED_EXCEPTION(_vector_0x1300)
385
386/* ---[ 0x1400: Reserved exception ]------------------------------------- */
387 .org 0x1400
388 UNHANDLED_EXCEPTION(_vector_0x1400)
389
390/* ---[ 0x1500: Reserved exception ]------------------------------------- */
391 .org 0x1500
392 UNHANDLED_EXCEPTION(_vector_0x1500)
393
394/* ---[ 0x1600: Reserved exception ]------------------------------------- */
395 .org 0x1600
396 UNHANDLED_EXCEPTION(_vector_0x1600)
397
398/* ---[ 0x1700: Reserved exception ]------------------------------------- */
399 .org 0x1700
400 UNHANDLED_EXCEPTION(_vector_0x1700)
401
402/* ---[ 0x1800: Reserved exception ]------------------------------------- */
403 .org 0x1800
404 UNHANDLED_EXCEPTION(_vector_0x1800)
405
406/* ---[ 0x1900: Reserved exception ]------------------------------------- */
407 .org 0x1900
408 UNHANDLED_EXCEPTION(_vector_0x1900)
409
410/* ---[ 0x1a00: Reserved exception ]------------------------------------- */
411 .org 0x1a00
412 UNHANDLED_EXCEPTION(_vector_0x1a00)
413
414/* ---[ 0x1b00: Reserved exception ]------------------------------------- */
415 .org 0x1b00
416 UNHANDLED_EXCEPTION(_vector_0x1b00)
417
418/* ---[ 0x1c00: Reserved exception ]------------------------------------- */
419 .org 0x1c00
420 UNHANDLED_EXCEPTION(_vector_0x1c00)
421
422/* ---[ 0x1d00: Reserved exception ]------------------------------------- */
423 .org 0x1d00
424 UNHANDLED_EXCEPTION(_vector_0x1d00)
425
426/* ---[ 0x1e00: Reserved exception ]------------------------------------- */
427 .org 0x1e00
428 UNHANDLED_EXCEPTION(_vector_0x1e00)
429
430/* ---[ 0x1f00: Reserved exception ]------------------------------------- */
431 .org 0x1f00
432 UNHANDLED_EXCEPTION(_vector_0x1f00)
433
434 .org 0x2000
435/* ===================================================[ kernel start ]=== */
436
437/* .text*/
438
439/* This early stuff belongs in HEAD, but some of the functions below definitely
440 * don't... */
441
442 __HEAD
443 .global _start
444_start:
445 /* save kernel parameters */
446 l.or r25,r0,r3 /* pointer to fdt */
447
448 /*
449 * ensure a deterministic start
450 */
451
452 l.ori r3,r0,0x1
453 l.mtspr r0,r3,SPR_SR
454
455 CLEAR_GPR(r1)
456 CLEAR_GPR(r2)
457 CLEAR_GPR(r3)
458 CLEAR_GPR(r4)
459 CLEAR_GPR(r5)
460 CLEAR_GPR(r6)
461 CLEAR_GPR(r7)
462 CLEAR_GPR(r8)
463 CLEAR_GPR(r9)
464 CLEAR_GPR(r10)
465 CLEAR_GPR(r11)
466 CLEAR_GPR(r12)
467 CLEAR_GPR(r13)
468 CLEAR_GPR(r14)
469 CLEAR_GPR(r15)
470 CLEAR_GPR(r16)
471 CLEAR_GPR(r17)
472 CLEAR_GPR(r18)
473 CLEAR_GPR(r19)
474 CLEAR_GPR(r20)
475 CLEAR_GPR(r21)
476 CLEAR_GPR(r22)
477 CLEAR_GPR(r23)
478 CLEAR_GPR(r24)
479 CLEAR_GPR(r26)
480 CLEAR_GPR(r27)
481 CLEAR_GPR(r28)
482 CLEAR_GPR(r29)
483 CLEAR_GPR(r30)
484 CLEAR_GPR(r31)
485
486 /*
487 * set up initial ksp and current
488 */
489 LOAD_SYMBOL_2_GPR(r1,init_thread_union+0x2000) // setup kernel stack
490 LOAD_SYMBOL_2_GPR(r10,init_thread_union) // setup current
491 tophys (r31,r10)
492 l.sw TI_KSP(r31), r1
493
494 l.ori r4,r0,0x0
495
496
497 /*
498 * .data contains initialized data,
499 * .bss contains uninitialized data - clear it up
500 */
501clear_bss:
502 LOAD_SYMBOL_2_GPR(r24, __bss_start)
503 LOAD_SYMBOL_2_GPR(r26, _end)
504 tophys(r28,r24)
505 tophys(r30,r26)
506 CLEAR_GPR(r24)
507 CLEAR_GPR(r26)
5081:
509 l.sw (0)(r28),r0
510 l.sfltu r28,r30
511 l.bf 1b
512 l.addi r28,r28,4
513
514enable_ic:
515 l.jal _ic_enable
516 l.nop
517
518enable_dc:
519 l.jal _dc_enable
520 l.nop
521
522flush_tlb:
523 /*
524 * I N V A L I D A T E T L B e n t r i e s
525 */
526 LOAD_SYMBOL_2_GPR(r5,SPR_DTLBMR_BASE(0))
527 LOAD_SYMBOL_2_GPR(r6,SPR_ITLBMR_BASE(0))
528 l.addi r7,r0,128 /* Maximum number of sets */
5291:
530 l.mtspr r5,r0,0x0
531 l.mtspr r6,r0,0x0
532
533 l.addi r5,r5,1
534 l.addi r6,r6,1
535 l.sfeq r7,r0
536 l.bnf 1b
537 l.addi r7,r7,-1
538
539
540/* The MMU needs to be enabled before or32_early_setup is called */
541
542enable_mmu:
543 /*
544 * enable dmmu & immu
545 * SR[5] = 0, SR[6] = 0, 6th and 7th bit of SR set to 0
546 */
547 l.mfspr r30,r0,SPR_SR
548 l.movhi r28,hi(SPR_SR_DME | SPR_SR_IME)
549 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
550 l.or r30,r30,r28
551 l.mtspr r0,r30,SPR_SR
552 l.nop
553 l.nop
554 l.nop
555 l.nop
556 l.nop
557 l.nop
558 l.nop
559 l.nop
560 l.nop
561 l.nop
562 l.nop
563 l.nop
564 l.nop
565 l.nop
566 l.nop
567 l.nop
568
569 // reset the simulation counters
570 l.nop 5
571
572 /* check fdt header magic word */
573 l.lwz r3,0(r25) /* load magic from fdt into r3 */
574 l.movhi r4,hi(OF_DT_HEADER)
575 l.ori r4,r4,lo(OF_DT_HEADER)
576 l.sfeq r3,r4
577 l.bf _fdt_found
578 l.nop
579 /* magic number mismatch, set fdt pointer to null */
580 l.or r25,r0,r0
581_fdt_found:
582 /* pass fdt pointer to or32_early_setup in r3 */
583 l.or r3,r0,r25
584 LOAD_SYMBOL_2_GPR(r24, or32_early_setup)
585 l.jalr r24
586 l.nop
587
588clear_regs:
589 /*
590 * clear all GPRS to increase determinism
591 */
592 CLEAR_GPR(r2)
593 CLEAR_GPR(r3)
594 CLEAR_GPR(r4)
595 CLEAR_GPR(r5)
596 CLEAR_GPR(r6)
597 CLEAR_GPR(r7)
598 CLEAR_GPR(r8)
599 CLEAR_GPR(r9)
600 CLEAR_GPR(r11)
601 CLEAR_GPR(r12)
602 CLEAR_GPR(r13)
603 CLEAR_GPR(r14)
604 CLEAR_GPR(r15)
605 CLEAR_GPR(r16)
606 CLEAR_GPR(r17)
607 CLEAR_GPR(r18)
608 CLEAR_GPR(r19)
609 CLEAR_GPR(r20)
610 CLEAR_GPR(r21)
611 CLEAR_GPR(r22)
612 CLEAR_GPR(r23)
613 CLEAR_GPR(r24)
614 CLEAR_GPR(r25)
615 CLEAR_GPR(r26)
616 CLEAR_GPR(r27)
617 CLEAR_GPR(r28)
618 CLEAR_GPR(r29)
619 CLEAR_GPR(r30)
620 CLEAR_GPR(r31)
621
622jump_start_kernel:
623 /*
624 * jump to kernel entry (start_kernel)
625 */
626 LOAD_SYMBOL_2_GPR(r30, start_kernel)
627 l.jr r30
628 l.nop
629
630/* ========================================[ cache ]=== */
631
632 /* aligment here so we don't change memory offsets with
633 * memory controler defined
634 */
635 .align 0x2000
636
637_ic_enable:
638 /* Check if IC present and skip enabling otherwise */
639 l.mfspr r24,r0,SPR_UPR
640 l.andi r26,r24,SPR_UPR_ICP
641 l.sfeq r26,r0
642 l.bf 9f
643 l.nop
644
645 /* Disable IC */
646 l.mfspr r6,r0,SPR_SR
647 l.addi r5,r0,-1
648 l.xori r5,r5,SPR_SR_ICE
649 l.and r5,r6,r5
650 l.mtspr r0,r5,SPR_SR
651
652 /* Establish cache block size
653 If BS=0, 16;
654 If BS=1, 32;
655 r14 contain block size
656 */
657 l.mfspr r24,r0,SPR_ICCFGR
658 l.andi r26,r24,SPR_ICCFGR_CBS
659 l.srli r28,r26,7
660 l.ori r30,r0,16
661 l.sll r14,r30,r28
662
663 /* Establish number of cache sets
664 r16 contains number of cache sets
665 r28 contains log(# of cache sets)
666 */
667 l.andi r26,r24,SPR_ICCFGR_NCS
668 l.srli r28,r26,3
669 l.ori r30,r0,1
670 l.sll r16,r30,r28
671
672 /* Invalidate IC */
673 l.addi r6,r0,0
674 l.sll r5,r14,r28
675// l.mul r5,r14,r16
676// l.trap 1
677// l.addi r5,r0,IC_SIZE
6781:
679 l.mtspr r0,r6,SPR_ICBIR
680 l.sfne r6,r5
681 l.bf 1b
682 l.add r6,r6,r14
683 // l.addi r6,r6,IC_LINE
684
685 /* Enable IC */
686 l.mfspr r6,r0,SPR_SR
687 l.ori r6,r6,SPR_SR_ICE
688 l.mtspr r0,r6,SPR_SR
689 l.nop
690 l.nop
691 l.nop
692 l.nop
693 l.nop
694 l.nop
695 l.nop
696 l.nop
697 l.nop
698 l.nop
6999:
700 l.jr r9
701 l.nop
702
703_dc_enable:
704 /* Check if DC present and skip enabling otherwise */
705 l.mfspr r24,r0,SPR_UPR
706 l.andi r26,r24,SPR_UPR_DCP
707 l.sfeq r26,r0
708 l.bf 9f
709 l.nop
710
711 /* Disable DC */
712 l.mfspr r6,r0,SPR_SR
713 l.addi r5,r0,-1
714 l.xori r5,r5,SPR_SR_DCE
715 l.and r5,r6,r5
716 l.mtspr r0,r5,SPR_SR
717
718 /* Establish cache block size
719 If BS=0, 16;
720 If BS=1, 32;
721 r14 contain block size
722 */
723 l.mfspr r24,r0,SPR_DCCFGR
724 l.andi r26,r24,SPR_DCCFGR_CBS
725 l.srli r28,r26,7
726 l.ori r30,r0,16
727 l.sll r14,r30,r28
728
729 /* Establish number of cache sets
730 r16 contains number of cache sets
731 r28 contains log(# of cache sets)
732 */
733 l.andi r26,r24,SPR_DCCFGR_NCS
734 l.srli r28,r26,3
735 l.ori r30,r0,1
736 l.sll r16,r30,r28
737
738 /* Invalidate DC */
739 l.addi r6,r0,0
740 l.sll r5,r14,r28
7411:
742 l.mtspr r0,r6,SPR_DCBIR
743 l.sfne r6,r5
744 l.bf 1b
745 l.add r6,r6,r14
746
747 /* Enable DC */
748 l.mfspr r6,r0,SPR_SR
749 l.ori r6,r6,SPR_SR_DCE
750 l.mtspr r0,r6,SPR_SR
7519:
752 l.jr r9
753 l.nop
754
755/* ===============================================[ page table masks ]=== */
756
757#define DTLB_UP_CONVERT_MASK 0x3fa
758#define ITLB_UP_CONVERT_MASK 0x3a
759
760/* for SMP we'd have (this is a bit subtle, CC must be always set
761 * for SMP, but since we have _PAGE_PRESENT bit always defined
762 * we can just modify the mask)
763 */
764#define DTLB_SMP_CONVERT_MASK 0x3fb
765#define ITLB_SMP_CONVERT_MASK 0x3b
766
767/* ---[ boot dtlb miss handler ]----------------------------------------- */
768
769boot_dtlb_miss_handler:
770
771/* mask for DTLB_MR register: - (0) sets V (valid) bit,
772 * - (31-12) sets bits belonging to VPN (31-12)
773 */
774#define DTLB_MR_MASK 0xfffff001
775
776/* mask for DTLB_TR register: - (2) sets CI (cache inhibit) bit,
777 * - (4) sets A (access) bit,
778 * - (5) sets D (dirty) bit,
779 * - (8) sets SRE (superuser read) bit
780 * - (9) sets SWE (superuser write) bit
781 * - (31-12) sets bits belonging to VPN (31-12)
782 */
783#define DTLB_TR_MASK 0xfffff332
784
785/* These are for masking out the VPN/PPN value from the MR/TR registers...
786 * it's not the same as the PFN */
787#define VPN_MASK 0xfffff000
788#define PPN_MASK 0xfffff000
789
790
791 EXCEPTION_STORE_GPR6
792
793#if 0
794 l.mfspr r6,r0,SPR_ESR_BASE //
795 l.andi r6,r6,SPR_SR_SM // are we in kernel mode ?
796 l.sfeqi r6,0 // r6 == 0x1 --> SM
797 l.bf exit_with_no_dtranslation //
798 l.nop
799#endif
800
801 /* this could be optimized by moving storing of
802 * non r6 registers here, and jumping r6 restore
803 * if not in supervisor mode
804 */
805
806 EXCEPTION_STORE_GPR2
807 EXCEPTION_STORE_GPR3
808 EXCEPTION_STORE_GPR4
809 EXCEPTION_STORE_GPR5
810
811 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA
812
813immediate_translation:
814 CLEAR_GPR(r6)
815
816 l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN size (4Kb)
817
818 l.mfspr r6, r0, SPR_DMMUCFGR
819 l.andi r6, r6, SPR_DMMUCFGR_NTS
820 l.srli r6, r6, SPR_DMMUCFGR_NTS_OFF
821 l.ori r5, r0, 0x1
822 l.sll r5, r5, r6 // r5 = number DMMU sets
823 l.addi r6, r5, -1 // r6 = nsets mask
824 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
825
826 l.or r6,r6,r4 // r6 <- r4
827 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
828 l.movhi r5,hi(DTLB_MR_MASK) // r5 <- ffff:0000.x000
829 l.ori r5,r5,lo(DTLB_MR_MASK) // r5 <- ffff:1111.x001 - apply DTLB_MR_MASK
830 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have DTLBMR entry
831 l.mtspr r2,r5,SPR_DTLBMR_BASE(0) // set DTLBMR
832
833 /* set up DTLB with no translation for EA <= 0xbfffffff */
834 LOAD_SYMBOL_2_GPR(r6,0xbfffffff)
835 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xbfffffff >= EA)
836 l.bf 1f // goto out
837 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
838
839 tophys(r3,r4) // r3 <- PA
8401:
841 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
842 l.movhi r5,hi(DTLB_TR_MASK) // r5 <- ffff:0000.x000
843 l.ori r5,r5,lo(DTLB_TR_MASK) // r5 <- ffff:1111.x330 - apply DTLB_MR_MASK
844 l.and r5,r5,r3 // r5 <- PPN :PPN .x330 - we have DTLBTR entry
845 l.mtspr r2,r5,SPR_DTLBTR_BASE(0) // set DTLBTR
846
847 EXCEPTION_LOAD_GPR6
848 EXCEPTION_LOAD_GPR5
849 EXCEPTION_LOAD_GPR4
850 EXCEPTION_LOAD_GPR3
851 EXCEPTION_LOAD_GPR2
852
853 l.rfe // SR <- ESR, PC <- EPC
854
855exit_with_no_dtranslation:
856 /* EA out of memory or not in supervisor mode */
857 EXCEPTION_LOAD_GPR6
858 EXCEPTION_LOAD_GPR4
859 l.j _dispatch_bus_fault
860
861/* ---[ boot itlb miss handler ]----------------------------------------- */
862
863boot_itlb_miss_handler:
864
865/* mask for ITLB_MR register: - sets V (valid) bit,
866 * - sets bits belonging to VPN (15-12)
867 */
868#define ITLB_MR_MASK 0xfffff001
869
870/* mask for ITLB_TR register: - sets A (access) bit,
871 * - sets SXE (superuser execute) bit
872 * - sets bits belonging to VPN (15-12)
873 */
874#define ITLB_TR_MASK 0xfffff050
875
876/*
877#define VPN_MASK 0xffffe000
878#define PPN_MASK 0xffffe000
879*/
880
881
882
883 EXCEPTION_STORE_GPR2
884 EXCEPTION_STORE_GPR3
885 EXCEPTION_STORE_GPR4
886 EXCEPTION_STORE_GPR5
887 EXCEPTION_STORE_GPR6
888
889#if 0
890 l.mfspr r6,r0,SPR_ESR_BASE //
891 l.andi r6,r6,SPR_SR_SM // are we in kernel mode ?
892 l.sfeqi r6,0 // r6 == 0x1 --> SM
893 l.bf exit_with_no_itranslation
894 l.nop
895#endif
896
897
898 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA
899
900earlyearly:
901 CLEAR_GPR(r6)
902
903 l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN size (4Kb)
904
905 l.mfspr r6, r0, SPR_IMMUCFGR
906 l.andi r6, r6, SPR_IMMUCFGR_NTS
907 l.srli r6, r6, SPR_IMMUCFGR_NTS_OFF
908 l.ori r5, r0, 0x1
909 l.sll r5, r5, r6 // r5 = number IMMU sets from IMMUCFGR
910 l.addi r6, r5, -1 // r6 = nsets mask
911 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
912
913 l.or r6,r6,r4 // r6 <- r4
914 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
915 l.movhi r5,hi(ITLB_MR_MASK) // r5 <- ffff:0000.x000
916 l.ori r5,r5,lo(ITLB_MR_MASK) // r5 <- ffff:1111.x001 - apply ITLB_MR_MASK
917 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have ITLBMR entry
918 l.mtspr r2,r5,SPR_ITLBMR_BASE(0) // set ITLBMR
919
920 /*
921 * set up ITLB with no translation for EA <= 0x0fffffff
922 *
923 * we need this for head.S mapping (EA = PA). if we move all functions
924 * which run with mmu enabled into entry.S, we might be able to eliminate this.
925 *
926 */
927 LOAD_SYMBOL_2_GPR(r6,0x0fffffff)
928 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xb0ffffff >= EA)
929 l.bf 1f // goto out
930 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
931
932 tophys(r3,r4) // r3 <- PA
9331:
934 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
935 l.movhi r5,hi(ITLB_TR_MASK) // r5 <- ffff:0000.x000
936 l.ori r5,r5,lo(ITLB_TR_MASK) // r5 <- ffff:1111.x050 - apply ITLB_MR_MASK
937 l.and r5,r5,r3 // r5 <- PPN :PPN .x050 - we have ITLBTR entry
938 l.mtspr r2,r5,SPR_ITLBTR_BASE(0) // set ITLBTR
939
940 EXCEPTION_LOAD_GPR6
941 EXCEPTION_LOAD_GPR5
942 EXCEPTION_LOAD_GPR4
943 EXCEPTION_LOAD_GPR3
944 EXCEPTION_LOAD_GPR2
945
946 l.rfe // SR <- ESR, PC <- EPC
947
948exit_with_no_itranslation:
949 EXCEPTION_LOAD_GPR4
950 EXCEPTION_LOAD_GPR6
951 l.j _dispatch_bus_fault
952 l.nop
953
954/* ====================================================================== */
955/*
956 * Stuff below here shouldn't go into .head section... maybe this stuff
957 * can be moved to entry.S ???
958 */
959
960/* ==============================================[ DTLB miss handler ]=== */
961
962/*
963 * Comments:
964 * Exception handlers are entered with MMU off so the following handler
965 * needs to use physical addressing
966 *
967 */
968
969 .text
970ENTRY(dtlb_miss_handler)
971 EXCEPTION_STORE_GPR2
972 EXCEPTION_STORE_GPR3
973 EXCEPTION_STORE_GPR4
974 EXCEPTION_STORE_GPR5
975 EXCEPTION_STORE_GPR6
976 /*
977 * get EA of the miss
978 */
979 l.mfspr r2,r0,SPR_EEAR_BASE
980 /*
981 * pmd = (pmd_t *)(current_pgd + pgd_index(daddr));
982 */
983 GET_CURRENT_PGD(r3,r5) // r3 is current_pgd, r5 is temp
984 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
985 l.slli r4,r4,0x2 // to get address << 2
986 l.add r5,r4,r3 // r4 is pgd_index(daddr)
987 /*
988 * if (pmd_none(*pmd))
989 * goto pmd_none:
990 */
991 tophys (r4,r5)
992 l.lwz r3,0x0(r4) // get *pmd value
993 l.sfne r3,r0
994 l.bnf d_pmd_none
995 l.andi r3,r3,~PAGE_MASK //0x1fff // ~PAGE_MASK
996 /*
997 * if (pmd_bad(*pmd))
998 * pmd_clear(pmd)
999 * goto pmd_bad:
1000 */
1001// l.sfeq r3,r0 // check *pmd value
1002// l.bf d_pmd_good
1003 l.addi r3,r0,0xffffe000 // PAGE_MASK
1004// l.j d_pmd_bad
1005// l.sw 0x0(r4),r0 // clear pmd
1006d_pmd_good:
1007 /*
1008 * pte = *pte_offset(pmd, daddr);
1009 */
1010 l.lwz r4,0x0(r4) // get **pmd value
1011 l.and r4,r4,r3 // & PAGE_MASK
1012 l.srli r5,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
1013 l.andi r3,r5,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1014 l.slli r3,r3,0x2 // to get address << 2
1015 l.add r3,r3,r4
1016 l.lwz r2,0x0(r3) // this is pte at last
1017 /*
1018 * if (!pte_present(pte))
1019 */
1020 l.andi r4,r2,0x1
1021 l.sfne r4,r0 // is pte present
1022 l.bnf d_pte_not_present
1023 l.addi r3,r0,0xffffe3fa // PAGE_MASK | DTLB_UP_CONVERT_MASK
1024 /*
1025 * fill DTLB TR register
1026 */
1027 l.and r4,r2,r3 // apply the mask
1028 // Determine number of DMMU sets
1029 l.mfspr r6, r0, SPR_DMMUCFGR
1030 l.andi r6, r6, SPR_DMMUCFGR_NTS
1031 l.srli r6, r6, SPR_DMMUCFGR_NTS_OFF
1032 l.ori r3, r0, 0x1
1033 l.sll r3, r3, r6 // r3 = number DMMU sets DMMUCFGR
1034 l.addi r6, r3, -1 // r6 = nsets mask
1035 l.and r5, r5, r6 // calc offset: & (NUM_TLB_ENTRIES-1)
1036 //NUM_TLB_ENTRIES
1037 l.mtspr r5,r4,SPR_DTLBTR_BASE(0)
1038 /*
1039 * fill DTLB MR register
1040 */
1041 l.mfspr r2,r0,SPR_EEAR_BASE
1042 l.addi r3,r0,0xffffe000 // PAGE_MASK
1043 l.and r4,r2,r3 // apply PAGE_MASK to EA (__PHX__ do we really need this?)
1044 l.ori r4,r4,0x1 // set hardware valid bit: DTBL_MR entry
1045 l.mtspr r5,r4,SPR_DTLBMR_BASE(0)
1046
1047 EXCEPTION_LOAD_GPR2
1048 EXCEPTION_LOAD_GPR3
1049 EXCEPTION_LOAD_GPR4
1050 EXCEPTION_LOAD_GPR5
1051 EXCEPTION_LOAD_GPR6
1052 l.rfe
1053d_pmd_bad:
1054 l.nop 1
1055 EXCEPTION_LOAD_GPR2
1056 EXCEPTION_LOAD_GPR3
1057 EXCEPTION_LOAD_GPR4
1058 EXCEPTION_LOAD_GPR5
1059 EXCEPTION_LOAD_GPR6
1060 l.rfe
1061d_pmd_none:
1062d_pte_not_present:
1063 EXCEPTION_LOAD_GPR2
1064 EXCEPTION_LOAD_GPR3
1065 EXCEPTION_LOAD_GPR4
1066 EXCEPTION_LOAD_GPR5
1067 EXCEPTION_LOAD_GPR6
1068 EXCEPTION_HANDLE(_dtlb_miss_page_fault_handler)
1069
1070/* ==============================================[ ITLB miss handler ]=== */
1071ENTRY(itlb_miss_handler)
1072 EXCEPTION_STORE_GPR2
1073 EXCEPTION_STORE_GPR3
1074 EXCEPTION_STORE_GPR4
1075 EXCEPTION_STORE_GPR5
1076 EXCEPTION_STORE_GPR6
1077 /*
1078 * get EA of the miss
1079 */
1080 l.mfspr r2,r0,SPR_EEAR_BASE
1081
1082 /*
1083 * pmd = (pmd_t *)(current_pgd + pgd_index(daddr));
1084 *
1085 */
1086 GET_CURRENT_PGD(r3,r5) // r3 is current_pgd, r5 is temp
1087 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1088 l.slli r4,r4,0x2 // to get address << 2
1089 l.add r5,r4,r3 // r4 is pgd_index(daddr)
1090 /*
1091 * if (pmd_none(*pmd))
1092 * goto pmd_none:
1093 */
1094 tophys (r4,r5)
1095 l.lwz r3,0x0(r4) // get *pmd value
1096 l.sfne r3,r0
1097 l.bnf i_pmd_none
1098 l.andi r3,r3,0x1fff // ~PAGE_MASK
1099 /*
1100 * if (pmd_bad(*pmd))
1101 * pmd_clear(pmd)
1102 * goto pmd_bad:
1103 */
1104
1105// l.sfeq r3,r0 // check *pmd value
1106// l.bf i_pmd_good
1107 l.addi r3,r0,0xffffe000 // PAGE_MASK
1108// l.j i_pmd_bad
1109// l.sw 0x0(r4),r0 // clear pmd
1110
1111i_pmd_good:
1112 /*
1113 * pte = *pte_offset(pmd, iaddr);
1114 *
1115 */
1116 l.lwz r4,0x0(r4) // get **pmd value
1117 l.and r4,r4,r3 // & PAGE_MASK
1118 l.srli r5,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
1119 l.andi r3,r5,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1120 l.slli r3,r3,0x2 // to get address << 2
1121 l.add r3,r3,r4
1122 l.lwz r2,0x0(r3) // this is pte at last
1123 /*
1124 * if (!pte_present(pte))
1125 *
1126 */
1127 l.andi r4,r2,0x1
1128 l.sfne r4,r0 // is pte present
1129 l.bnf i_pte_not_present
1130 l.addi r3,r0,0xffffe03a // PAGE_MASK | ITLB_UP_CONVERT_MASK
1131 /*
1132 * fill ITLB TR register
1133 */
1134 l.and r4,r2,r3 // apply the mask
1135 l.andi r3,r2,0x7c0 // _PAGE_EXEC | _PAGE_SRE | _PAGE_SWE | _PAGE_URE | _PAGE_UWE
1136// l.andi r3,r2,0x400 // _PAGE_EXEC
1137 l.sfeq r3,r0
1138 l.bf itlb_tr_fill //_workaround
1139 // Determine number of IMMU sets
1140 l.mfspr r6, r0, SPR_IMMUCFGR
1141 l.andi r6, r6, SPR_IMMUCFGR_NTS
1142 l.srli r6, r6, SPR_IMMUCFGR_NTS_OFF
1143 l.ori r3, r0, 0x1
1144 l.sll r3, r3, r6 // r3 = number IMMU sets IMMUCFGR
1145 l.addi r6, r3, -1 // r6 = nsets mask
1146 l.and r5, r5, r6 // calc offset: & (NUM_TLB_ENTRIES-1)
1147
1148/*
1149 * __PHX__ :: fixme
1150 * we should not just blindly set executable flags,
1151 * but it does help with ping. the clean way would be to find out
1152 * (and fix it) why stack doesn't have execution permissions
1153 */
1154
1155itlb_tr_fill_workaround:
1156 l.ori r4,r4,0xc0 // | (SPR_ITLBTR_UXE | ITLBTR_SXE)
1157itlb_tr_fill:
1158 l.mtspr r5,r4,SPR_ITLBTR_BASE(0)
1159 /*
1160 * fill DTLB MR register
1161 */
1162 l.mfspr r2,r0,SPR_EEAR_BASE
1163 l.addi r3,r0,0xffffe000 // PAGE_MASK
1164 l.and r4,r2,r3 // apply PAGE_MASK to EA (__PHX__ do we really need this?)
1165 l.ori r4,r4,0x1 // set hardware valid bit: DTBL_MR entry
1166 l.mtspr r5,r4,SPR_ITLBMR_BASE(0)
1167
1168 EXCEPTION_LOAD_GPR2
1169 EXCEPTION_LOAD_GPR3
1170 EXCEPTION_LOAD_GPR4
1171 EXCEPTION_LOAD_GPR5
1172 EXCEPTION_LOAD_GPR6
1173 l.rfe
1174
1175i_pmd_bad:
1176 l.nop 1
1177 EXCEPTION_LOAD_GPR2
1178 EXCEPTION_LOAD_GPR3
1179 EXCEPTION_LOAD_GPR4
1180 EXCEPTION_LOAD_GPR5
1181 EXCEPTION_LOAD_GPR6
1182 l.rfe
1183i_pmd_none:
1184i_pte_not_present:
1185 EXCEPTION_LOAD_GPR2
1186 EXCEPTION_LOAD_GPR3
1187 EXCEPTION_LOAD_GPR4
1188 EXCEPTION_LOAD_GPR5
1189 EXCEPTION_LOAD_GPR6
1190 EXCEPTION_HANDLE(_itlb_miss_page_fault_handler)
1191
1192/* ==============================================[ boot tlb handlers ]=== */
1193
1194
1195/* =================================================[ debugging aids ]=== */
1196
1197 .align 64
1198_immu_trampoline:
1199 .space 64
1200_immu_trampoline_top:
1201
1202#define TRAMP_SLOT_0 (0x0)
1203#define TRAMP_SLOT_1 (0x4)
1204#define TRAMP_SLOT_2 (0x8)
1205#define TRAMP_SLOT_3 (0xc)
1206#define TRAMP_SLOT_4 (0x10)
1207#define TRAMP_SLOT_5 (0x14)
1208#define TRAMP_FRAME_SIZE (0x18)
1209
1210ENTRY(_immu_trampoline_workaround)
1211 // r2 EEA
1212 // r6 is physical EEA
1213 tophys(r6,r2)
1214
1215 LOAD_SYMBOL_2_GPR(r5,_immu_trampoline)
1216 tophys (r3,r5) // r3 is trampoline (physical)
1217
1218 LOAD_SYMBOL_2_GPR(r4,0x15000000)
1219 l.sw TRAMP_SLOT_0(r3),r4
1220 l.sw TRAMP_SLOT_1(r3),r4
1221 l.sw TRAMP_SLOT_4(r3),r4
1222 l.sw TRAMP_SLOT_5(r3),r4
1223
1224 // EPC = EEA - 0x4
1225 l.lwz r4,0x0(r6) // load op @ EEA + 0x0 (fc address)
1226 l.sw TRAMP_SLOT_3(r3),r4 // store it to _immu_trampoline_data
1227 l.lwz r4,-0x4(r6) // load op @ EEA - 0x4 (f8 address)
1228 l.sw TRAMP_SLOT_2(r3),r4 // store it to _immu_trampoline_data
1229
1230 l.srli r5,r4,26 // check opcode for write access
1231 l.sfeqi r5,0 // l.j
1232 l.bf 0f
1233 l.sfeqi r5,0x11 // l.jr
1234 l.bf 1f
1235 l.sfeqi r5,1 // l.jal
1236 l.bf 2f
1237 l.sfeqi r5,0x12 // l.jalr
1238 l.bf 3f
1239 l.sfeqi r5,3 // l.bnf
1240 l.bf 4f
1241 l.sfeqi r5,4 // l.bf
1242 l.bf 5f
124399:
1244 l.nop
1245 l.j 99b // should never happen
1246 l.nop 1
1247
1248 // r2 is EEA
1249 // r3 is trampoline address (physical)
1250 // r4 is instruction
1251 // r6 is physical(EEA)
1252 //
1253 // r5
1254
12552: // l.jal
1256
1257 /* 19 20 aa aa l.movhi r9,0xaaaa
1258 * a9 29 bb bb l.ori r9,0xbbbb
1259 *
1260 * where 0xaaaabbbb is EEA + 0x4 shifted right 2
1261 */
1262
1263 l.addi r6,r2,0x4 // this is 0xaaaabbbb
1264
1265 // l.movhi r9,0xaaaa
1266 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
1267 l.sh (TRAMP_SLOT_0+0x0)(r3),r5
1268 l.srli r5,r6,16
1269 l.sh (TRAMP_SLOT_0+0x2)(r3),r5
1270
1271 // l.ori r9,0xbbbb
1272 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
1273 l.sh (TRAMP_SLOT_1+0x0)(r3),r5
1274 l.andi r5,r6,0xffff
1275 l.sh (TRAMP_SLOT_1+0x2)(r3),r5
1276
1277 /* falthrough, need to set up new jump offset */
1278
1279
12800: // l.j
1281 l.slli r6,r4,6 // original offset shifted left 6 - 2
1282// l.srli r6,r6,6 // original offset shifted right 2
1283
1284 l.slli r4,r2,4 // old jump position: EEA shifted left 4
1285// l.srli r4,r4,6 // old jump position: shifted right 2
1286
1287 l.addi r5,r3,0xc // new jump position (physical)
1288 l.slli r5,r5,4 // new jump position: shifted left 4
1289
1290 // calculate new jump offset
1291 // new_off = old_off + (old_jump - new_jump)
1292
1293 l.sub r5,r4,r5 // old_jump - new_jump
1294 l.add r5,r6,r5 // orig_off + (old_jump - new_jump)
1295 l.srli r5,r5,6 // new offset shifted right 2
1296
1297 // r5 is new jump offset
1298 // l.j has opcode 0x0...
1299 l.sw TRAMP_SLOT_2(r3),r5 // write it back
1300
1301 l.j trampoline_out
1302 l.nop
1303
1304/* ----------------------------- */
1305
13063: // l.jalr
1307
1308 /* 19 20 aa aa l.movhi r9,0xaaaa
1309 * a9 29 bb bb l.ori r9,0xbbbb
1310 *
1311 * where 0xaaaabbbb is EEA + 0x4 shifted right 2
1312 */
1313
1314 l.addi r6,r2,0x4 // this is 0xaaaabbbb
1315
1316 // l.movhi r9,0xaaaa
1317 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
1318 l.sh (TRAMP_SLOT_0+0x0)(r3),r5
1319 l.srli r5,r6,16
1320 l.sh (TRAMP_SLOT_0+0x2)(r3),r5
1321
1322 // l.ori r9,0xbbbb
1323 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
1324 l.sh (TRAMP_SLOT_1+0x0)(r3),r5
1325 l.andi r5,r6,0xffff
1326 l.sh (TRAMP_SLOT_1+0x2)(r3),r5
1327
1328 l.lhz r5,(TRAMP_SLOT_2+0x0)(r3) // load hi part of jump instruction
1329 l.andi r5,r5,0x3ff // clear out opcode part
1330 l.ori r5,r5,0x4400 // opcode changed from l.jalr -> l.jr
1331 l.sh (TRAMP_SLOT_2+0x0)(r3),r5 // write it back
1332
1333 /* falthrough */
1334
13351: // l.jr
1336 l.j trampoline_out
1337 l.nop
1338
1339/* ----------------------------- */
1340
13414: // l.bnf
13425: // l.bf
1343 l.slli r6,r4,6 // original offset shifted left 6 - 2
1344// l.srli r6,r6,6 // original offset shifted right 2
1345
1346 l.slli r4,r2,4 // old jump position: EEA shifted left 4
1347// l.srli r4,r4,6 // old jump position: shifted right 2
1348
1349 l.addi r5,r3,0xc // new jump position (physical)
1350 l.slli r5,r5,4 // new jump position: shifted left 4
1351
1352 // calculate new jump offset
1353 // new_off = old_off + (old_jump - new_jump)
1354
1355 l.add r6,r6,r4 // (orig_off + old_jump)
1356 l.sub r6,r6,r5 // (orig_off + old_jump) - new_jump
1357 l.srli r6,r6,6 // new offset shifted right 2
1358
1359 // r6 is new jump offset
1360 l.lwz r4,(TRAMP_SLOT_2+0x0)(r3) // load jump instruction
1361 l.srli r4,r4,16
1362 l.andi r4,r4,0xfc00 // get opcode part
1363 l.slli r4,r4,16
1364 l.or r6,r4,r6 // l.b(n)f new offset
1365 l.sw TRAMP_SLOT_2(r3),r6 // write it back
1366
1367 /* we need to add l.j to EEA + 0x8 */
1368 tophys (r4,r2) // may not be needed (due to shifts down_
1369 l.addi r4,r4,(0x8 - 0x8) // jump target = r2 + 0x8 (compensate for 0x8)
1370 // jump position = r5 + 0x8 (0x8 compensated)
1371 l.sub r4,r4,r5 // jump offset = target - new_position + 0x8
1372
1373 l.slli r4,r4,4 // the amount of info in imediate of jump
1374 l.srli r4,r4,6 // jump instruction with offset
1375 l.sw TRAMP_SLOT_4(r3),r4 // write it to 4th slot
1376
1377 /* fallthrough */
1378
1379trampoline_out:
1380 // set up new EPC to point to our trampoline code
1381 LOAD_SYMBOL_2_GPR(r5,_immu_trampoline)
1382 l.mtspr r0,r5,SPR_EPCR_BASE
1383
1384 // immu_trampoline is (4x) CACHE_LINE aligned
1385 // and only 6 instructions long,
1386 // so we need to invalidate only 2 lines
1387
1388 /* Establish cache block size
1389 If BS=0, 16;
1390 If BS=1, 32;
1391 r14 contain block size
1392 */
1393 l.mfspr r21,r0,SPR_ICCFGR
1394 l.andi r21,r21,SPR_ICCFGR_CBS
1395 l.srli r21,r21,7
1396 l.ori r23,r0,16
1397 l.sll r14,r23,r21
1398
1399 l.mtspr r0,r5,SPR_ICBIR
1400 l.add r5,r5,r14
1401 l.mtspr r0,r5,SPR_ICBIR
1402
1403 l.jr r9
1404 l.nop
1405
1406
1407/*
1408 * DSCR: prints a string referenced by r3.
1409 *
1410 * PRMS: r3 - address of the first character of null
1411 * terminated string to be printed
1412 *
1413 * PREQ: UART at UART_BASE_ADD has to be initialized
1414 *
1415 * POST: caller should be aware that r3, r9 are changed
1416 */
1417ENTRY(_emergency_print)
1418 EMERGENCY_PRINT_STORE_GPR4
1419 EMERGENCY_PRINT_STORE_GPR5
1420 EMERGENCY_PRINT_STORE_GPR6
1421 EMERGENCY_PRINT_STORE_GPR7
14222:
1423 l.lbz r7,0(r3)
1424 l.sfeq r7,r0
1425 l.bf 9f
1426 l.nop
1427
1428// putc:
1429 l.movhi r4,hi(UART_BASE_ADD)
1430
1431 l.addi r6,r0,0x20
14321: l.lbz r5,5(r4)
1433 l.andi r5,r5,0x20
1434 l.sfeq r5,r6
1435 l.bnf 1b
1436 l.nop
1437
1438 l.sb 0(r4),r7
1439
1440 l.addi r6,r0,0x60
14411: l.lbz r5,5(r4)
1442 l.andi r5,r5,0x60
1443 l.sfeq r5,r6
1444 l.bnf 1b
1445 l.nop
1446
1447 /* next character */
1448 l.j 2b
1449 l.addi r3,r3,0x1
1450
14519:
1452 EMERGENCY_PRINT_LOAD_GPR7
1453 EMERGENCY_PRINT_LOAD_GPR6
1454 EMERGENCY_PRINT_LOAD_GPR5
1455 EMERGENCY_PRINT_LOAD_GPR4
1456 l.jr r9
1457 l.nop
1458
1459ENTRY(_emergency_print_nr)
1460 EMERGENCY_PRINT_STORE_GPR4
1461 EMERGENCY_PRINT_STORE_GPR5
1462 EMERGENCY_PRINT_STORE_GPR6
1463 EMERGENCY_PRINT_STORE_GPR7
1464 EMERGENCY_PRINT_STORE_GPR8
1465
1466 l.addi r8,r0,32 // shift register
1467
14681: /* remove leading zeros */
1469 l.addi r8,r8,-0x4
1470 l.srl r7,r3,r8
1471 l.andi r7,r7,0xf
1472
1473 /* don't skip the last zero if number == 0x0 */
1474 l.sfeqi r8,0x4
1475 l.bf 2f
1476 l.nop
1477
1478 l.sfeq r7,r0
1479 l.bf 1b
1480 l.nop
1481
14822:
1483 l.srl r7,r3,r8
1484
1485 l.andi r7,r7,0xf
1486 l.sflts r8,r0
1487 l.bf 9f
1488
1489 l.sfgtui r7,0x9
1490 l.bnf 8f
1491 l.nop
1492 l.addi r7,r7,0x27
1493
14948:
1495 l.addi r7,r7,0x30
1496// putc:
1497 l.movhi r4,hi(UART_BASE_ADD)
1498
1499 l.addi r6,r0,0x20
15001: l.lbz r5,5(r4)
1501 l.andi r5,r5,0x20
1502 l.sfeq r5,r6
1503 l.bnf 1b
1504 l.nop
1505
1506 l.sb 0(r4),r7
1507
1508 l.addi r6,r0,0x60
15091: l.lbz r5,5(r4)
1510 l.andi r5,r5,0x60
1511 l.sfeq r5,r6
1512 l.bnf 1b
1513 l.nop
1514
1515 /* next character */
1516 l.j 2b
1517 l.addi r8,r8,-0x4
1518
15199:
1520 EMERGENCY_PRINT_LOAD_GPR8
1521 EMERGENCY_PRINT_LOAD_GPR7
1522 EMERGENCY_PRINT_LOAD_GPR6
1523 EMERGENCY_PRINT_LOAD_GPR5
1524 EMERGENCY_PRINT_LOAD_GPR4
1525 l.jr r9
1526 l.nop
1527
1528
1529/*
1530 * This should be used for debugging only.
1531 * It messes up the Linux early serial output
1532 * somehow, so use it sparingly and essentially
1533 * only if you need to debug something that goes wrong
1534 * before Linux gets the early serial going.
1535 *
1536 * Furthermore, you'll have to make sure you set the
1537 * UART_DEVISOR correctly according to the system
1538 * clock rate.
1539 *
1540 *
1541 */
1542
1543
1544
1545#define SYS_CLK 20000000
1546//#define SYS_CLK 1843200
1547#define OR32_CONSOLE_BAUD 115200
1548#define UART_DIVISOR SYS_CLK/(16*OR32_CONSOLE_BAUD)
1549
1550ENTRY(_early_uart_init)
1551 l.movhi r3,hi(UART_BASE_ADD)
1552
1553 l.addi r4,r0,0x7
1554 l.sb 0x2(r3),r4
1555
1556 l.addi r4,r0,0x0
1557 l.sb 0x1(r3),r4
1558
1559 l.addi r4,r0,0x3
1560 l.sb 0x3(r3),r4
1561
1562 l.lbz r5,3(r3)
1563 l.ori r4,r5,0x80
1564 l.sb 0x3(r3),r4
1565 l.addi r4,r0,((UART_DIVISOR>>8) & 0x000000ff)
1566 l.sb UART_DLM(r3),r4
1567 l.addi r4,r0,((UART_DIVISOR) & 0x000000ff)
1568 l.sb UART_DLL(r3),r4
1569 l.sb 0x3(r3),r5
1570
1571 l.jr r9
1572 l.nop
1573
1574_string_copying_linux:
1575 .string "\n\n\n\n\n\rCopying Linux... \0"
1576
1577_string_ok_booting:
1578 .string "Ok, booting the kernel.\n\r\0"
1579
1580_string_unhandled_exception:
1581 .string "\n\rRunarunaround: Unhandled exception 0x\0"
1582
1583_string_epc_prefix:
1584 .string ": EPC=0x\0"
1585
1586_string_nl:
1587 .string "\n\r\0"
1588
1589 .global _string_esr_irq_bug
1590_string_esr_irq_bug:
1591 .string "\n\rESR external interrupt bug, for details look into entry.S\n\r\0"
1592
1593
1594
1595/* ========================================[ page aligned structures ]=== */
1596
1597/*
1598 * .data section should be page aligned
1599 * (look into arch/or32/kernel/vmlinux.lds)
1600 */
1601 .section .data,"aw"
1602 .align 8192
1603 .global empty_zero_page
1604empty_zero_page:
1605 .space 8192
1606
1607 .global swapper_pg_dir
1608swapper_pg_dir:
1609 .space 8192
1610
1611 .global _unhandled_stack
1612_unhandled_stack:
1613 .space 8192
1614_unhandled_stack_top:
1615
1616/* ============================================================[ EOF ]=== */