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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999, 2000, 06 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 */
9#ifndef _ASM_SPINLOCK_H
10#define _ASM_SPINLOCK_H
11
12#include <linux/compiler.h>
13
14#include <asm/barrier.h>
15#include <asm/war.h>
16
17/*
18 * Your basic SMP spinlocks, allowing only a single CPU anywhere
19 *
20 * Simple spin lock operations. There are two variants, one clears IRQ's
21 * on the local processor, one does not.
22 *
23 * These are fair FIFO ticket locks
24 *
25 * (the type definitions are in asm/spinlock_types.h)
26 */
27
28
29/*
30 * Ticket locks are conceptually two parts, one indicating the current head of
31 * the queue, and the other indicating the current tail. The lock is acquired
32 * by atomically noting the tail and incrementing it by one (thus adding
33 * ourself to the queue and noting our position), then waiting until the head
34 * becomes equal to the the initial value of the tail.
35 */
36
37static inline int arch_spin_is_locked(arch_spinlock_t *lock)
38{
39 u32 counters = ACCESS_ONCE(lock->lock);
40
41 return ((counters >> 16) ^ counters) & 0xffff;
42}
43
44#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
45#define arch_spin_unlock_wait(x) \
46 while (arch_spin_is_locked(x)) { cpu_relax(); }
47
48static inline int arch_spin_is_contended(arch_spinlock_t *lock)
49{
50 u32 counters = ACCESS_ONCE(lock->lock);
51
52 return (((counters >> 16) - counters) & 0xffff) > 1;
53}
54#define arch_spin_is_contended arch_spin_is_contended
55
56static inline void arch_spin_lock(arch_spinlock_t *lock)
57{
58 int my_ticket;
59 int tmp;
60 int inc = 0x10000;
61
62 if (R10000_LLSC_WAR) {
63 __asm__ __volatile__ (
64 " .set push # arch_spin_lock \n"
65 " .set noreorder \n"
66 " \n"
67 "1: ll %[ticket], %[ticket_ptr] \n"
68 " addu %[my_ticket], %[ticket], %[inc] \n"
69 " sc %[my_ticket], %[ticket_ptr] \n"
70 " beqzl %[my_ticket], 1b \n"
71 " nop \n"
72 " srl %[my_ticket], %[ticket], 16 \n"
73 " andi %[ticket], %[ticket], 0xffff \n"
74 " andi %[my_ticket], %[my_ticket], 0xffff \n"
75 " bne %[ticket], %[my_ticket], 4f \n"
76 " subu %[ticket], %[my_ticket], %[ticket] \n"
77 "2: \n"
78 " .subsection 2 \n"
79 "4: andi %[ticket], %[ticket], 0xffff \n"
80 " sll %[ticket], 5 \n"
81 " \n"
82 "6: bnez %[ticket], 6b \n"
83 " subu %[ticket], 1 \n"
84 " \n"
85 " lhu %[ticket], %[serving_now_ptr] \n"
86 " beq %[ticket], %[my_ticket], 2b \n"
87 " subu %[ticket], %[my_ticket], %[ticket] \n"
88 " b 4b \n"
89 " subu %[ticket], %[ticket], 1 \n"
90 " .previous \n"
91 " .set pop \n"
92 : [ticket_ptr] "+m" (lock->lock),
93 [serving_now_ptr] "+m" (lock->h.serving_now),
94 [ticket] "=&r" (tmp),
95 [my_ticket] "=&r" (my_ticket)
96 : [inc] "r" (inc));
97 } else {
98 __asm__ __volatile__ (
99 " .set push # arch_spin_lock \n"
100 " .set noreorder \n"
101 " \n"
102 "1: ll %[ticket], %[ticket_ptr] \n"
103 " addu %[my_ticket], %[ticket], %[inc] \n"
104 " sc %[my_ticket], %[ticket_ptr] \n"
105 " beqz %[my_ticket], 1b \n"
106 " srl %[my_ticket], %[ticket], 16 \n"
107 " andi %[ticket], %[ticket], 0xffff \n"
108 " andi %[my_ticket], %[my_ticket], 0xffff \n"
109 " bne %[ticket], %[my_ticket], 4f \n"
110 " subu %[ticket], %[my_ticket], %[ticket] \n"
111 "2: \n"
112 " .subsection 2 \n"
113 "4: andi %[ticket], %[ticket], 0x1fff \n"
114 " sll %[ticket], 5 \n"
115 " \n"
116 "6: bnez %[ticket], 6b \n"
117 " subu %[ticket], 1 \n"
118 " \n"
119 " lhu %[ticket], %[serving_now_ptr] \n"
120 " beq %[ticket], %[my_ticket], 2b \n"
121 " subu %[ticket], %[my_ticket], %[ticket] \n"
122 " b 4b \n"
123 " subu %[ticket], %[ticket], 1 \n"
124 " .previous \n"
125 " .set pop \n"
126 : [ticket_ptr] "+m" (lock->lock),
127 [serving_now_ptr] "+m" (lock->h.serving_now),
128 [ticket] "=&r" (tmp),
129 [my_ticket] "=&r" (my_ticket)
130 : [inc] "r" (inc));
131 }
132
133 smp_llsc_mb();
134}
135
136static inline void arch_spin_unlock(arch_spinlock_t *lock)
137{
138 unsigned int serving_now = lock->h.serving_now + 1;
139 wmb();
140 lock->h.serving_now = (u16)serving_now;
141 nudge_writes();
142}
143
144static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock)
145{
146 int tmp, tmp2, tmp3;
147 int inc = 0x10000;
148
149 if (R10000_LLSC_WAR) {
150 __asm__ __volatile__ (
151 " .set push # arch_spin_trylock \n"
152 " .set noreorder \n"
153 " \n"
154 "1: ll %[ticket], %[ticket_ptr] \n"
155 " srl %[my_ticket], %[ticket], 16 \n"
156 " andi %[my_ticket], %[my_ticket], 0xffff \n"
157 " andi %[now_serving], %[ticket], 0xffff \n"
158 " bne %[my_ticket], %[now_serving], 3f \n"
159 " addu %[ticket], %[ticket], %[inc] \n"
160 " sc %[ticket], %[ticket_ptr] \n"
161 " beqzl %[ticket], 1b \n"
162 " li %[ticket], 1 \n"
163 "2: \n"
164 " .subsection 2 \n"
165 "3: b 2b \n"
166 " li %[ticket], 0 \n"
167 " .previous \n"
168 " .set pop \n"
169 : [ticket_ptr] "+m" (lock->lock),
170 [ticket] "=&r" (tmp),
171 [my_ticket] "=&r" (tmp2),
172 [now_serving] "=&r" (tmp3)
173 : [inc] "r" (inc));
174 } else {
175 __asm__ __volatile__ (
176 " .set push # arch_spin_trylock \n"
177 " .set noreorder \n"
178 " \n"
179 "1: ll %[ticket], %[ticket_ptr] \n"
180 " srl %[my_ticket], %[ticket], 16 \n"
181 " andi %[my_ticket], %[my_ticket], 0xffff \n"
182 " andi %[now_serving], %[ticket], 0xffff \n"
183 " bne %[my_ticket], %[now_serving], 3f \n"
184 " addu %[ticket], %[ticket], %[inc] \n"
185 " sc %[ticket], %[ticket_ptr] \n"
186 " beqz %[ticket], 1b \n"
187 " li %[ticket], 1 \n"
188 "2: \n"
189 " .subsection 2 \n"
190 "3: b 2b \n"
191 " li %[ticket], 0 \n"
192 " .previous \n"
193 " .set pop \n"
194 : [ticket_ptr] "+m" (lock->lock),
195 [ticket] "=&r" (tmp),
196 [my_ticket] "=&r" (tmp2),
197 [now_serving] "=&r" (tmp3)
198 : [inc] "r" (inc));
199 }
200
201 smp_llsc_mb();
202
203 return tmp;
204}
205
206/*
207 * Read-write spinlocks, allowing multiple readers but only one writer.
208 *
209 * NOTE! it is quite common to have readers in interrupts but no interrupt
210 * writers. For those circumstances we can "mix" irq-safe locks - any writer
211 * needs to get a irq-safe write-lock, but readers can get non-irqsafe
212 * read-locks.
213 */
214
215/*
216 * read_can_lock - would read_trylock() succeed?
217 * @lock: the rwlock in question.
218 */
219#define arch_read_can_lock(rw) ((rw)->lock >= 0)
220
221/*
222 * write_can_lock - would write_trylock() succeed?
223 * @lock: the rwlock in question.
224 */
225#define arch_write_can_lock(rw) (!(rw)->lock)
226
227static inline void arch_read_lock(arch_rwlock_t *rw)
228{
229 unsigned int tmp;
230
231 if (R10000_LLSC_WAR) {
232 __asm__ __volatile__(
233 " .set noreorder # arch_read_lock \n"
234 "1: ll %1, %2 \n"
235 " bltz %1, 1b \n"
236 " addu %1, 1 \n"
237 " sc %1, %0 \n"
238 " beqzl %1, 1b \n"
239 " nop \n"
240 " .set reorder \n"
241 : "=m" (rw->lock), "=&r" (tmp)
242 : "m" (rw->lock)
243 : "memory");
244 } else {
245 __asm__ __volatile__(
246 " .set noreorder # arch_read_lock \n"
247 "1: ll %1, %2 \n"
248 " bltz %1, 3f \n"
249 " addu %1, 1 \n"
250 "2: sc %1, %0 \n"
251 " beqz %1, 1b \n"
252 " nop \n"
253 " .subsection 2 \n"
254 "3: ll %1, %2 \n"
255 " bltz %1, 3b \n"
256 " addu %1, 1 \n"
257 " b 2b \n"
258 " nop \n"
259 " .previous \n"
260 " .set reorder \n"
261 : "=m" (rw->lock), "=&r" (tmp)
262 : "m" (rw->lock)
263 : "memory");
264 }
265
266 smp_llsc_mb();
267}
268
269/* Note the use of sub, not subu which will make the kernel die with an
270 overflow exception if we ever try to unlock an rwlock that is already
271 unlocked or is being held by a writer. */
272static inline void arch_read_unlock(arch_rwlock_t *rw)
273{
274 unsigned int tmp;
275
276 smp_mb__before_llsc();
277
278 if (R10000_LLSC_WAR) {
279 __asm__ __volatile__(
280 "1: ll %1, %2 # arch_read_unlock \n"
281 " sub %1, 1 \n"
282 " sc %1, %0 \n"
283 " beqzl %1, 1b \n"
284 : "=m" (rw->lock), "=&r" (tmp)
285 : "m" (rw->lock)
286 : "memory");
287 } else {
288 __asm__ __volatile__(
289 " .set noreorder # arch_read_unlock \n"
290 "1: ll %1, %2 \n"
291 " sub %1, 1 \n"
292 " sc %1, %0 \n"
293 " beqz %1, 2f \n"
294 " nop \n"
295 " .subsection 2 \n"
296 "2: b 1b \n"
297 " nop \n"
298 " .previous \n"
299 " .set reorder \n"
300 : "=m" (rw->lock), "=&r" (tmp)
301 : "m" (rw->lock)
302 : "memory");
303 }
304}
305
306static inline void arch_write_lock(arch_rwlock_t *rw)
307{
308 unsigned int tmp;
309
310 if (R10000_LLSC_WAR) {
311 __asm__ __volatile__(
312 " .set noreorder # arch_write_lock \n"
313 "1: ll %1, %2 \n"
314 " bnez %1, 1b \n"
315 " lui %1, 0x8000 \n"
316 " sc %1, %0 \n"
317 " beqzl %1, 1b \n"
318 " nop \n"
319 " .set reorder \n"
320 : "=m" (rw->lock), "=&r" (tmp)
321 : "m" (rw->lock)
322 : "memory");
323 } else {
324 __asm__ __volatile__(
325 " .set noreorder # arch_write_lock \n"
326 "1: ll %1, %2 \n"
327 " bnez %1, 3f \n"
328 " lui %1, 0x8000 \n"
329 "2: sc %1, %0 \n"
330 " beqz %1, 3f \n"
331 " nop \n"
332 " .subsection 2 \n"
333 "3: ll %1, %2 \n"
334 " bnez %1, 3b \n"
335 " lui %1, 0x8000 \n"
336 " b 2b \n"
337 " nop \n"
338 " .previous \n"
339 " .set reorder \n"
340 : "=m" (rw->lock), "=&r" (tmp)
341 : "m" (rw->lock)
342 : "memory");
343 }
344
345 smp_llsc_mb();
346}
347
348static inline void arch_write_unlock(arch_rwlock_t *rw)
349{
350 smp_mb();
351
352 __asm__ __volatile__(
353 " # arch_write_unlock \n"
354 " sw $0, %0 \n"
355 : "=m" (rw->lock)
356 : "m" (rw->lock)
357 : "memory");
358}
359
360static inline int arch_read_trylock(arch_rwlock_t *rw)
361{
362 unsigned int tmp;
363 int ret;
364
365 if (R10000_LLSC_WAR) {
366 __asm__ __volatile__(
367 " .set noreorder # arch_read_trylock \n"
368 " li %2, 0 \n"
369 "1: ll %1, %3 \n"
370 " bltz %1, 2f \n"
371 " addu %1, 1 \n"
372 " sc %1, %0 \n"
373 " .set reorder \n"
374 " beqzl %1, 1b \n"
375 " nop \n"
376 __WEAK_LLSC_MB
377 " li %2, 1 \n"
378 "2: \n"
379 : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
380 : "m" (rw->lock)
381 : "memory");
382 } else {
383 __asm__ __volatile__(
384 " .set noreorder # arch_read_trylock \n"
385 " li %2, 0 \n"
386 "1: ll %1, %3 \n"
387 " bltz %1, 2f \n"
388 " addu %1, 1 \n"
389 " sc %1, %0 \n"
390 " beqz %1, 1b \n"
391 " nop \n"
392 " .set reorder \n"
393 __WEAK_LLSC_MB
394 " li %2, 1 \n"
395 "2: \n"
396 : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
397 : "m" (rw->lock)
398 : "memory");
399 }
400
401 return ret;
402}
403
404static inline int arch_write_trylock(arch_rwlock_t *rw)
405{
406 unsigned int tmp;
407 int ret;
408
409 if (R10000_LLSC_WAR) {
410 __asm__ __volatile__(
411 " .set noreorder # arch_write_trylock \n"
412 " li %2, 0 \n"
413 "1: ll %1, %3 \n"
414 " bnez %1, 2f \n"
415 " lui %1, 0x8000 \n"
416 " sc %1, %0 \n"
417 " beqzl %1, 1b \n"
418 " nop \n"
419 __WEAK_LLSC_MB
420 " li %2, 1 \n"
421 " .set reorder \n"
422 "2: \n"
423 : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
424 : "m" (rw->lock)
425 : "memory");
426 } else {
427 __asm__ __volatile__(
428 " .set noreorder # arch_write_trylock \n"
429 " li %2, 0 \n"
430 "1: ll %1, %3 \n"
431 " bnez %1, 2f \n"
432 " lui %1, 0x8000 \n"
433 " sc %1, %0 \n"
434 " beqz %1, 3f \n"
435 " li %2, 1 \n"
436 "2: \n"
437 __WEAK_LLSC_MB
438 " .subsection 2 \n"
439 "3: b 1b \n"
440 " li %2, 0 \n"
441 " .previous \n"
442 " .set reorder \n"
443 : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
444 : "m" (rw->lock)
445 : "memory");
446 }
447
448 return ret;
449}
450
451#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
452#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
453
454#define arch_spin_relax(lock) cpu_relax()
455#define arch_read_relax(lock) cpu_relax()
456#define arch_write_relax(lock) cpu_relax()
457
458#endif /* _ASM_SPINLOCK_H */
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999, 2000, 06 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 */
9#ifndef _ASM_SPINLOCK_H
10#define _ASM_SPINLOCK_H
11
12#include <linux/compiler.h>
13
14#include <asm/barrier.h>
15#include <asm/compiler.h>
16#include <asm/war.h>
17
18/*
19 * Your basic SMP spinlocks, allowing only a single CPU anywhere
20 *
21 * Simple spin lock operations. There are two variants, one clears IRQ's
22 * on the local processor, one does not.
23 *
24 * These are fair FIFO ticket locks
25 *
26 * (the type definitions are in asm/spinlock_types.h)
27 */
28
29
30/*
31 * Ticket locks are conceptually two parts, one indicating the current head of
32 * the queue, and the other indicating the current tail. The lock is acquired
33 * by atomically noting the tail and incrementing it by one (thus adding
34 * ourself to the queue and noting our position), then waiting until the head
35 * becomes equal to the the initial value of the tail.
36 */
37
38static inline int arch_spin_is_locked(arch_spinlock_t *lock)
39{
40 u32 counters = ACCESS_ONCE(lock->lock);
41
42 return ((counters >> 16) ^ counters) & 0xffff;
43}
44
45static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
46{
47 return lock.h.serving_now == lock.h.ticket;
48}
49
50#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
51#define arch_spin_unlock_wait(x) \
52 while (arch_spin_is_locked(x)) { cpu_relax(); }
53
54static inline int arch_spin_is_contended(arch_spinlock_t *lock)
55{
56 u32 counters = ACCESS_ONCE(lock->lock);
57
58 return (((counters >> 16) - counters) & 0xffff) > 1;
59}
60#define arch_spin_is_contended arch_spin_is_contended
61
62static inline void arch_spin_lock(arch_spinlock_t *lock)
63{
64 int my_ticket;
65 int tmp;
66 int inc = 0x10000;
67
68 if (R10000_LLSC_WAR) {
69 __asm__ __volatile__ (
70 " .set push # arch_spin_lock \n"
71 " .set noreorder \n"
72 " \n"
73 "1: ll %[ticket], %[ticket_ptr] \n"
74 " addu %[my_ticket], %[ticket], %[inc] \n"
75 " sc %[my_ticket], %[ticket_ptr] \n"
76 " beqzl %[my_ticket], 1b \n"
77 " nop \n"
78 " srl %[my_ticket], %[ticket], 16 \n"
79 " andi %[ticket], %[ticket], 0xffff \n"
80 " bne %[ticket], %[my_ticket], 4f \n"
81 " subu %[ticket], %[my_ticket], %[ticket] \n"
82 "2: \n"
83 " .subsection 2 \n"
84 "4: andi %[ticket], %[ticket], 0xffff \n"
85 " sll %[ticket], 5 \n"
86 " \n"
87 "6: bnez %[ticket], 6b \n"
88 " subu %[ticket], 1 \n"
89 " \n"
90 " lhu %[ticket], %[serving_now_ptr] \n"
91 " beq %[ticket], %[my_ticket], 2b \n"
92 " subu %[ticket], %[my_ticket], %[ticket] \n"
93 " b 4b \n"
94 " subu %[ticket], %[ticket], 1 \n"
95 " .previous \n"
96 " .set pop \n"
97 : [ticket_ptr] "+" GCC_OFF_SMALL_ASM() (lock->lock),
98 [serving_now_ptr] "+m" (lock->h.serving_now),
99 [ticket] "=&r" (tmp),
100 [my_ticket] "=&r" (my_ticket)
101 : [inc] "r" (inc));
102 } else {
103 __asm__ __volatile__ (
104 " .set push # arch_spin_lock \n"
105 " .set noreorder \n"
106 " \n"
107 "1: ll %[ticket], %[ticket_ptr] \n"
108 " addu %[my_ticket], %[ticket], %[inc] \n"
109 " sc %[my_ticket], %[ticket_ptr] \n"
110 " beqz %[my_ticket], 1b \n"
111 " srl %[my_ticket], %[ticket], 16 \n"
112 " andi %[ticket], %[ticket], 0xffff \n"
113 " bne %[ticket], %[my_ticket], 4f \n"
114 " subu %[ticket], %[my_ticket], %[ticket] \n"
115 "2: \n"
116 " .subsection 2 \n"
117 "4: andi %[ticket], %[ticket], 0xffff \n"
118 " sll %[ticket], 5 \n"
119 " \n"
120 "6: bnez %[ticket], 6b \n"
121 " subu %[ticket], 1 \n"
122 " \n"
123 " lhu %[ticket], %[serving_now_ptr] \n"
124 " beq %[ticket], %[my_ticket], 2b \n"
125 " subu %[ticket], %[my_ticket], %[ticket] \n"
126 " b 4b \n"
127 " subu %[ticket], %[ticket], 1 \n"
128 " .previous \n"
129 " .set pop \n"
130 : [ticket_ptr] "+" GCC_OFF_SMALL_ASM() (lock->lock),
131 [serving_now_ptr] "+m" (lock->h.serving_now),
132 [ticket] "=&r" (tmp),
133 [my_ticket] "=&r" (my_ticket)
134 : [inc] "r" (inc));
135 }
136
137 smp_llsc_mb();
138}
139
140static inline void arch_spin_unlock(arch_spinlock_t *lock)
141{
142 unsigned int serving_now = lock->h.serving_now + 1;
143 wmb();
144 lock->h.serving_now = (u16)serving_now;
145 nudge_writes();
146}
147
148static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock)
149{
150 int tmp, tmp2, tmp3;
151 int inc = 0x10000;
152
153 if (R10000_LLSC_WAR) {
154 __asm__ __volatile__ (
155 " .set push # arch_spin_trylock \n"
156 " .set noreorder \n"
157 " \n"
158 "1: ll %[ticket], %[ticket_ptr] \n"
159 " srl %[my_ticket], %[ticket], 16 \n"
160 " andi %[now_serving], %[ticket], 0xffff \n"
161 " bne %[my_ticket], %[now_serving], 3f \n"
162 " addu %[ticket], %[ticket], %[inc] \n"
163 " sc %[ticket], %[ticket_ptr] \n"
164 " beqzl %[ticket], 1b \n"
165 " li %[ticket], 1 \n"
166 "2: \n"
167 " .subsection 2 \n"
168 "3: b 2b \n"
169 " li %[ticket], 0 \n"
170 " .previous \n"
171 " .set pop \n"
172 : [ticket_ptr] "+" GCC_OFF_SMALL_ASM() (lock->lock),
173 [ticket] "=&r" (tmp),
174 [my_ticket] "=&r" (tmp2),
175 [now_serving] "=&r" (tmp3)
176 : [inc] "r" (inc));
177 } else {
178 __asm__ __volatile__ (
179 " .set push # arch_spin_trylock \n"
180 " .set noreorder \n"
181 " \n"
182 "1: ll %[ticket], %[ticket_ptr] \n"
183 " srl %[my_ticket], %[ticket], 16 \n"
184 " andi %[now_serving], %[ticket], 0xffff \n"
185 " bne %[my_ticket], %[now_serving], 3f \n"
186 " addu %[ticket], %[ticket], %[inc] \n"
187 " sc %[ticket], %[ticket_ptr] \n"
188 " beqz %[ticket], 1b \n"
189 " li %[ticket], 1 \n"
190 "2: \n"
191 " .subsection 2 \n"
192 "3: b 2b \n"
193 " li %[ticket], 0 \n"
194 " .previous \n"
195 " .set pop \n"
196 : [ticket_ptr] "+" GCC_OFF_SMALL_ASM() (lock->lock),
197 [ticket] "=&r" (tmp),
198 [my_ticket] "=&r" (tmp2),
199 [now_serving] "=&r" (tmp3)
200 : [inc] "r" (inc));
201 }
202
203 smp_llsc_mb();
204
205 return tmp;
206}
207
208/*
209 * Read-write spinlocks, allowing multiple readers but only one writer.
210 *
211 * NOTE! it is quite common to have readers in interrupts but no interrupt
212 * writers. For those circumstances we can "mix" irq-safe locks - any writer
213 * needs to get a irq-safe write-lock, but readers can get non-irqsafe
214 * read-locks.
215 */
216
217/*
218 * read_can_lock - would read_trylock() succeed?
219 * @lock: the rwlock in question.
220 */
221#define arch_read_can_lock(rw) ((rw)->lock >= 0)
222
223/*
224 * write_can_lock - would write_trylock() succeed?
225 * @lock: the rwlock in question.
226 */
227#define arch_write_can_lock(rw) (!(rw)->lock)
228
229static inline void arch_read_lock(arch_rwlock_t *rw)
230{
231 unsigned int tmp;
232
233 if (R10000_LLSC_WAR) {
234 __asm__ __volatile__(
235 " .set noreorder # arch_read_lock \n"
236 "1: ll %1, %2 \n"
237 " bltz %1, 1b \n"
238 " addu %1, 1 \n"
239 " sc %1, %0 \n"
240 " beqzl %1, 1b \n"
241 " nop \n"
242 " .set reorder \n"
243 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
244 : GCC_OFF_SMALL_ASM() (rw->lock)
245 : "memory");
246 } else {
247 do {
248 __asm__ __volatile__(
249 "1: ll %1, %2 # arch_read_lock \n"
250 " bltz %1, 1b \n"
251 " addu %1, 1 \n"
252 "2: sc %1, %0 \n"
253 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
254 : GCC_OFF_SMALL_ASM() (rw->lock)
255 : "memory");
256 } while (unlikely(!tmp));
257 }
258
259 smp_llsc_mb();
260}
261
262static inline void arch_read_unlock(arch_rwlock_t *rw)
263{
264 unsigned int tmp;
265
266 smp_mb__before_llsc();
267
268 if (R10000_LLSC_WAR) {
269 __asm__ __volatile__(
270 "1: ll %1, %2 # arch_read_unlock \n"
271 " addiu %1, -1 \n"
272 " sc %1, %0 \n"
273 " beqzl %1, 1b \n"
274 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
275 : GCC_OFF_SMALL_ASM() (rw->lock)
276 : "memory");
277 } else {
278 do {
279 __asm__ __volatile__(
280 "1: ll %1, %2 # arch_read_unlock \n"
281 " addiu %1, -1 \n"
282 " sc %1, %0 \n"
283 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
284 : GCC_OFF_SMALL_ASM() (rw->lock)
285 : "memory");
286 } while (unlikely(!tmp));
287 }
288}
289
290static inline void arch_write_lock(arch_rwlock_t *rw)
291{
292 unsigned int tmp;
293
294 if (R10000_LLSC_WAR) {
295 __asm__ __volatile__(
296 " .set noreorder # arch_write_lock \n"
297 "1: ll %1, %2 \n"
298 " bnez %1, 1b \n"
299 " lui %1, 0x8000 \n"
300 " sc %1, %0 \n"
301 " beqzl %1, 1b \n"
302 " nop \n"
303 " .set reorder \n"
304 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
305 : GCC_OFF_SMALL_ASM() (rw->lock)
306 : "memory");
307 } else {
308 do {
309 __asm__ __volatile__(
310 "1: ll %1, %2 # arch_write_lock \n"
311 " bnez %1, 1b \n"
312 " lui %1, 0x8000 \n"
313 "2: sc %1, %0 \n"
314 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
315 : GCC_OFF_SMALL_ASM() (rw->lock)
316 : "memory");
317 } while (unlikely(!tmp));
318 }
319
320 smp_llsc_mb();
321}
322
323static inline void arch_write_unlock(arch_rwlock_t *rw)
324{
325 smp_mb__before_llsc();
326
327 __asm__ __volatile__(
328 " # arch_write_unlock \n"
329 " sw $0, %0 \n"
330 : "=m" (rw->lock)
331 : "m" (rw->lock)
332 : "memory");
333}
334
335static inline int arch_read_trylock(arch_rwlock_t *rw)
336{
337 unsigned int tmp;
338 int ret;
339
340 if (R10000_LLSC_WAR) {
341 __asm__ __volatile__(
342 " .set noreorder # arch_read_trylock \n"
343 " li %2, 0 \n"
344 "1: ll %1, %3 \n"
345 " bltz %1, 2f \n"
346 " addu %1, 1 \n"
347 " sc %1, %0 \n"
348 " .set reorder \n"
349 " beqzl %1, 1b \n"
350 " nop \n"
351 __WEAK_LLSC_MB
352 " li %2, 1 \n"
353 "2: \n"
354 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret)
355 : GCC_OFF_SMALL_ASM() (rw->lock)
356 : "memory");
357 } else {
358 __asm__ __volatile__(
359 " .set noreorder # arch_read_trylock \n"
360 " li %2, 0 \n"
361 "1: ll %1, %3 \n"
362 " bltz %1, 2f \n"
363 " addu %1, 1 \n"
364 " sc %1, %0 \n"
365 " beqz %1, 1b \n"
366 " nop \n"
367 " .set reorder \n"
368 __WEAK_LLSC_MB
369 " li %2, 1 \n"
370 "2: \n"
371 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret)
372 : GCC_OFF_SMALL_ASM() (rw->lock)
373 : "memory");
374 }
375
376 return ret;
377}
378
379static inline int arch_write_trylock(arch_rwlock_t *rw)
380{
381 unsigned int tmp;
382 int ret;
383
384 if (R10000_LLSC_WAR) {
385 __asm__ __volatile__(
386 " .set noreorder # arch_write_trylock \n"
387 " li %2, 0 \n"
388 "1: ll %1, %3 \n"
389 " bnez %1, 2f \n"
390 " lui %1, 0x8000 \n"
391 " sc %1, %0 \n"
392 " beqzl %1, 1b \n"
393 " nop \n"
394 __WEAK_LLSC_MB
395 " li %2, 1 \n"
396 " .set reorder \n"
397 "2: \n"
398 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret)
399 : GCC_OFF_SMALL_ASM() (rw->lock)
400 : "memory");
401 } else {
402 do {
403 __asm__ __volatile__(
404 " ll %1, %3 # arch_write_trylock \n"
405 " li %2, 0 \n"
406 " bnez %1, 2f \n"
407 " lui %1, 0x8000 \n"
408 " sc %1, %0 \n"
409 " li %2, 1 \n"
410 "2: \n"
411 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp),
412 "=&r" (ret)
413 : GCC_OFF_SMALL_ASM() (rw->lock)
414 : "memory");
415 } while (unlikely(!tmp));
416
417 smp_llsc_mb();
418 }
419
420 return ret;
421}
422
423#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
424#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
425
426#define arch_spin_relax(lock) cpu_relax()
427#define arch_read_relax(lock) cpu_relax()
428#define arch_write_relax(lock) cpu_relax()
429
430#endif /* _ASM_SPINLOCK_H */