1/*
  2 * Copyright (c) 2011 Broadcom Corporation
  3 *
  4 * Permission to use, copy, modify, and/or distribute this software for any
  5 * purpose with or without fee is hereby granted, provided that the above
  6 * copyright notice and this permission notice appear in all copies.
  7 *
  8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 15 */
 16
 17#ifndef	_BRCM_AIUTILS_H_
 18#define	_BRCM_AIUTILS_H_
 19
 20#include <linux/bcma/bcma.h>
 21
 22#include "types.h"
 23
 24/*
 25 * SOC Interconnect Address Map.
 26 * All regions may not exist on all chips.
 27 */
 28/* each core gets 4Kbytes for registers */
 29#define SI_CORE_SIZE		0x1000
 30/*
 31 * Max cores (this is arbitrary, for software
 32 * convenience and could be changed if we
 33 * make any larger chips
 34 */
 35#define	SI_MAXCORES		16
 36
 37/* Client Mode sb2pcitranslation2 size in bytes */
 38#define SI_PCI_DMA_SZ		0x40000000
 39
 40/* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
 41#define SI_PCIE_DMA_H32		0x80000000
 42
 43/* chipcommon being the first core: */
 44#define	SI_CC_IDX		0
 45
 46/* SOC Interconnect types (aka chip types) */
 47#define	SOCI_AI			1
 48
 49/* A register that is common to all cores to
 50 * communicate w/PMU regarding clock control.
 51 */
 52#define SI_CLK_CTL_ST		0x1e0	/* clock control and status */
 53
 54/* clk_ctl_st register */
 55#define	CCS_FORCEALP		0x00000001	/* force ALP request */
 56#define	CCS_FORCEHT		0x00000002	/* force HT request */
 57#define	CCS_FORCEILP		0x00000004	/* force ILP request */
 58#define	CCS_ALPAREQ		0x00000008	/* ALP Avail Request */
 59#define	CCS_HTAREQ		0x00000010	/* HT Avail Request */
 60#define	CCS_FORCEHWREQOFF	0x00000020	/* Force HW Clock Request Off */
 61#define CCS_ERSRC_REQ_MASK	0x00000700	/* external resource requests */
 62#define CCS_ERSRC_REQ_SHIFT	8
 63#define	CCS_ALPAVAIL		0x00010000	/* ALP is available */
 64#define	CCS_HTAVAIL		0x00020000	/* HT is available */
 65#define CCS_BP_ON_APL		0x00040000	/* RO: running on ALP clock */
 66#define CCS_BP_ON_HT		0x00080000	/* RO: running on HT clock */
 67#define CCS_ERSRC_STS_MASK	0x07000000	/* external resource status */
 68#define CCS_ERSRC_STS_SHIFT	24
 69
 70/* HT avail in chipc and pcmcia on 4328a0 */
 71#define	CCS0_HTAVAIL		0x00010000
 72/* ALP avail in chipc and pcmcia on 4328a0 */
 73#define	CCS0_ALPAVAIL		0x00020000
 74
 75/* Not really related to SOC Interconnect, but a couple of software
 76 * conventions for the use the flash space:
 77 */
 78
 79/* Minumum amount of flash we support */
 80#define FLASH_MIN		0x00020000	/* Minimum flash size */
 81
 82#define	CC_SROM_OTP		0x800	/* SROM/OTP address space */
 83
 84/* gpiotimerval */
 85#define GPIO_ONTIME_SHIFT	16
 86
 87/* Fields in clkdiv */
 88#define	CLKD_OTP		0x000f0000
 89#define	CLKD_OTP_SHIFT		16
 90
 91/* Package IDs */
 92#define	BCM4717_PKG_ID		9	/* 4717 package id */
 93#define	BCM4718_PKG_ID		10	/* 4718 package id */
 94#define BCM43224_FAB_SMIC	0xa	/* the chip is manufactured by SMIC */
 95
 96/* these are router chips */
 97#define	BCM4716_CHIP_ID		0x4716	/* 4716 chipcommon chipid */
 98#define	BCM47162_CHIP_ID	47162	/* 47162 chipcommon chipid */
 99#define	BCM4748_CHIP_ID		0x4748	/* 4716 chipcommon chipid (OTP, RBBU) */
100
101/* dynamic clock control defines */
102#define	LPOMINFREQ		25000	/* low power oscillator min */
103#define	LPOMAXFREQ		43000	/* low power oscillator max */
104#define	XTALMINFREQ		19800000	/* 20 MHz - 1% */
105#define	XTALMAXFREQ		20200000	/* 20 MHz + 1% */
106#define	PCIMINFREQ		25000000	/* 25 MHz */
107#define	PCIMAXFREQ		34000000	/* 33 MHz + fudge */
108
109#define	ILP_DIV_5MHZ		0	/* ILP = 5 MHz */
110#define	ILP_DIV_1MHZ		4	/* ILP = 1 MHz */
111
112/* clkctl xtal what flags */
113#define	XTAL			0x1	/* primary crystal oscillator (2050) */
114#define	PLL			0x2	/* main chip pll */
115
116/* GPIO usage priorities */
117#define GPIO_DRV_PRIORITY	0	/* Driver */
118#define GPIO_APP_PRIORITY	1	/* Application */
119#define GPIO_HI_PRIORITY	2	/* Highest priority. Ignore GPIO
120					 * reservation
121					 */
122
123/* GPIO pull up/down */
124#define GPIO_PULLUP		0
125#define GPIO_PULLDN		1
126
127/* GPIO event regtype */
128#define GPIO_REGEVT		0	/* GPIO register event */
129#define GPIO_REGEVT_INTMSK	1	/* GPIO register event int mask */
130#define GPIO_REGEVT_INTPOL	2	/* GPIO register event int polarity */
131
132/* device path */
133#define SI_DEVPATH_BUFSZ	16	/* min buffer size in bytes */
134
135/* SI routine enumeration: to be used by update function with multiple hooks */
136#define	SI_DOATTACH	1
137#define SI_PCIDOWN	2
138#define SI_PCIUP	3
139
140/*
141 * Data structure to export all chip specific common variables
142 *   public (read-only) portion of aiutils handle returned by si_attach()
143 */
144struct si_pub {
145	int ccrev;		/* chip common core rev */
146	u32 cccaps;		/* chip common capabilities */
147	int pmurev;		/* pmu core rev */
148	u32 pmucaps;		/* pmu capabilities */
149	uint boardtype;		/* board type */
150	uint boardvendor;	/* board vendor */
151	uint chip;		/* chip number */
152	uint chiprev;		/* chip revision */
153	uint chippkg;		/* chip package option */
154};
155
156struct pci_dev;
157
158struct gpioh_item {
159	void *arg;
160	bool level;
161	void (*handler) (u32 stat, void *arg);
162	u32 event;
163	struct gpioh_item *next;
164};
165
166/* misc si info needed by some of the routines */
167struct si_info {
168	struct si_pub pub;	/* back plane public state (must be first) */
169	struct bcma_bus *icbus;	/* handle to soc interconnect bus */
170	struct pci_dev *pcibus;	/* handle to pci bus */
171	struct bcma_device *buscore;
172
173	u32 chipst;		/* chip status */
174};
175
176/*
177 * Many of the routines below take an 'sih' handle as their first arg.
178 * Allocate this by calling si_attach().  Free it by calling si_detach().
179 * At any one time, the sih is logically focused on one particular si core
180 * (the "current core").
181 * Use si_setcore() or si_setcoreidx() to change the association to another core
182 */
183
184
185/* AMBA Interconnect exported externs */
186extern struct bcma_device *ai_findcore(struct si_pub *sih,
187				       u16 coreid, u16 coreunit);
188extern u32 ai_core_cflags(struct bcma_device *core, u32 mask, u32 val);
189
190/* === exported functions === */
191extern struct si_pub *ai_attach(struct bcma_bus *pbus);
192extern void ai_detach(struct si_pub *sih);
193extern uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val);
194extern void ai_clkctl_init(struct si_pub *sih);
195extern u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih);
196extern bool ai_clkctl_cc(struct si_pub *sih, uint mode);
197extern bool ai_deviceremoved(struct si_pub *sih);
198
199extern void ai_pci_down(struct si_pub *sih);
200extern void ai_pci_up(struct si_pub *sih);
201
202/* Enable Ex-PA for 4313 */
203extern void ai_epa_4313war(struct si_pub *sih);
204
205extern uint ai_get_buscoretype(struct si_pub *sih);
206extern uint ai_get_buscorerev(struct si_pub *sih);
207
208static inline u32 ai_get_cccaps(struct si_pub *sih)
209{
210	return sih->cccaps;
211}
212
213static inline int ai_get_pmurev(struct si_pub *sih)
214{
215	return sih->pmurev;
216}
217
218static inline u32 ai_get_pmucaps(struct si_pub *sih)
219{
220	return sih->pmucaps;
221}
222
223static inline uint ai_get_boardtype(struct si_pub *sih)
224{
225	return sih->boardtype;
226}
227
228static inline uint ai_get_boardvendor(struct si_pub *sih)
229{
230	return sih->boardvendor;
231}
232
233static inline uint ai_get_chip_id(struct si_pub *sih)
234{
235	return sih->chip;
236}
237
238static inline uint ai_get_chiprev(struct si_pub *sih)
239{
240	return sih->chiprev;
241}
242
243static inline uint ai_get_chippkg(struct si_pub *sih)
244{
245	return sih->chippkg;
246}
247
248#endif				/* _BRCM_AIUTILS_H_ */