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1/*
2 * arch/arm/mach-lpc32xx/gpiolib.c
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/errno.h>
23#include <linux/gpio.h>
24#include <linux/of_gpio.h>
25#include <linux/platform_device.h>
26#include <linux/module.h>
27
28#include <mach/hardware.h>
29#include <mach/platform.h>
30#include <mach/gpio-lpc32xx.h>
31
32#define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000)
33#define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004)
34#define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008)
35#define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C)
36#define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010)
37#define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014)
38#define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018)
39#define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C)
40#define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020)
41#define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024)
42#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028)
43#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C)
44#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030)
45#define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040)
46#define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044)
47#define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048)
48#define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C)
49#define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050)
50#define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054)
51#define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058)
52#define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060)
53#define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064)
54#define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068)
55#define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C)
56#define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070)
57#define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074)
58#define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078)
59
60#define GPIO012_PIN_TO_BIT(x) (1 << (x))
61#define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25))
62#define GPO3_PIN_TO_BIT(x) (1 << (x))
63#define GPIO012_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
64#define GPIO3_PIN_IN_SHIFT(x) ((x) == 5 ? 24 : 10 + (x))
65#define GPIO3_PIN_IN_SEL(x, y) (((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1)
66#define GPIO3_PIN5_IN_SEL(x) (((x) >> 24) & 1)
67#define GPI3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
68#define GPO3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
69
70struct gpio_regs {
71 void __iomem *inp_state;
72 void __iomem *outp_state;
73 void __iomem *outp_set;
74 void __iomem *outp_clr;
75 void __iomem *dir_set;
76 void __iomem *dir_clr;
77};
78
79/*
80 * GPIO names
81 */
82static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = {
83 "p0.0", "p0.1", "p0.2", "p0.3",
84 "p0.4", "p0.5", "p0.6", "p0.7"
85};
86
87static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = {
88 "p1.0", "p1.1", "p1.2", "p1.3",
89 "p1.4", "p1.5", "p1.6", "p1.7",
90 "p1.8", "p1.9", "p1.10", "p1.11",
91 "p1.12", "p1.13", "p1.14", "p1.15",
92 "p1.16", "p1.17", "p1.18", "p1.19",
93 "p1.20", "p1.21", "p1.22", "p1.23",
94};
95
96static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = {
97 "p2.0", "p2.1", "p2.2", "p2.3",
98 "p2.4", "p2.5", "p2.6", "p2.7",
99 "p2.8", "p2.9", "p2.10", "p2.11",
100 "p2.12"
101};
102
103static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = {
104 "gpio00", "gpio01", "gpio02", "gpio03",
105 "gpio04", "gpio05"
106};
107
108static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = {
109 "gpi00", "gpi01", "gpi02", "gpi03",
110 "gpi04", "gpi05", "gpi06", "gpi07",
111 "gpi08", "gpi09", NULL, NULL,
112 NULL, NULL, NULL, "gpi15",
113 "gpi16", "gpi17", "gpi18", "gpi19",
114 "gpi20", "gpi21", "gpi22", "gpi23",
115 "gpi24", "gpi25", "gpi26", "gpi27"
116};
117
118static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = {
119 "gpo00", "gpo01", "gpo02", "gpo03",
120 "gpo04", "gpo05", "gpo06", "gpo07",
121 "gpo08", "gpo09", "gpo10", "gpo11",
122 "gpo12", "gpo13", "gpo14", "gpo15",
123 "gpo16", "gpo17", "gpo18", "gpo19",
124 "gpo20", "gpo21", "gpo22", "gpo23"
125};
126
127static struct gpio_regs gpio_grp_regs_p0 = {
128 .inp_state = LPC32XX_GPIO_P0_INP_STATE,
129 .outp_set = LPC32XX_GPIO_P0_OUTP_SET,
130 .outp_clr = LPC32XX_GPIO_P0_OUTP_CLR,
131 .dir_set = LPC32XX_GPIO_P0_DIR_SET,
132 .dir_clr = LPC32XX_GPIO_P0_DIR_CLR,
133};
134
135static struct gpio_regs gpio_grp_regs_p1 = {
136 .inp_state = LPC32XX_GPIO_P1_INP_STATE,
137 .outp_set = LPC32XX_GPIO_P1_OUTP_SET,
138 .outp_clr = LPC32XX_GPIO_P1_OUTP_CLR,
139 .dir_set = LPC32XX_GPIO_P1_DIR_SET,
140 .dir_clr = LPC32XX_GPIO_P1_DIR_CLR,
141};
142
143static struct gpio_regs gpio_grp_regs_p2 = {
144 .inp_state = LPC32XX_GPIO_P2_INP_STATE,
145 .outp_set = LPC32XX_GPIO_P2_OUTP_SET,
146 .outp_clr = LPC32XX_GPIO_P2_OUTP_CLR,
147 .dir_set = LPC32XX_GPIO_P2_DIR_SET,
148 .dir_clr = LPC32XX_GPIO_P2_DIR_CLR,
149};
150
151static struct gpio_regs gpio_grp_regs_p3 = {
152 .inp_state = LPC32XX_GPIO_P3_INP_STATE,
153 .outp_state = LPC32XX_GPIO_P3_OUTP_STATE,
154 .outp_set = LPC32XX_GPIO_P3_OUTP_SET,
155 .outp_clr = LPC32XX_GPIO_P3_OUTP_CLR,
156 .dir_set = LPC32XX_GPIO_P2_DIR_SET,
157 .dir_clr = LPC32XX_GPIO_P2_DIR_CLR,
158};
159
160struct lpc32xx_gpio_chip {
161 struct gpio_chip chip;
162 struct gpio_regs *gpio_grp;
163};
164
165static inline struct lpc32xx_gpio_chip *to_lpc32xx_gpio(
166 struct gpio_chip *gpc)
167{
168 return container_of(gpc, struct lpc32xx_gpio_chip, chip);
169}
170
171static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
172 unsigned pin, int input)
173{
174 if (input)
175 __raw_writel(GPIO012_PIN_TO_BIT(pin),
176 group->gpio_grp->dir_clr);
177 else
178 __raw_writel(GPIO012_PIN_TO_BIT(pin),
179 group->gpio_grp->dir_set);
180}
181
182static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
183 unsigned pin, int input)
184{
185 u32 u = GPIO3_PIN_TO_BIT(pin);
186
187 if (input)
188 __raw_writel(u, group->gpio_grp->dir_clr);
189 else
190 __raw_writel(u, group->gpio_grp->dir_set);
191}
192
193static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
194 unsigned pin, int high)
195{
196 if (high)
197 __raw_writel(GPIO012_PIN_TO_BIT(pin),
198 group->gpio_grp->outp_set);
199 else
200 __raw_writel(GPIO012_PIN_TO_BIT(pin),
201 group->gpio_grp->outp_clr);
202}
203
204static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
205 unsigned pin, int high)
206{
207 u32 u = GPIO3_PIN_TO_BIT(pin);
208
209 if (high)
210 __raw_writel(u, group->gpio_grp->outp_set);
211 else
212 __raw_writel(u, group->gpio_grp->outp_clr);
213}
214
215static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
216 unsigned pin, int high)
217{
218 if (high)
219 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
220 else
221 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
222}
223
224static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
225 unsigned pin)
226{
227 return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
228 pin);
229}
230
231static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
232 unsigned pin)
233{
234 int state = __raw_readl(group->gpio_grp->inp_state);
235
236 /*
237 * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
238 * to bits 10..14, while GPIOP3-5 is mapped to bit 24.
239 */
240 return GPIO3_PIN_IN_SEL(state, pin);
241}
242
243static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
244 unsigned pin)
245{
246 return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
247}
248
249static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
250 unsigned pin)
251{
252 return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin);
253}
254
255/*
256 * GENERIC_GPIO primitives.
257 */
258static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip,
259 unsigned pin)
260{
261 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
262
263 __set_gpio_dir_p012(group, pin, 1);
264
265 return 0;
266}
267
268static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip,
269 unsigned pin)
270{
271 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
272
273 __set_gpio_dir_p3(group, pin, 1);
274
275 return 0;
276}
277
278static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip,
279 unsigned pin)
280{
281 return 0;
282}
283
284static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin)
285{
286 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
287
288 return __get_gpio_state_p012(group, pin);
289}
290
291static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin)
292{
293 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
294
295 return __get_gpio_state_p3(group, pin);
296}
297
298static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin)
299{
300 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
301
302 return __get_gpi_state_p3(group, pin);
303}
304
305static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin,
306 int value)
307{
308 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
309
310 __set_gpio_level_p012(group, pin, value);
311 __set_gpio_dir_p012(group, pin, 0);
312
313 return 0;
314}
315
316static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin,
317 int value)
318{
319 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
320
321 __set_gpio_level_p3(group, pin, value);
322 __set_gpio_dir_p3(group, pin, 0);
323
324 return 0;
325}
326
327static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin,
328 int value)
329{
330 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
331
332 __set_gpo_level_p3(group, pin, value);
333 return 0;
334}
335
336static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin,
337 int value)
338{
339 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
340
341 __set_gpio_level_p012(group, pin, value);
342}
343
344static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin,
345 int value)
346{
347 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
348
349 __set_gpio_level_p3(group, pin, value);
350}
351
352static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin,
353 int value)
354{
355 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
356
357 __set_gpo_level_p3(group, pin, value);
358}
359
360static int lpc32xx_gpo_get_value(struct gpio_chip *chip, unsigned pin)
361{
362 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
363
364 return __get_gpo_state_p3(group, pin);
365}
366
367static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin)
368{
369 if (pin < chip->ngpio)
370 return 0;
371
372 return -EINVAL;
373}
374
375static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
376 {
377 .chip = {
378 .label = "gpio_p0",
379 .direction_input = lpc32xx_gpio_dir_input_p012,
380 .get = lpc32xx_gpio_get_value_p012,
381 .direction_output = lpc32xx_gpio_dir_output_p012,
382 .set = lpc32xx_gpio_set_value_p012,
383 .request = lpc32xx_gpio_request,
384 .base = LPC32XX_GPIO_P0_GRP,
385 .ngpio = LPC32XX_GPIO_P0_MAX,
386 .names = gpio_p0_names,
387 .can_sleep = 0,
388 },
389 .gpio_grp = &gpio_grp_regs_p0,
390 },
391 {
392 .chip = {
393 .label = "gpio_p1",
394 .direction_input = lpc32xx_gpio_dir_input_p012,
395 .get = lpc32xx_gpio_get_value_p012,
396 .direction_output = lpc32xx_gpio_dir_output_p012,
397 .set = lpc32xx_gpio_set_value_p012,
398 .request = lpc32xx_gpio_request,
399 .base = LPC32XX_GPIO_P1_GRP,
400 .ngpio = LPC32XX_GPIO_P1_MAX,
401 .names = gpio_p1_names,
402 .can_sleep = 0,
403 },
404 .gpio_grp = &gpio_grp_regs_p1,
405 },
406 {
407 .chip = {
408 .label = "gpio_p2",
409 .direction_input = lpc32xx_gpio_dir_input_p012,
410 .get = lpc32xx_gpio_get_value_p012,
411 .direction_output = lpc32xx_gpio_dir_output_p012,
412 .set = lpc32xx_gpio_set_value_p012,
413 .request = lpc32xx_gpio_request,
414 .base = LPC32XX_GPIO_P2_GRP,
415 .ngpio = LPC32XX_GPIO_P2_MAX,
416 .names = gpio_p2_names,
417 .can_sleep = 0,
418 },
419 .gpio_grp = &gpio_grp_regs_p2,
420 },
421 {
422 .chip = {
423 .label = "gpio_p3",
424 .direction_input = lpc32xx_gpio_dir_input_p3,
425 .get = lpc32xx_gpio_get_value_p3,
426 .direction_output = lpc32xx_gpio_dir_output_p3,
427 .set = lpc32xx_gpio_set_value_p3,
428 .request = lpc32xx_gpio_request,
429 .base = LPC32XX_GPIO_P3_GRP,
430 .ngpio = LPC32XX_GPIO_P3_MAX,
431 .names = gpio_p3_names,
432 .can_sleep = 0,
433 },
434 .gpio_grp = &gpio_grp_regs_p3,
435 },
436 {
437 .chip = {
438 .label = "gpi_p3",
439 .direction_input = lpc32xx_gpio_dir_in_always,
440 .get = lpc32xx_gpi_get_value,
441 .request = lpc32xx_gpio_request,
442 .base = LPC32XX_GPI_P3_GRP,
443 .ngpio = LPC32XX_GPI_P3_MAX,
444 .names = gpi_p3_names,
445 .can_sleep = 0,
446 },
447 .gpio_grp = &gpio_grp_regs_p3,
448 },
449 {
450 .chip = {
451 .label = "gpo_p3",
452 .direction_output = lpc32xx_gpio_dir_out_always,
453 .set = lpc32xx_gpo_set_value,
454 .get = lpc32xx_gpo_get_value,
455 .request = lpc32xx_gpio_request,
456 .base = LPC32XX_GPO_P3_GRP,
457 .ngpio = LPC32XX_GPO_P3_MAX,
458 .names = gpo_p3_names,
459 .can_sleep = 0,
460 },
461 .gpio_grp = &gpio_grp_regs_p3,
462 },
463};
464
465/* Empty now, can be removed later when mach-lpc32xx is finally switched over
466 * to DT support
467 */
468void __init lpc32xx_gpio_init(void)
469{
470}
471
472static int lpc32xx_of_xlate(struct gpio_chip *gc,
473 const struct of_phandle_args *gpiospec, u32 *flags)
474{
475 /* Is this the correct bank? */
476 u32 bank = gpiospec->args[0];
477 if ((bank > ARRAY_SIZE(lpc32xx_gpiochip) ||
478 (gc != &lpc32xx_gpiochip[bank].chip)))
479 return -EINVAL;
480
481 if (flags)
482 *flags = gpiospec->args[2];
483 return gpiospec->args[1];
484}
485
486static int __devinit lpc32xx_gpio_probe(struct platform_device *pdev)
487{
488 int i;
489
490 for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) {
491 if (pdev->dev.of_node) {
492 lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate;
493 lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3;
494 lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node;
495 }
496 gpiochip_add(&lpc32xx_gpiochip[i].chip);
497 }
498
499 return 0;
500}
501
502#ifdef CONFIG_OF
503static struct of_device_id lpc32xx_gpio_of_match[] __devinitdata = {
504 { .compatible = "nxp,lpc3220-gpio", },
505 { },
506};
507#endif
508
509static struct platform_driver lpc32xx_gpio_driver = {
510 .driver = {
511 .name = "lpc32xx-gpio",
512 .owner = THIS_MODULE,
513 .of_match_table = of_match_ptr(lpc32xx_gpio_of_match),
514 },
515 .probe = lpc32xx_gpio_probe,
516};
517
518module_platform_driver(lpc32xx_gpio_driver);
1/*
2 * GPIO driver for LPC32xx SoC
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/errno.h>
23#include <linux/gpio.h>
24#include <linux/of.h>
25#include <linux/of_gpio.h>
26#include <linux/platform_device.h>
27#include <linux/module.h>
28#include <linux/platform_data/gpio-lpc32xx.h>
29
30#include <mach/hardware.h>
31#include <mach/platform.h>
32#include <mach/irqs.h>
33
34#define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000)
35#define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004)
36#define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008)
37#define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C)
38#define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010)
39#define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014)
40#define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018)
41#define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C)
42#define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020)
43#define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024)
44#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028)
45#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C)
46#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030)
47#define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040)
48#define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044)
49#define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048)
50#define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C)
51#define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050)
52#define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054)
53#define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058)
54#define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060)
55#define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064)
56#define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068)
57#define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C)
58#define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070)
59#define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074)
60#define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078)
61
62#define GPIO012_PIN_TO_BIT(x) (1 << (x))
63#define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25))
64#define GPO3_PIN_TO_BIT(x) (1 << (x))
65#define GPIO012_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
66#define GPIO3_PIN_IN_SHIFT(x) ((x) == 5 ? 24 : 10 + (x))
67#define GPIO3_PIN_IN_SEL(x, y) (((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1)
68#define GPIO3_PIN5_IN_SEL(x) (((x) >> 24) & 1)
69#define GPI3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
70#define GPO3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
71
72struct gpio_regs {
73 void __iomem *inp_state;
74 void __iomem *outp_state;
75 void __iomem *outp_set;
76 void __iomem *outp_clr;
77 void __iomem *dir_set;
78 void __iomem *dir_clr;
79};
80
81/*
82 * GPIO names
83 */
84static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = {
85 "p0.0", "p0.1", "p0.2", "p0.3",
86 "p0.4", "p0.5", "p0.6", "p0.7"
87};
88
89static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = {
90 "p1.0", "p1.1", "p1.2", "p1.3",
91 "p1.4", "p1.5", "p1.6", "p1.7",
92 "p1.8", "p1.9", "p1.10", "p1.11",
93 "p1.12", "p1.13", "p1.14", "p1.15",
94 "p1.16", "p1.17", "p1.18", "p1.19",
95 "p1.20", "p1.21", "p1.22", "p1.23",
96};
97
98static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = {
99 "p2.0", "p2.1", "p2.2", "p2.3",
100 "p2.4", "p2.5", "p2.6", "p2.7",
101 "p2.8", "p2.9", "p2.10", "p2.11",
102 "p2.12"
103};
104
105static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = {
106 "gpio00", "gpio01", "gpio02", "gpio03",
107 "gpio04", "gpio05"
108};
109
110static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = {
111 "gpi00", "gpi01", "gpi02", "gpi03",
112 "gpi04", "gpi05", "gpi06", "gpi07",
113 "gpi08", "gpi09", NULL, NULL,
114 NULL, NULL, NULL, "gpi15",
115 "gpi16", "gpi17", "gpi18", "gpi19",
116 "gpi20", "gpi21", "gpi22", "gpi23",
117 "gpi24", "gpi25", "gpi26", "gpi27",
118 "gpi28"
119};
120
121static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = {
122 "gpo00", "gpo01", "gpo02", "gpo03",
123 "gpo04", "gpo05", "gpo06", "gpo07",
124 "gpo08", "gpo09", "gpo10", "gpo11",
125 "gpo12", "gpo13", "gpo14", "gpo15",
126 "gpo16", "gpo17", "gpo18", "gpo19",
127 "gpo20", "gpo21", "gpo22", "gpo23"
128};
129
130static struct gpio_regs gpio_grp_regs_p0 = {
131 .inp_state = LPC32XX_GPIO_P0_INP_STATE,
132 .outp_set = LPC32XX_GPIO_P0_OUTP_SET,
133 .outp_clr = LPC32XX_GPIO_P0_OUTP_CLR,
134 .dir_set = LPC32XX_GPIO_P0_DIR_SET,
135 .dir_clr = LPC32XX_GPIO_P0_DIR_CLR,
136};
137
138static struct gpio_regs gpio_grp_regs_p1 = {
139 .inp_state = LPC32XX_GPIO_P1_INP_STATE,
140 .outp_set = LPC32XX_GPIO_P1_OUTP_SET,
141 .outp_clr = LPC32XX_GPIO_P1_OUTP_CLR,
142 .dir_set = LPC32XX_GPIO_P1_DIR_SET,
143 .dir_clr = LPC32XX_GPIO_P1_DIR_CLR,
144};
145
146static struct gpio_regs gpio_grp_regs_p2 = {
147 .inp_state = LPC32XX_GPIO_P2_INP_STATE,
148 .outp_set = LPC32XX_GPIO_P2_OUTP_SET,
149 .outp_clr = LPC32XX_GPIO_P2_OUTP_CLR,
150 .dir_set = LPC32XX_GPIO_P2_DIR_SET,
151 .dir_clr = LPC32XX_GPIO_P2_DIR_CLR,
152};
153
154static struct gpio_regs gpio_grp_regs_p3 = {
155 .inp_state = LPC32XX_GPIO_P3_INP_STATE,
156 .outp_state = LPC32XX_GPIO_P3_OUTP_STATE,
157 .outp_set = LPC32XX_GPIO_P3_OUTP_SET,
158 .outp_clr = LPC32XX_GPIO_P3_OUTP_CLR,
159 .dir_set = LPC32XX_GPIO_P2_DIR_SET,
160 .dir_clr = LPC32XX_GPIO_P2_DIR_CLR,
161};
162
163struct lpc32xx_gpio_chip {
164 struct gpio_chip chip;
165 struct gpio_regs *gpio_grp;
166};
167
168static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
169 unsigned pin, int input)
170{
171 if (input)
172 __raw_writel(GPIO012_PIN_TO_BIT(pin),
173 group->gpio_grp->dir_clr);
174 else
175 __raw_writel(GPIO012_PIN_TO_BIT(pin),
176 group->gpio_grp->dir_set);
177}
178
179static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
180 unsigned pin, int input)
181{
182 u32 u = GPIO3_PIN_TO_BIT(pin);
183
184 if (input)
185 __raw_writel(u, group->gpio_grp->dir_clr);
186 else
187 __raw_writel(u, group->gpio_grp->dir_set);
188}
189
190static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
191 unsigned pin, int high)
192{
193 if (high)
194 __raw_writel(GPIO012_PIN_TO_BIT(pin),
195 group->gpio_grp->outp_set);
196 else
197 __raw_writel(GPIO012_PIN_TO_BIT(pin),
198 group->gpio_grp->outp_clr);
199}
200
201static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
202 unsigned pin, int high)
203{
204 u32 u = GPIO3_PIN_TO_BIT(pin);
205
206 if (high)
207 __raw_writel(u, group->gpio_grp->outp_set);
208 else
209 __raw_writel(u, group->gpio_grp->outp_clr);
210}
211
212static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
213 unsigned pin, int high)
214{
215 if (high)
216 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
217 else
218 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
219}
220
221static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
222 unsigned pin)
223{
224 return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
225 pin);
226}
227
228static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
229 unsigned pin)
230{
231 int state = __raw_readl(group->gpio_grp->inp_state);
232
233 /*
234 * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
235 * to bits 10..14, while GPIOP3-5 is mapped to bit 24.
236 */
237 return GPIO3_PIN_IN_SEL(state, pin);
238}
239
240static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
241 unsigned pin)
242{
243 return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
244}
245
246static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
247 unsigned pin)
248{
249 return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin);
250}
251
252/*
253 * GPIO primitives.
254 */
255static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip,
256 unsigned pin)
257{
258 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
259
260 __set_gpio_dir_p012(group, pin, 1);
261
262 return 0;
263}
264
265static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip,
266 unsigned pin)
267{
268 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
269
270 __set_gpio_dir_p3(group, pin, 1);
271
272 return 0;
273}
274
275static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip,
276 unsigned pin)
277{
278 return 0;
279}
280
281static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin)
282{
283 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
284
285 return !!__get_gpio_state_p012(group, pin);
286}
287
288static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin)
289{
290 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
291
292 return !!__get_gpio_state_p3(group, pin);
293}
294
295static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin)
296{
297 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
298
299 return !!__get_gpi_state_p3(group, pin);
300}
301
302static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin,
303 int value)
304{
305 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
306
307 __set_gpio_level_p012(group, pin, value);
308 __set_gpio_dir_p012(group, pin, 0);
309
310 return 0;
311}
312
313static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin,
314 int value)
315{
316 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
317
318 __set_gpio_level_p3(group, pin, value);
319 __set_gpio_dir_p3(group, pin, 0);
320
321 return 0;
322}
323
324static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin,
325 int value)
326{
327 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
328
329 __set_gpo_level_p3(group, pin, value);
330 return 0;
331}
332
333static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin,
334 int value)
335{
336 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
337
338 __set_gpio_level_p012(group, pin, value);
339}
340
341static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin,
342 int value)
343{
344 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
345
346 __set_gpio_level_p3(group, pin, value);
347}
348
349static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin,
350 int value)
351{
352 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
353
354 __set_gpo_level_p3(group, pin, value);
355}
356
357static int lpc32xx_gpo_get_value(struct gpio_chip *chip, unsigned pin)
358{
359 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
360
361 return !!__get_gpo_state_p3(group, pin);
362}
363
364static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin)
365{
366 if (pin < chip->ngpio)
367 return 0;
368
369 return -EINVAL;
370}
371
372static int lpc32xx_gpio_to_irq_p01(struct gpio_chip *chip, unsigned offset)
373{
374 return IRQ_LPC32XX_P0_P1_IRQ;
375}
376
377static const char lpc32xx_gpio_to_irq_gpio_p3_table[] = {
378 IRQ_LPC32XX_GPIO_00,
379 IRQ_LPC32XX_GPIO_01,
380 IRQ_LPC32XX_GPIO_02,
381 IRQ_LPC32XX_GPIO_03,
382 IRQ_LPC32XX_GPIO_04,
383 IRQ_LPC32XX_GPIO_05,
384};
385
386static int lpc32xx_gpio_to_irq_gpio_p3(struct gpio_chip *chip, unsigned offset)
387{
388 if (offset < ARRAY_SIZE(lpc32xx_gpio_to_irq_gpio_p3_table))
389 return lpc32xx_gpio_to_irq_gpio_p3_table[offset];
390 return -ENXIO;
391}
392
393static const char lpc32xx_gpio_to_irq_gpi_p3_table[] = {
394 IRQ_LPC32XX_GPI_00,
395 IRQ_LPC32XX_GPI_01,
396 IRQ_LPC32XX_GPI_02,
397 IRQ_LPC32XX_GPI_03,
398 IRQ_LPC32XX_GPI_04,
399 IRQ_LPC32XX_GPI_05,
400 IRQ_LPC32XX_GPI_06,
401 IRQ_LPC32XX_GPI_07,
402 IRQ_LPC32XX_GPI_08,
403 IRQ_LPC32XX_GPI_09,
404 -ENXIO, /* 10 */
405 -ENXIO, /* 11 */
406 -ENXIO, /* 12 */
407 -ENXIO, /* 13 */
408 -ENXIO, /* 14 */
409 -ENXIO, /* 15 */
410 -ENXIO, /* 16 */
411 -ENXIO, /* 17 */
412 -ENXIO, /* 18 */
413 IRQ_LPC32XX_GPI_19,
414 -ENXIO, /* 20 */
415 -ENXIO, /* 21 */
416 -ENXIO, /* 22 */
417 -ENXIO, /* 23 */
418 -ENXIO, /* 24 */
419 -ENXIO, /* 25 */
420 -ENXIO, /* 26 */
421 -ENXIO, /* 27 */
422 IRQ_LPC32XX_GPI_28,
423};
424
425static int lpc32xx_gpio_to_irq_gpi_p3(struct gpio_chip *chip, unsigned offset)
426{
427 if (offset < ARRAY_SIZE(lpc32xx_gpio_to_irq_gpi_p3_table))
428 return lpc32xx_gpio_to_irq_gpi_p3_table[offset];
429 return -ENXIO;
430}
431
432static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
433 {
434 .chip = {
435 .label = "gpio_p0",
436 .direction_input = lpc32xx_gpio_dir_input_p012,
437 .get = lpc32xx_gpio_get_value_p012,
438 .direction_output = lpc32xx_gpio_dir_output_p012,
439 .set = lpc32xx_gpio_set_value_p012,
440 .request = lpc32xx_gpio_request,
441 .to_irq = lpc32xx_gpio_to_irq_p01,
442 .base = LPC32XX_GPIO_P0_GRP,
443 .ngpio = LPC32XX_GPIO_P0_MAX,
444 .names = gpio_p0_names,
445 .can_sleep = false,
446 },
447 .gpio_grp = &gpio_grp_regs_p0,
448 },
449 {
450 .chip = {
451 .label = "gpio_p1",
452 .direction_input = lpc32xx_gpio_dir_input_p012,
453 .get = lpc32xx_gpio_get_value_p012,
454 .direction_output = lpc32xx_gpio_dir_output_p012,
455 .set = lpc32xx_gpio_set_value_p012,
456 .request = lpc32xx_gpio_request,
457 .to_irq = lpc32xx_gpio_to_irq_p01,
458 .base = LPC32XX_GPIO_P1_GRP,
459 .ngpio = LPC32XX_GPIO_P1_MAX,
460 .names = gpio_p1_names,
461 .can_sleep = false,
462 },
463 .gpio_grp = &gpio_grp_regs_p1,
464 },
465 {
466 .chip = {
467 .label = "gpio_p2",
468 .direction_input = lpc32xx_gpio_dir_input_p012,
469 .get = lpc32xx_gpio_get_value_p012,
470 .direction_output = lpc32xx_gpio_dir_output_p012,
471 .set = lpc32xx_gpio_set_value_p012,
472 .request = lpc32xx_gpio_request,
473 .base = LPC32XX_GPIO_P2_GRP,
474 .ngpio = LPC32XX_GPIO_P2_MAX,
475 .names = gpio_p2_names,
476 .can_sleep = false,
477 },
478 .gpio_grp = &gpio_grp_regs_p2,
479 },
480 {
481 .chip = {
482 .label = "gpio_p3",
483 .direction_input = lpc32xx_gpio_dir_input_p3,
484 .get = lpc32xx_gpio_get_value_p3,
485 .direction_output = lpc32xx_gpio_dir_output_p3,
486 .set = lpc32xx_gpio_set_value_p3,
487 .request = lpc32xx_gpio_request,
488 .to_irq = lpc32xx_gpio_to_irq_gpio_p3,
489 .base = LPC32XX_GPIO_P3_GRP,
490 .ngpio = LPC32XX_GPIO_P3_MAX,
491 .names = gpio_p3_names,
492 .can_sleep = false,
493 },
494 .gpio_grp = &gpio_grp_regs_p3,
495 },
496 {
497 .chip = {
498 .label = "gpi_p3",
499 .direction_input = lpc32xx_gpio_dir_in_always,
500 .get = lpc32xx_gpi_get_value,
501 .request = lpc32xx_gpio_request,
502 .to_irq = lpc32xx_gpio_to_irq_gpi_p3,
503 .base = LPC32XX_GPI_P3_GRP,
504 .ngpio = LPC32XX_GPI_P3_MAX,
505 .names = gpi_p3_names,
506 .can_sleep = false,
507 },
508 .gpio_grp = &gpio_grp_regs_p3,
509 },
510 {
511 .chip = {
512 .label = "gpo_p3",
513 .direction_output = lpc32xx_gpio_dir_out_always,
514 .set = lpc32xx_gpo_set_value,
515 .get = lpc32xx_gpo_get_value,
516 .request = lpc32xx_gpio_request,
517 .base = LPC32XX_GPO_P3_GRP,
518 .ngpio = LPC32XX_GPO_P3_MAX,
519 .names = gpo_p3_names,
520 .can_sleep = false,
521 },
522 .gpio_grp = &gpio_grp_regs_p3,
523 },
524};
525
526static int lpc32xx_of_xlate(struct gpio_chip *gc,
527 const struct of_phandle_args *gpiospec, u32 *flags)
528{
529 /* Is this the correct bank? */
530 u32 bank = gpiospec->args[0];
531 if ((bank >= ARRAY_SIZE(lpc32xx_gpiochip) ||
532 (gc != &lpc32xx_gpiochip[bank].chip)))
533 return -EINVAL;
534
535 if (flags)
536 *flags = gpiospec->args[2];
537 return gpiospec->args[1];
538}
539
540static int lpc32xx_gpio_probe(struct platform_device *pdev)
541{
542 int i;
543
544 for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) {
545 if (pdev->dev.of_node) {
546 lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate;
547 lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3;
548 lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node;
549 }
550 devm_gpiochip_add_data(&pdev->dev, &lpc32xx_gpiochip[i].chip,
551 &lpc32xx_gpiochip[i]);
552 }
553
554 return 0;
555}
556
557#ifdef CONFIG_OF
558static const struct of_device_id lpc32xx_gpio_of_match[] = {
559 { .compatible = "nxp,lpc3220-gpio", },
560 { },
561};
562#endif
563
564static struct platform_driver lpc32xx_gpio_driver = {
565 .driver = {
566 .name = "lpc32xx-gpio",
567 .of_match_table = of_match_ptr(lpc32xx_gpio_of_match),
568 },
569 .probe = lpc32xx_gpio_probe,
570};
571
572module_platform_driver(lpc32xx_gpio_driver);