1/*
  2 * Copyright 2011 IBM Corporation.
  3 *
  4 *  This program is free software; you can redistribute it and/or
  5 *  modify it under the terms of the GNU General Public License
  6 *  as published by the Free Software Foundation; either version
  7 *  2 of the License, or (at your option) any later version.
  8 *
  9 */
 10#include <linux/types.h>
 11#include <linux/threads.h>
 12#include <linux/kernel.h>
 13#include <linux/irq.h>
 14#include <linux/debugfs.h>
 15#include <linux/smp.h>
 16#include <linux/interrupt.h>
 17#include <linux/seq_file.h>
 18#include <linux/init.h>
 19#include <linux/cpu.h>
 20#include <linux/of.h>
 21#include <linux/slab.h>
 22#include <linux/spinlock.h>
 23
 24#include <asm/prom.h>
 25#include <asm/io.h>
 26#include <asm/smp.h>
 27#include <asm/machdep.h>
 28#include <asm/irq.h>
 29#include <asm/errno.h>
 30#include <asm/rtas.h>
 31#include <asm/xics.h>
 32#include <asm/firmware.h>
 33
 34/* Globals common to all ICP/ICS implementations */
 35const struct icp_ops	*icp_ops;
 36
 37unsigned int xics_default_server		= 0xff;
 38unsigned int xics_default_distrib_server	= 0;
 39unsigned int xics_interrupt_server_size		= 8;
 40
 41DEFINE_PER_CPU(struct xics_cppr, xics_cppr);
 42
 43struct irq_domain *xics_host;
 44
 45static LIST_HEAD(ics_list);
 46
 47void xics_update_irq_servers(void)
 48{
 49	int i, j;
 50	struct device_node *np;
 51	u32 ilen;
 52	const u32 *ireg;
 53	u32 hcpuid;
 54
 55	/* Find the server numbers for the boot cpu. */
 56	np = of_get_cpu_node(boot_cpuid, NULL);
 57	BUG_ON(!np);
 58
 59	hcpuid = get_hard_smp_processor_id(boot_cpuid);
 60	xics_default_server = xics_default_distrib_server = hcpuid;
 61
 62	pr_devel("xics: xics_default_server = 0x%x\n", xics_default_server);
 63
 64	ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen);
 65	if (!ireg) {
 66		of_node_put(np);
 67		return;
 68	}
 69
 70	i = ilen / sizeof(int);
 71
 72	/* Global interrupt distribution server is specified in the last
 73	 * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last
 74	 * entry fom this property for current boot cpu id and use it as
 75	 * default distribution server
 76	 */
 77	for (j = 0; j < i; j += 2) {
 78		if (ireg[j] == hcpuid) {
 79			xics_default_distrib_server = ireg[j+1];
 80			break;
 81		}
 82	}
 83	pr_devel("xics: xics_default_distrib_server = 0x%x\n",
 84		 xics_default_distrib_server);
 85	of_node_put(np);
 86}
 87
 88/* GIQ stuff, currently only supported on RTAS setups, will have
 89 * to be sorted properly for bare metal
 90 */
 91void xics_set_cpu_giq(unsigned int gserver, unsigned int join)
 92{
 93#ifdef CONFIG_PPC_RTAS
 94	int index;
 95	int status;
 96
 97	if (!rtas_indicator_present(GLOBAL_INTERRUPT_QUEUE, NULL))
 98		return;
 99
100	index = (1UL << xics_interrupt_server_size) - 1 - gserver;
101
102	status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE, index, join);
103
104	WARN(status < 0, "set-indicator(%d, %d, %u) returned %d\n",
105	     GLOBAL_INTERRUPT_QUEUE, index, join, status);
106#endif
107}
108
109void xics_setup_cpu(void)
110{
111	icp_ops->set_priority(LOWEST_PRIORITY);
112
113	xics_set_cpu_giq(xics_default_distrib_server, 1);
114}
115
116void xics_mask_unknown_vec(unsigned int vec)
117{
118	struct ics *ics;
119
120	pr_err("Interrupt 0x%x (real) is invalid, disabling it.\n", vec);
121
122	list_for_each_entry(ics, &ics_list, link)
123		ics->mask_unknown(ics, vec);
124}
125
126
127#ifdef CONFIG_SMP
128
129static void xics_request_ipi(void)
130{
131	unsigned int ipi;
132
133	ipi = irq_create_mapping(xics_host, XICS_IPI);
134	BUG_ON(ipi == NO_IRQ);
135
136	/*
137	 * IPIs are marked IRQF_PERCPU. The handler was set in map.
138	 */
139	BUG_ON(request_irq(ipi, icp_ops->ipi_action,
140			   IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL));
141}
142
143int __init xics_smp_probe(void)
144{
145	/* Setup cause_ipi callback  based on which ICP is used */
146	smp_ops->cause_ipi = icp_ops->cause_ipi;
147
148	/* Register all the IPIs */
149	xics_request_ipi();
150
151	return cpumask_weight(cpu_possible_mask);
152}
153
154#endif /* CONFIG_SMP */
155
156void xics_teardown_cpu(void)
157{
158	struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
159
160	/*
161	 * we have to reset the cppr index to 0 because we're
162	 * not going to return from the IPI
163	 */
164	os_cppr->index = 0;
165	icp_ops->set_priority(0);
166	icp_ops->teardown_cpu();
167}
168
169void xics_kexec_teardown_cpu(int secondary)
170{
171	xics_teardown_cpu();
172
173	icp_ops->flush_ipi();
174
175	/*
176	 * Some machines need to have at least one cpu in the GIQ,
177	 * so leave the master cpu in the group.
178	 */
179	if (secondary)
180		xics_set_cpu_giq(xics_default_distrib_server, 0);
181}
182
183
184#ifdef CONFIG_HOTPLUG_CPU
185
186/* Interrupts are disabled. */
187void xics_migrate_irqs_away(void)
188{
189	int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id();
190	unsigned int irq, virq;
191	struct irq_desc *desc;
192
193	/* If we used to be the default server, move to the new "boot_cpuid" */
194	if (hw_cpu == xics_default_server)
195		xics_update_irq_servers();
196
197	/* Reject any interrupt that was queued to us... */
198	icp_ops->set_priority(0);
199
200	/* Remove ourselves from the global interrupt queue */
201	xics_set_cpu_giq(xics_default_distrib_server, 0);
202
203	/* Allow IPIs again... */
204	icp_ops->set_priority(DEFAULT_PRIORITY);
205
206	for_each_irq_desc(virq, desc) {
207		struct irq_chip *chip;
208		long server;
209		unsigned long flags;
210		struct ics *ics;
211
212		/* We can't set affinity on ISA interrupts */
213		if (virq < NUM_ISA_INTERRUPTS)
214			continue;
215		/* We only need to migrate enabled IRQS */
216		if (!desc->action)
217			continue;
218		if (desc->irq_data.domain != xics_host)
219			continue;
220		irq = desc->irq_data.hwirq;
221		/* We need to get IPIs still. */
222		if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
223			continue;
224		chip = irq_desc_get_chip(desc);
225		if (!chip || !chip->irq_set_affinity)
226			continue;
227
228		raw_spin_lock_irqsave(&desc->lock, flags);
229
230		/* Locate interrupt server */
231		server = -1;
232		ics = irq_get_chip_data(virq);
233		if (ics)
234			server = ics->get_server(ics, irq);
235		if (server < 0) {
236			printk(KERN_ERR "%s: Can't find server for irq %d\n",
237			       __func__, irq);
238			goto unlock;
239		}
240
241		/* We only support delivery to all cpus or to one cpu.
242		 * The irq has to be migrated only in the single cpu
243		 * case.
244		 */
245		if (server != hw_cpu)
246			goto unlock;
247
248		/* This is expected during cpu offline. */
249		if (cpu_online(cpu))
250			pr_warning("IRQ %u affinity broken off cpu %u\n",
251			       virq, cpu);
252
253		/* Reset affinity to all cpus */
254		raw_spin_unlock_irqrestore(&desc->lock, flags);
255		irq_set_affinity(virq, cpu_all_mask);
256		continue;
257unlock:
258		raw_spin_unlock_irqrestore(&desc->lock, flags);
259	}
260}
261#endif /* CONFIG_HOTPLUG_CPU */
262
263#ifdef CONFIG_SMP
264/*
265 * For the moment we only implement delivery to all cpus or one cpu.
266 *
267 * If the requested affinity is cpu_all_mask, we set global affinity.
268 * If not we set it to the first cpu in the mask, even if multiple cpus
269 * are set. This is so things like irqbalance (which set core and package
270 * wide affinities) do the right thing.
271 *
272 * We need to fix this to implement support for the links
273 */
274int xics_get_irq_server(unsigned int virq, const struct cpumask *cpumask,
275			unsigned int strict_check)
276{
277
278	if (!distribute_irqs)
279		return xics_default_server;
280
281	if (!cpumask_subset(cpu_possible_mask, cpumask)) {
282		int server = cpumask_first_and(cpu_online_mask, cpumask);
283
284		if (server < nr_cpu_ids)
285			return get_hard_smp_processor_id(server);
286
287		if (strict_check)
288			return -1;
289	}
290
291	/*
292	 * Workaround issue with some versions of JS20 firmware that
293	 * deliver interrupts to cpus which haven't been started. This
294	 * happens when using the maxcpus= boot option.
295	 */
296	if (cpumask_equal(cpu_online_mask, cpu_present_mask))
297		return xics_default_distrib_server;
298
299	return xics_default_server;
300}
301#endif /* CONFIG_SMP */
302
303static int xics_host_match(struct irq_domain *h, struct device_node *node)
 
304{
305	struct ics *ics;
306
307	list_for_each_entry(ics, &ics_list, link)
308		if (ics->host_match(ics, node))
309			return 1;
310
311	return 0;
312}
313
314/* Dummies */
315static void xics_ipi_unmask(struct irq_data *d) { }
316static void xics_ipi_mask(struct irq_data *d) { }
317
318static struct irq_chip xics_ipi_chip = {
319	.name = "XICS",
320	.irq_eoi = NULL, /* Patched at init time */
321	.irq_mask = xics_ipi_mask,
322	.irq_unmask = xics_ipi_unmask,
323};
324
325static int xics_host_map(struct irq_domain *h, unsigned int virq,
326			 irq_hw_number_t hw)
327{
328	struct ics *ics;
329
330	pr_devel("xics: map virq %d, hwirq 0x%lx\n", virq, hw);
331
332	/* Insert the interrupt mapping into the radix tree for fast lookup */
333	irq_radix_revmap_insert(xics_host, virq, hw);
334
335	/* They aren't all level sensitive but we just don't really know */
336	irq_set_status_flags(virq, IRQ_LEVEL);
337
338	/* Don't call into ICS for IPIs */
339	if (hw == XICS_IPI) {
340		irq_set_chip_and_handler(virq, &xics_ipi_chip,
341					 handle_percpu_irq);
342		return 0;
343	}
344
345	/* Let the ICS setup the chip data */
346	list_for_each_entry(ics, &ics_list, link)
347		if (ics->map(ics, virq) == 0)
348			return 0;
349
350	return -EINVAL;
351}
352
353static int xics_host_xlate(struct irq_domain *h, struct device_node *ct,
354			   const u32 *intspec, unsigned int intsize,
355			   irq_hw_number_t *out_hwirq, unsigned int *out_flags)
356
357{
358	/* Current xics implementation translates everything
359	 * to level. It is not technically right for MSIs but this
360	 * is irrelevant at this point. We might get smarter in the future
361	 */
362	*out_hwirq = intspec[0];
363	*out_flags = IRQ_TYPE_LEVEL_LOW;
364
365	return 0;
366}
367
368static struct irq_domain_ops xics_host_ops = {
369	.match = xics_host_match,
370	.map = xics_host_map,
371	.xlate = xics_host_xlate,
372};
373
374static void __init xics_init_host(void)
375{
376	xics_host = irq_domain_add_tree(NULL, &xics_host_ops, NULL);
377	BUG_ON(xics_host == NULL);
378	irq_set_default_host(xics_host);
379}
380
381void __init xics_register_ics(struct ics *ics)
382{
383	list_add(&ics->link, &ics_list);
384}
385
386static void __init xics_get_server_size(void)
387{
388	struct device_node *np;
389	const u32 *isize;
390
391	/* We fetch the interrupt server size from the first ICS node
392	 * we find if any
393	 */
394	np = of_find_compatible_node(NULL, NULL, "ibm,ppc-xics");
395	if (!np)
396		return;
397	isize = of_get_property(np, "ibm,interrupt-server#-size", NULL);
398	if (!isize)
399		return;
400	xics_interrupt_server_size = *isize;
401	of_node_put(np);
402}
403
404void __init xics_init(void)
405{
406	int rc = -1;
407
408	/* Fist locate ICP */
409	if (firmware_has_feature(FW_FEATURE_LPAR))
410		rc = icp_hv_init();
411	if (rc < 0)
412		rc = icp_native_init();
413	if (rc < 0) {
414		pr_warning("XICS: Cannot find a Presentation Controller !\n");
415		return;
416	}
417
418	/* Copy get_irq callback over to ppc_md */
419	ppc_md.get_irq = icp_ops->get_irq;
420
421	/* Patch up IPI chip EOI */
422	xics_ipi_chip.irq_eoi = icp_ops->eoi;
423
424	/* Now locate ICS */
425	rc = ics_rtas_init();
426	if (rc < 0)
427		rc = ics_opal_init();
428	if (rc < 0)
429		pr_warning("XICS: Cannot find a Source Controller !\n");
430
431	/* Initialize common bits */
432	xics_get_server_size();
433	xics_update_irq_servers();
434	xics_init_host();
435	xics_setup_cpu();
436}

  1/*
  2 * Copyright 2011 IBM Corporation.
  3 *
  4 *  This program is free software; you can redistribute it and/or
  5 *  modify it under the terms of the GNU General Public License
  6 *  as published by the Free Software Foundation; either version
  7 *  2 of the License, or (at your option) any later version.
  8 *
  9 */
 10#include <linux/types.h>
 11#include <linux/threads.h>
 12#include <linux/kernel.h>
 13#include <linux/irq.h>
 14#include <linux/debugfs.h>
 15#include <linux/smp.h>
 16#include <linux/interrupt.h>
 17#include <linux/seq_file.h>
 18#include <linux/init.h>
 19#include <linux/cpu.h>
 20#include <linux/of.h>
 21#include <linux/slab.h>
 22#include <linux/spinlock.h>
 23
 24#include <asm/prom.h>
 25#include <asm/io.h>
 26#include <asm/smp.h>
 27#include <asm/machdep.h>
 28#include <asm/irq.h>
 29#include <asm/errno.h>
 30#include <asm/rtas.h>
 31#include <asm/xics.h>
 32#include <asm/firmware.h>
 33
 34/* Globals common to all ICP/ICS implementations */
 35const struct icp_ops	*icp_ops;
 36
 37unsigned int xics_default_server		= 0xff;
 38unsigned int xics_default_distrib_server	= 0;
 39unsigned int xics_interrupt_server_size		= 8;
 40
 41DEFINE_PER_CPU(struct xics_cppr, xics_cppr);
 42
 43struct irq_domain *xics_host;
 44
 45static LIST_HEAD(ics_list);
 46
 47void xics_update_irq_servers(void)
 48{
 49	int i, j;
 50	struct device_node *np;
 51	u32 ilen;
 52	const __be32 *ireg;
 53	u32 hcpuid;
 54
 55	/* Find the server numbers for the boot cpu. */
 56	np = of_get_cpu_node(boot_cpuid, NULL);
 57	BUG_ON(!np);
 58
 59	hcpuid = get_hard_smp_processor_id(boot_cpuid);
 60	xics_default_server = xics_default_distrib_server = hcpuid;
 61
 62	pr_devel("xics: xics_default_server = 0x%x\n", xics_default_server);
 63
 64	ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen);
 65	if (!ireg) {
 66		of_node_put(np);
 67		return;
 68	}
 69
 70	i = ilen / sizeof(int);
 71
 72	/* Global interrupt distribution server is specified in the last
 73	 * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last
 74	 * entry fom this property for current boot cpu id and use it as
 75	 * default distribution server
 76	 */
 77	for (j = 0; j < i; j += 2) {
 78		if (be32_to_cpu(ireg[j]) == hcpuid) {
 79			xics_default_distrib_server = be32_to_cpu(ireg[j+1]);
 80			break;
 81		}
 82	}
 83	pr_devel("xics: xics_default_distrib_server = 0x%x\n",
 84		 xics_default_distrib_server);
 85	of_node_put(np);
 86}
 87
 88/* GIQ stuff, currently only supported on RTAS setups, will have
 89 * to be sorted properly for bare metal
 90 */
 91void xics_set_cpu_giq(unsigned int gserver, unsigned int join)
 92{
 93#ifdef CONFIG_PPC_RTAS
 94	int index;
 95	int status;
 96
 97	if (!rtas_indicator_present(GLOBAL_INTERRUPT_QUEUE, NULL))
 98		return;
 99
100	index = (1UL << xics_interrupt_server_size) - 1 - gserver;
101
102	status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE, index, join);
103
104	WARN(status < 0, "set-indicator(%d, %d, %u) returned %d\n",
105	     GLOBAL_INTERRUPT_QUEUE, index, join, status);
106#endif
107}
108
109void xics_setup_cpu(void)
110{
111	icp_ops->set_priority(LOWEST_PRIORITY);
112
113	xics_set_cpu_giq(xics_default_distrib_server, 1);
114}
115
116void xics_mask_unknown_vec(unsigned int vec)
117{
118	struct ics *ics;
119
120	pr_err("Interrupt 0x%x (real) is invalid, disabling it.\n", vec);
121
122	list_for_each_entry(ics, &ics_list, link)
123		ics->mask_unknown(ics, vec);
124}
125
126
127#ifdef CONFIG_SMP
128
129static void xics_request_ipi(void)
130{
131	unsigned int ipi;
132
133	ipi = irq_create_mapping(xics_host, XICS_IPI);
134	BUG_ON(ipi == NO_IRQ);
135
136	/*
137	 * IPIs are marked IRQF_PERCPU. The handler was set in map.
138	 */
139	BUG_ON(request_irq(ipi, icp_ops->ipi_action,
140			   IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL));
141}
142
143void __init xics_smp_probe(void)
144{
145	/* Setup cause_ipi callback  based on which ICP is used */
146	smp_ops->cause_ipi = icp_ops->cause_ipi;
147
148	/* Register all the IPIs */
149	xics_request_ipi();
 
 
150}
151
152#endif /* CONFIG_SMP */
153
154void xics_teardown_cpu(void)
155{
156	struct xics_cppr *os_cppr = this_cpu_ptr(&xics_cppr);
157
158	/*
159	 * we have to reset the cppr index to 0 because we're
160	 * not going to return from the IPI
161	 */
162	os_cppr->index = 0;
163	icp_ops->set_priority(0);
164	icp_ops->teardown_cpu();
165}
166
167void xics_kexec_teardown_cpu(int secondary)
168{
169	xics_teardown_cpu();
170
171	icp_ops->flush_ipi();
172
173	/*
174	 * Some machines need to have at least one cpu in the GIQ,
175	 * so leave the master cpu in the group.
176	 */
177	if (secondary)
178		xics_set_cpu_giq(xics_default_distrib_server, 0);
179}
180
181
182#ifdef CONFIG_HOTPLUG_CPU
183
184/* Interrupts are disabled. */
185void xics_migrate_irqs_away(void)
186{
187	int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id();
188	unsigned int irq, virq;
189	struct irq_desc *desc;
190
191	/* If we used to be the default server, move to the new "boot_cpuid" */
192	if (hw_cpu == xics_default_server)
193		xics_update_irq_servers();
194
195	/* Reject any interrupt that was queued to us... */
196	icp_ops->set_priority(0);
197
198	/* Remove ourselves from the global interrupt queue */
199	xics_set_cpu_giq(xics_default_distrib_server, 0);
200
201	/* Allow IPIs again... */
202	icp_ops->set_priority(DEFAULT_PRIORITY);
203
204	for_each_irq_desc(virq, desc) {
205		struct irq_chip *chip;
206		long server;
207		unsigned long flags;
208		struct ics *ics;
209
210		/* We can't set affinity on ISA interrupts */
211		if (virq < NUM_ISA_INTERRUPTS)
212			continue;
213		/* We only need to migrate enabled IRQS */
214		if (!desc->action)
215			continue;
216		if (desc->irq_data.domain != xics_host)
217			continue;
218		irq = desc->irq_data.hwirq;
219		/* We need to get IPIs still. */
220		if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
221			continue;
222		chip = irq_desc_get_chip(desc);
223		if (!chip || !chip->irq_set_affinity)
224			continue;
225
226		raw_spin_lock_irqsave(&desc->lock, flags);
227
228		/* Locate interrupt server */
229		server = -1;
230		ics = irq_desc_get_chip_data(desc);
231		if (ics)
232			server = ics->get_server(ics, irq);
233		if (server < 0) {
234			printk(KERN_ERR "%s: Can't find server for irq %d\n",
235			       __func__, irq);
236			goto unlock;
237		}
238
239		/* We only support delivery to all cpus or to one cpu.
240		 * The irq has to be migrated only in the single cpu
241		 * case.
242		 */
243		if (server != hw_cpu)
244			goto unlock;
245
246		/* This is expected during cpu offline. */
247		if (cpu_online(cpu))
248			pr_warning("IRQ %u affinity broken off cpu %u\n",
249			       virq, cpu);
250
251		/* Reset affinity to all cpus */
252		raw_spin_unlock_irqrestore(&desc->lock, flags);
253		irq_set_affinity(virq, cpu_all_mask);
254		continue;
255unlock:
256		raw_spin_unlock_irqrestore(&desc->lock, flags);
257	}
258}
259#endif /* CONFIG_HOTPLUG_CPU */
260
261#ifdef CONFIG_SMP
262/*
263 * For the moment we only implement delivery to all cpus or one cpu.
264 *
265 * If the requested affinity is cpu_all_mask, we set global affinity.
266 * If not we set it to the first cpu in the mask, even if multiple cpus
267 * are set. This is so things like irqbalance (which set core and package
268 * wide affinities) do the right thing.
269 *
270 * We need to fix this to implement support for the links
271 */
272int xics_get_irq_server(unsigned int virq, const struct cpumask *cpumask,
273			unsigned int strict_check)
274{
275
276	if (!distribute_irqs)
277		return xics_default_server;
278
279	if (!cpumask_subset(cpu_possible_mask, cpumask)) {
280		int server = cpumask_first_and(cpu_online_mask, cpumask);
281
282		if (server < nr_cpu_ids)
283			return get_hard_smp_processor_id(server);
284
285		if (strict_check)
286			return -1;
287	}
288
289	/*
290	 * Workaround issue with some versions of JS20 firmware that
291	 * deliver interrupts to cpus which haven't been started. This
292	 * happens when using the maxcpus= boot option.
293	 */
294	if (cpumask_equal(cpu_online_mask, cpu_present_mask))
295		return xics_default_distrib_server;
296
297	return xics_default_server;
298}
299#endif /* CONFIG_SMP */
300
301static int xics_host_match(struct irq_domain *h, struct device_node *node,
302			   enum irq_domain_bus_token bus_token)
303{
304	struct ics *ics;
305
306	list_for_each_entry(ics, &ics_list, link)
307		if (ics->host_match(ics, node))
308			return 1;
309
310	return 0;
311}
312
313/* Dummies */
314static void xics_ipi_unmask(struct irq_data *d) { }
315static void xics_ipi_mask(struct irq_data *d) { }
316
317static struct irq_chip xics_ipi_chip = {
318	.name = "XICS",
319	.irq_eoi = NULL, /* Patched at init time */
320	.irq_mask = xics_ipi_mask,
321	.irq_unmask = xics_ipi_unmask,
322};
323
324static int xics_host_map(struct irq_domain *h, unsigned int virq,
325			 irq_hw_number_t hw)
326{
327	struct ics *ics;
328
329	pr_devel("xics: map virq %d, hwirq 0x%lx\n", virq, hw);
330
 
 
 
331	/* They aren't all level sensitive but we just don't really know */
332	irq_set_status_flags(virq, IRQ_LEVEL);
333
334	/* Don't call into ICS for IPIs */
335	if (hw == XICS_IPI) {
336		irq_set_chip_and_handler(virq, &xics_ipi_chip,
337					 handle_percpu_irq);
338		return 0;
339	}
340
341	/* Let the ICS setup the chip data */
342	list_for_each_entry(ics, &ics_list, link)
343		if (ics->map(ics, virq) == 0)
344			return 0;
345
346	return -EINVAL;
347}
348
349static int xics_host_xlate(struct irq_domain *h, struct device_node *ct,
350			   const u32 *intspec, unsigned int intsize,
351			   irq_hw_number_t *out_hwirq, unsigned int *out_flags)
352
353{
354	/* Current xics implementation translates everything
355	 * to level. It is not technically right for MSIs but this
356	 * is irrelevant at this point. We might get smarter in the future
357	 */
358	*out_hwirq = intspec[0];
359	*out_flags = IRQ_TYPE_LEVEL_LOW;
360
361	return 0;
362}
363
364static const struct irq_domain_ops xics_host_ops = {
365	.match = xics_host_match,
366	.map = xics_host_map,
367	.xlate = xics_host_xlate,
368};
369
370static void __init xics_init_host(void)
371{
372	xics_host = irq_domain_add_tree(NULL, &xics_host_ops, NULL);
373	BUG_ON(xics_host == NULL);
374	irq_set_default_host(xics_host);
375}
376
377void __init xics_register_ics(struct ics *ics)
378{
379	list_add(&ics->link, &ics_list);
380}
381
382static void __init xics_get_server_size(void)
383{
384	struct device_node *np;
385	const __be32 *isize;
386
387	/* We fetch the interrupt server size from the first ICS node
388	 * we find if any
389	 */
390	np = of_find_compatible_node(NULL, NULL, "ibm,ppc-xics");
391	if (!np)
392		return;
393	isize = of_get_property(np, "ibm,interrupt-server#-size", NULL);
394	if (!isize)
395		return;
396	xics_interrupt_server_size = be32_to_cpu(*isize);
397	of_node_put(np);
398}
399
400void __init xics_init(void)
401{
402	int rc = -1;
403
404	/* Fist locate ICP */
405	if (firmware_has_feature(FW_FEATURE_LPAR))
406		rc = icp_hv_init();
407	if (rc < 0)
408		rc = icp_native_init();
409	if (rc < 0) {
410		pr_warning("XICS: Cannot find a Presentation Controller !\n");
411		return;
412	}
413
414	/* Copy get_irq callback over to ppc_md */
415	ppc_md.get_irq = icp_ops->get_irq;
416
417	/* Patch up IPI chip EOI */
418	xics_ipi_chip.irq_eoi = icp_ops->eoi;
419
420	/* Now locate ICS */
421	rc = ics_rtas_init();
422	if (rc < 0)
423		rc = ics_opal_init();
424	if (rc < 0)
425		pr_warning("XICS: Cannot find a Source Controller !\n");
426
427	/* Initialize common bits */
428	xics_get_server_size();
429	xics_update_irq_servers();
430	xics_init_host();
431	xics_setup_cpu();
432}