Loading...
1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
12 *
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/io.h>
23#include <linux/clk.h>
24
25#include <asm/tlb.h>
26#include <asm/mach/map.h>
27
28#include <plat/sram.h>
29#include <plat/sdrc.h>
30#include <plat/serial.h>
31#include <plat/omap-pm.h>
32#include <plat/omap_hwmod.h>
33#include <plat/multi.h>
34#include <plat/dma.h>
35
36#include "iomap.h"
37#include "voltage.h"
38#include "powerdomain.h"
39#include "clockdomain.h"
40#include "common.h"
41#include "clock2xxx.h"
42#include "clock3xxx.h"
43#include "clock44xx.h"
44
45/*
46 * The machine specific code may provide the extra mapping besides the
47 * default mapping provided here.
48 */
49
50#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
51static struct map_desc omap24xx_io_desc[] __initdata = {
52 {
53 .virtual = L3_24XX_VIRT,
54 .pfn = __phys_to_pfn(L3_24XX_PHYS),
55 .length = L3_24XX_SIZE,
56 .type = MT_DEVICE
57 },
58 {
59 .virtual = L4_24XX_VIRT,
60 .pfn = __phys_to_pfn(L4_24XX_PHYS),
61 .length = L4_24XX_SIZE,
62 .type = MT_DEVICE
63 },
64};
65
66#ifdef CONFIG_SOC_OMAP2420
67static struct map_desc omap242x_io_desc[] __initdata = {
68 {
69 .virtual = DSP_MEM_2420_VIRT,
70 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
71 .length = DSP_MEM_2420_SIZE,
72 .type = MT_DEVICE
73 },
74 {
75 .virtual = DSP_IPI_2420_VIRT,
76 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
77 .length = DSP_IPI_2420_SIZE,
78 .type = MT_DEVICE
79 },
80 {
81 .virtual = DSP_MMU_2420_VIRT,
82 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
83 .length = DSP_MMU_2420_SIZE,
84 .type = MT_DEVICE
85 },
86};
87
88#endif
89
90#ifdef CONFIG_SOC_OMAP2430
91static struct map_desc omap243x_io_desc[] __initdata = {
92 {
93 .virtual = L4_WK_243X_VIRT,
94 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
95 .length = L4_WK_243X_SIZE,
96 .type = MT_DEVICE
97 },
98 {
99 .virtual = OMAP243X_GPMC_VIRT,
100 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
101 .length = OMAP243X_GPMC_SIZE,
102 .type = MT_DEVICE
103 },
104 {
105 .virtual = OMAP243X_SDRC_VIRT,
106 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
107 .length = OMAP243X_SDRC_SIZE,
108 .type = MT_DEVICE
109 },
110 {
111 .virtual = OMAP243X_SMS_VIRT,
112 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
113 .length = OMAP243X_SMS_SIZE,
114 .type = MT_DEVICE
115 },
116};
117#endif
118#endif
119
120#ifdef CONFIG_ARCH_OMAP3
121static struct map_desc omap34xx_io_desc[] __initdata = {
122 {
123 .virtual = L3_34XX_VIRT,
124 .pfn = __phys_to_pfn(L3_34XX_PHYS),
125 .length = L3_34XX_SIZE,
126 .type = MT_DEVICE
127 },
128 {
129 .virtual = L4_34XX_VIRT,
130 .pfn = __phys_to_pfn(L4_34XX_PHYS),
131 .length = L4_34XX_SIZE,
132 .type = MT_DEVICE
133 },
134 {
135 .virtual = OMAP34XX_GPMC_VIRT,
136 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
137 .length = OMAP34XX_GPMC_SIZE,
138 .type = MT_DEVICE
139 },
140 {
141 .virtual = OMAP343X_SMS_VIRT,
142 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
143 .length = OMAP343X_SMS_SIZE,
144 .type = MT_DEVICE
145 },
146 {
147 .virtual = OMAP343X_SDRC_VIRT,
148 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
149 .length = OMAP343X_SDRC_SIZE,
150 .type = MT_DEVICE
151 },
152 {
153 .virtual = L4_PER_34XX_VIRT,
154 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
155 .length = L4_PER_34XX_SIZE,
156 .type = MT_DEVICE
157 },
158 {
159 .virtual = L4_EMU_34XX_VIRT,
160 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
161 .length = L4_EMU_34XX_SIZE,
162 .type = MT_DEVICE
163 },
164#if defined(CONFIG_DEBUG_LL) && \
165 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
166 {
167 .virtual = ZOOM_UART_VIRT,
168 .pfn = __phys_to_pfn(ZOOM_UART_BASE),
169 .length = SZ_1M,
170 .type = MT_DEVICE
171 },
172#endif
173};
174#endif
175
176#ifdef CONFIG_SOC_TI81XX
177static struct map_desc omapti81xx_io_desc[] __initdata = {
178 {
179 .virtual = L4_34XX_VIRT,
180 .pfn = __phys_to_pfn(L4_34XX_PHYS),
181 .length = L4_34XX_SIZE,
182 .type = MT_DEVICE
183 }
184};
185#endif
186
187#ifdef CONFIG_SOC_AM33XX
188static struct map_desc omapam33xx_io_desc[] __initdata = {
189 {
190 .virtual = L4_34XX_VIRT,
191 .pfn = __phys_to_pfn(L4_34XX_PHYS),
192 .length = L4_34XX_SIZE,
193 .type = MT_DEVICE
194 },
195 {
196 .virtual = L4_WK_AM33XX_VIRT,
197 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
198 .length = L4_WK_AM33XX_SIZE,
199 .type = MT_DEVICE
200 }
201};
202#endif
203
204#ifdef CONFIG_ARCH_OMAP4
205static struct map_desc omap44xx_io_desc[] __initdata = {
206 {
207 .virtual = L3_44XX_VIRT,
208 .pfn = __phys_to_pfn(L3_44XX_PHYS),
209 .length = L3_44XX_SIZE,
210 .type = MT_DEVICE,
211 },
212 {
213 .virtual = L4_44XX_VIRT,
214 .pfn = __phys_to_pfn(L4_44XX_PHYS),
215 .length = L4_44XX_SIZE,
216 .type = MT_DEVICE,
217 },
218 {
219 .virtual = L4_PER_44XX_VIRT,
220 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
221 .length = L4_PER_44XX_SIZE,
222 .type = MT_DEVICE,
223 },
224#ifdef CONFIG_OMAP4_ERRATA_I688
225 {
226 .virtual = OMAP4_SRAM_VA,
227 .pfn = __phys_to_pfn(OMAP4_SRAM_PA),
228 .length = PAGE_SIZE,
229 .type = MT_MEMORY_SO,
230 },
231#endif
232
233};
234#endif
235
236#ifdef CONFIG_SOC_OMAP2420
237void __init omap242x_map_common_io(void)
238{
239 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
240 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
241}
242#endif
243
244#ifdef CONFIG_SOC_OMAP2430
245void __init omap243x_map_common_io(void)
246{
247 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
248 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
249}
250#endif
251
252#ifdef CONFIG_ARCH_OMAP3
253void __init omap34xx_map_common_io(void)
254{
255 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
256}
257#endif
258
259#ifdef CONFIG_SOC_TI81XX
260void __init omapti81xx_map_common_io(void)
261{
262 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
263}
264#endif
265
266#ifdef CONFIG_SOC_AM33XX
267void __init omapam33xx_map_common_io(void)
268{
269 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
270}
271#endif
272
273#ifdef CONFIG_ARCH_OMAP4
274void __init omap44xx_map_common_io(void)
275{
276 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
277 omap_barriers_init();
278}
279#endif
280
281/*
282 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
283 *
284 * Sets the CORE DPLL3 M2 divider to the same value that it's at
285 * currently. This has the effect of setting the SDRC SDRAM AC timing
286 * registers to the values currently defined by the kernel. Currently
287 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
288 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
289 * or passes along the return value of clk_set_rate().
290 */
291static int __init _omap2_init_reprogram_sdrc(void)
292{
293 struct clk *dpll3_m2_ck;
294 int v = -EINVAL;
295 long rate;
296
297 if (!cpu_is_omap34xx())
298 return 0;
299
300 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
301 if (IS_ERR(dpll3_m2_ck))
302 return -EINVAL;
303
304 rate = clk_get_rate(dpll3_m2_ck);
305 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
306 v = clk_set_rate(dpll3_m2_ck, rate);
307 if (v)
308 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
309
310 clk_put(dpll3_m2_ck);
311
312 return v;
313}
314
315static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
316{
317 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
318}
319
320static void __init omap_common_init_early(void)
321{
322 omap_init_consistent_dma_size();
323}
324
325static void __init omap_hwmod_init_postsetup(void)
326{
327 u8 postsetup_state;
328
329 /* Set the default postsetup state for all hwmods */
330#ifdef CONFIG_PM_RUNTIME
331 postsetup_state = _HWMOD_STATE_IDLE;
332#else
333 postsetup_state = _HWMOD_STATE_ENABLED;
334#endif
335 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
336
337 omap_pm_if_early_init();
338}
339
340#ifdef CONFIG_SOC_OMAP2420
341void __init omap2420_init_early(void)
342{
343 omap2_set_globals_242x();
344 omap2xxx_check_revision();
345 omap_common_init_early();
346 omap2xxx_voltagedomains_init();
347 omap242x_powerdomains_init();
348 omap242x_clockdomains_init();
349 omap2420_hwmod_init();
350 omap_hwmod_init_postsetup();
351 omap2420_clk_init();
352}
353
354void __init omap2420_init_late(void)
355{
356 omap_mux_late_init();
357 omap2_common_pm_late_init();
358 omap2_pm_init();
359}
360#endif
361
362#ifdef CONFIG_SOC_OMAP2430
363void __init omap2430_init_early(void)
364{
365 omap2_set_globals_243x();
366 omap2xxx_check_revision();
367 omap_common_init_early();
368 omap2xxx_voltagedomains_init();
369 omap243x_powerdomains_init();
370 omap243x_clockdomains_init();
371 omap2430_hwmod_init();
372 omap_hwmod_init_postsetup();
373 omap2430_clk_init();
374}
375
376void __init omap2430_init_late(void)
377{
378 omap_mux_late_init();
379 omap2_common_pm_late_init();
380 omap2_pm_init();
381}
382#endif
383
384/*
385 * Currently only board-omap3beagle.c should call this because of the
386 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
387 */
388#ifdef CONFIG_ARCH_OMAP3
389void __init omap3_init_early(void)
390{
391 omap2_set_globals_3xxx();
392 omap3xxx_check_revision();
393 omap3xxx_check_features();
394 omap_common_init_early();
395 omap3xxx_voltagedomains_init();
396 omap3xxx_powerdomains_init();
397 omap3xxx_clockdomains_init();
398 omap3xxx_hwmod_init();
399 omap_hwmod_init_postsetup();
400 omap3xxx_clk_init();
401}
402
403void __init omap3430_init_early(void)
404{
405 omap3_init_early();
406}
407
408void __init omap35xx_init_early(void)
409{
410 omap3_init_early();
411}
412
413void __init omap3630_init_early(void)
414{
415 omap3_init_early();
416}
417
418void __init am35xx_init_early(void)
419{
420 omap3_init_early();
421}
422
423void __init ti81xx_init_early(void)
424{
425 omap2_set_globals_ti81xx();
426 omap3xxx_check_revision();
427 ti81xx_check_features();
428 omap_common_init_early();
429 omap3xxx_voltagedomains_init();
430 omap3xxx_powerdomains_init();
431 omap3xxx_clockdomains_init();
432 omap3xxx_hwmod_init();
433 omap_hwmod_init_postsetup();
434 omap3xxx_clk_init();
435}
436
437void __init omap3_init_late(void)
438{
439 omap_mux_late_init();
440 omap2_common_pm_late_init();
441 omap3_pm_init();
442}
443
444void __init omap3430_init_late(void)
445{
446 omap_mux_late_init();
447 omap2_common_pm_late_init();
448 omap3_pm_init();
449}
450
451void __init omap35xx_init_late(void)
452{
453 omap_mux_late_init();
454 omap2_common_pm_late_init();
455 omap3_pm_init();
456}
457
458void __init omap3630_init_late(void)
459{
460 omap_mux_late_init();
461 omap2_common_pm_late_init();
462 omap3_pm_init();
463}
464
465void __init am35xx_init_late(void)
466{
467 omap_mux_late_init();
468 omap2_common_pm_late_init();
469 omap3_pm_init();
470}
471
472void __init ti81xx_init_late(void)
473{
474 omap_mux_late_init();
475 omap2_common_pm_late_init();
476 omap3_pm_init();
477}
478#endif
479
480#ifdef CONFIG_ARCH_OMAP4
481void __init omap4430_init_early(void)
482{
483 omap2_set_globals_443x();
484 omap4xxx_check_revision();
485 omap4xxx_check_features();
486 omap_common_init_early();
487 omap44xx_voltagedomains_init();
488 omap44xx_powerdomains_init();
489 omap44xx_clockdomains_init();
490 omap44xx_hwmod_init();
491 omap_hwmod_init_postsetup();
492 omap4xxx_clk_init();
493}
494
495void __init omap4430_init_late(void)
496{
497 omap_mux_late_init();
498 omap2_common_pm_late_init();
499 omap4_pm_init();
500}
501#endif
502
503void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
504 struct omap_sdrc_params *sdrc_cs1)
505{
506 omap_sram_init();
507
508 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
509 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
510 _omap2_init_reprogram_sdrc();
511 }
512}
1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
12 *
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/io.h>
23#include <linux/clk.h>
24
25#include <asm/tlb.h>
26#include <asm/mach/map.h>
27
28#include <linux/omap-dma.h>
29
30#include "omap_hwmod.h"
31#include "soc.h"
32#include "iomap.h"
33#include "voltage.h"
34#include "powerdomain.h"
35#include "clockdomain.h"
36#include "common.h"
37#include "clock.h"
38#include "clock2xxx.h"
39#include "clock3xxx.h"
40#include "omap-pm.h"
41#include "sdrc.h"
42#include "control.h"
43#include "serial.h"
44#include "sram.h"
45#include "cm2xxx.h"
46#include "cm3xxx.h"
47#include "cm33xx.h"
48#include "cm44xx.h"
49#include "prm.h"
50#include "cm.h"
51#include "prcm_mpu44xx.h"
52#include "prminst44xx.h"
53#include "prm2xxx.h"
54#include "prm3xxx.h"
55#include "prm33xx.h"
56#include "prm44xx.h"
57#include "opp2xxx.h"
58
59/*
60 * omap_clk_soc_init: points to a function that does the SoC-specific
61 * clock initializations
62 */
63static int (*omap_clk_soc_init)(void);
64
65/*
66 * The machine specific code may provide the extra mapping besides the
67 * default mapping provided here.
68 */
69
70#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
71static struct map_desc omap24xx_io_desc[] __initdata = {
72 {
73 .virtual = L3_24XX_VIRT,
74 .pfn = __phys_to_pfn(L3_24XX_PHYS),
75 .length = L3_24XX_SIZE,
76 .type = MT_DEVICE
77 },
78 {
79 .virtual = L4_24XX_VIRT,
80 .pfn = __phys_to_pfn(L4_24XX_PHYS),
81 .length = L4_24XX_SIZE,
82 .type = MT_DEVICE
83 },
84};
85
86#ifdef CONFIG_SOC_OMAP2420
87static struct map_desc omap242x_io_desc[] __initdata = {
88 {
89 .virtual = DSP_MEM_2420_VIRT,
90 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
91 .length = DSP_MEM_2420_SIZE,
92 .type = MT_DEVICE
93 },
94 {
95 .virtual = DSP_IPI_2420_VIRT,
96 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
97 .length = DSP_IPI_2420_SIZE,
98 .type = MT_DEVICE
99 },
100 {
101 .virtual = DSP_MMU_2420_VIRT,
102 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
103 .length = DSP_MMU_2420_SIZE,
104 .type = MT_DEVICE
105 },
106};
107
108#endif
109
110#ifdef CONFIG_SOC_OMAP2430
111static struct map_desc omap243x_io_desc[] __initdata = {
112 {
113 .virtual = L4_WK_243X_VIRT,
114 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
115 .length = L4_WK_243X_SIZE,
116 .type = MT_DEVICE
117 },
118 {
119 .virtual = OMAP243X_GPMC_VIRT,
120 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
121 .length = OMAP243X_GPMC_SIZE,
122 .type = MT_DEVICE
123 },
124 {
125 .virtual = OMAP243X_SDRC_VIRT,
126 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
127 .length = OMAP243X_SDRC_SIZE,
128 .type = MT_DEVICE
129 },
130 {
131 .virtual = OMAP243X_SMS_VIRT,
132 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
133 .length = OMAP243X_SMS_SIZE,
134 .type = MT_DEVICE
135 },
136};
137#endif
138#endif
139
140#ifdef CONFIG_ARCH_OMAP3
141static struct map_desc omap34xx_io_desc[] __initdata = {
142 {
143 .virtual = L3_34XX_VIRT,
144 .pfn = __phys_to_pfn(L3_34XX_PHYS),
145 .length = L3_34XX_SIZE,
146 .type = MT_DEVICE
147 },
148 {
149 .virtual = L4_34XX_VIRT,
150 .pfn = __phys_to_pfn(L4_34XX_PHYS),
151 .length = L4_34XX_SIZE,
152 .type = MT_DEVICE
153 },
154 {
155 .virtual = OMAP34XX_GPMC_VIRT,
156 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
157 .length = OMAP34XX_GPMC_SIZE,
158 .type = MT_DEVICE
159 },
160 {
161 .virtual = OMAP343X_SMS_VIRT,
162 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
163 .length = OMAP343X_SMS_SIZE,
164 .type = MT_DEVICE
165 },
166 {
167 .virtual = OMAP343X_SDRC_VIRT,
168 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
169 .length = OMAP343X_SDRC_SIZE,
170 .type = MT_DEVICE
171 },
172 {
173 .virtual = L4_PER_34XX_VIRT,
174 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
175 .length = L4_PER_34XX_SIZE,
176 .type = MT_DEVICE
177 },
178 {
179 .virtual = L4_EMU_34XX_VIRT,
180 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
181 .length = L4_EMU_34XX_SIZE,
182 .type = MT_DEVICE
183 },
184};
185#endif
186
187#ifdef CONFIG_SOC_TI81XX
188static struct map_desc omapti81xx_io_desc[] __initdata = {
189 {
190 .virtual = L4_34XX_VIRT,
191 .pfn = __phys_to_pfn(L4_34XX_PHYS),
192 .length = L4_34XX_SIZE,
193 .type = MT_DEVICE
194 }
195};
196#endif
197
198#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
199static struct map_desc omapam33xx_io_desc[] __initdata = {
200 {
201 .virtual = L4_34XX_VIRT,
202 .pfn = __phys_to_pfn(L4_34XX_PHYS),
203 .length = L4_34XX_SIZE,
204 .type = MT_DEVICE
205 },
206 {
207 .virtual = L4_WK_AM33XX_VIRT,
208 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
209 .length = L4_WK_AM33XX_SIZE,
210 .type = MT_DEVICE
211 }
212};
213#endif
214
215#ifdef CONFIG_ARCH_OMAP4
216static struct map_desc omap44xx_io_desc[] __initdata = {
217 {
218 .virtual = L3_44XX_VIRT,
219 .pfn = __phys_to_pfn(L3_44XX_PHYS),
220 .length = L3_44XX_SIZE,
221 .type = MT_DEVICE,
222 },
223 {
224 .virtual = L4_44XX_VIRT,
225 .pfn = __phys_to_pfn(L4_44XX_PHYS),
226 .length = L4_44XX_SIZE,
227 .type = MT_DEVICE,
228 },
229 {
230 .virtual = L4_PER_44XX_VIRT,
231 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
232 .length = L4_PER_44XX_SIZE,
233 .type = MT_DEVICE,
234 },
235};
236#endif
237
238#ifdef CONFIG_SOC_OMAP5
239static struct map_desc omap54xx_io_desc[] __initdata = {
240 {
241 .virtual = L3_54XX_VIRT,
242 .pfn = __phys_to_pfn(L3_54XX_PHYS),
243 .length = L3_54XX_SIZE,
244 .type = MT_DEVICE,
245 },
246 {
247 .virtual = L4_54XX_VIRT,
248 .pfn = __phys_to_pfn(L4_54XX_PHYS),
249 .length = L4_54XX_SIZE,
250 .type = MT_DEVICE,
251 },
252 {
253 .virtual = L4_WK_54XX_VIRT,
254 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
255 .length = L4_WK_54XX_SIZE,
256 .type = MT_DEVICE,
257 },
258 {
259 .virtual = L4_PER_54XX_VIRT,
260 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
261 .length = L4_PER_54XX_SIZE,
262 .type = MT_DEVICE,
263 },
264};
265#endif
266
267#ifdef CONFIG_SOC_DRA7XX
268static struct map_desc dra7xx_io_desc[] __initdata = {
269 {
270 .virtual = L4_CFG_MPU_DRA7XX_VIRT,
271 .pfn = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS),
272 .length = L4_CFG_MPU_DRA7XX_SIZE,
273 .type = MT_DEVICE,
274 },
275 {
276 .virtual = L3_MAIN_SN_DRA7XX_VIRT,
277 .pfn = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS),
278 .length = L3_MAIN_SN_DRA7XX_SIZE,
279 .type = MT_DEVICE,
280 },
281 {
282 .virtual = L4_PER1_DRA7XX_VIRT,
283 .pfn = __phys_to_pfn(L4_PER1_DRA7XX_PHYS),
284 .length = L4_PER1_DRA7XX_SIZE,
285 .type = MT_DEVICE,
286 },
287 {
288 .virtual = L4_PER2_DRA7XX_VIRT,
289 .pfn = __phys_to_pfn(L4_PER2_DRA7XX_PHYS),
290 .length = L4_PER2_DRA7XX_SIZE,
291 .type = MT_DEVICE,
292 },
293 {
294 .virtual = L4_PER3_DRA7XX_VIRT,
295 .pfn = __phys_to_pfn(L4_PER3_DRA7XX_PHYS),
296 .length = L4_PER3_DRA7XX_SIZE,
297 .type = MT_DEVICE,
298 },
299 {
300 .virtual = L4_CFG_DRA7XX_VIRT,
301 .pfn = __phys_to_pfn(L4_CFG_DRA7XX_PHYS),
302 .length = L4_CFG_DRA7XX_SIZE,
303 .type = MT_DEVICE,
304 },
305 {
306 .virtual = L4_WKUP_DRA7XX_VIRT,
307 .pfn = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS),
308 .length = L4_WKUP_DRA7XX_SIZE,
309 .type = MT_DEVICE,
310 },
311};
312#endif
313
314#ifdef CONFIG_SOC_OMAP2420
315void __init omap242x_map_io(void)
316{
317 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
318 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
319}
320#endif
321
322#ifdef CONFIG_SOC_OMAP2430
323void __init omap243x_map_io(void)
324{
325 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
326 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
327}
328#endif
329
330#ifdef CONFIG_ARCH_OMAP3
331void __init omap3_map_io(void)
332{
333 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
334}
335#endif
336
337#ifdef CONFIG_SOC_TI81XX
338void __init ti81xx_map_io(void)
339{
340 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
341}
342#endif
343
344#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
345void __init am33xx_map_io(void)
346{
347 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
348}
349#endif
350
351#ifdef CONFIG_ARCH_OMAP4
352void __init omap4_map_io(void)
353{
354 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
355 omap_barriers_init();
356}
357#endif
358
359#ifdef CONFIG_SOC_OMAP5
360void __init omap5_map_io(void)
361{
362 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
363 omap_barriers_init();
364}
365#endif
366
367#ifdef CONFIG_SOC_DRA7XX
368void __init dra7xx_map_io(void)
369{
370 iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc));
371 omap_barriers_init();
372}
373#endif
374/*
375 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
376 *
377 * Sets the CORE DPLL3 M2 divider to the same value that it's at
378 * currently. This has the effect of setting the SDRC SDRAM AC timing
379 * registers to the values currently defined by the kernel. Currently
380 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
381 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
382 * or passes along the return value of clk_set_rate().
383 */
384static int __init _omap2_init_reprogram_sdrc(void)
385{
386 struct clk *dpll3_m2_ck;
387 int v = -EINVAL;
388 long rate;
389
390 if (!cpu_is_omap34xx())
391 return 0;
392
393 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
394 if (IS_ERR(dpll3_m2_ck))
395 return -EINVAL;
396
397 rate = clk_get_rate(dpll3_m2_ck);
398 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
399 v = clk_set_rate(dpll3_m2_ck, rate);
400 if (v)
401 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
402
403 clk_put(dpll3_m2_ck);
404
405 return v;
406}
407
408static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
409{
410 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
411}
412
413static void __init omap_hwmod_init_postsetup(void)
414{
415 u8 postsetup_state;
416
417 /* Set the default postsetup state for all hwmods */
418#ifdef CONFIG_PM
419 postsetup_state = _HWMOD_STATE_IDLE;
420#else
421 postsetup_state = _HWMOD_STATE_ENABLED;
422#endif
423 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
424
425 omap_pm_if_early_init();
426}
427
428static void __init __maybe_unused omap_common_late_init(void)
429{
430 omap_mux_late_init();
431 omap2_common_pm_late_init();
432 omap_soc_device_init();
433}
434
435#ifdef CONFIG_SOC_OMAP2420
436void __init omap2420_init_early(void)
437{
438 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
439 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
440 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
441 omap2_control_base_init();
442 omap2xxx_check_revision();
443 omap2_prcm_base_init();
444 omap2xxx_voltagedomains_init();
445 omap242x_powerdomains_init();
446 omap242x_clockdomains_init();
447 omap2420_hwmod_init();
448 omap_hwmod_init_postsetup();
449 omap_clk_soc_init = omap2420_dt_clk_init;
450 rate_table = omap2420_rate_table;
451}
452
453void __init omap2420_init_late(void)
454{
455 omap_common_late_init();
456 omap2_pm_init();
457 omap2_clk_enable_autoidle_all();
458}
459#endif
460
461#ifdef CONFIG_SOC_OMAP2430
462void __init omap2430_init_early(void)
463{
464 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
465 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
466 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
467 omap2_control_base_init();
468 omap2xxx_check_revision();
469 omap2_prcm_base_init();
470 omap2xxx_voltagedomains_init();
471 omap243x_powerdomains_init();
472 omap243x_clockdomains_init();
473 omap2430_hwmod_init();
474 omap_hwmod_init_postsetup();
475 omap_clk_soc_init = omap2430_dt_clk_init;
476 rate_table = omap2430_rate_table;
477}
478
479void __init omap2430_init_late(void)
480{
481 omap_common_late_init();
482 omap2_pm_init();
483 omap2_clk_enable_autoidle_all();
484}
485#endif
486
487/*
488 * Currently only board-omap3beagle.c should call this because of the
489 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
490 */
491#ifdef CONFIG_ARCH_OMAP3
492void __init omap3_init_early(void)
493{
494 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
495 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
496 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
497 /* XXX: remove these once OMAP3 is DT only */
498 if (!of_have_populated_dt()) {
499 omap2_set_globals_control(
500 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE));
501 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
502 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
503 NULL);
504 }
505 omap2_control_base_init();
506 omap3xxx_check_revision();
507 omap3xxx_check_features();
508 omap2_prcm_base_init();
509 /* XXX: remove these once OMAP3 is DT only */
510 if (!of_have_populated_dt()) {
511 omap3xxx_prm_init(NULL);
512 omap3xxx_cm_init(NULL);
513 }
514 omap3xxx_voltagedomains_init();
515 omap3xxx_powerdomains_init();
516 omap3xxx_clockdomains_init();
517 omap3xxx_hwmod_init();
518 omap_hwmod_init_postsetup();
519 if (!of_have_populated_dt()) {
520 omap3_control_legacy_iomap_init();
521 if (soc_is_am35xx())
522 omap_clk_soc_init = am35xx_clk_legacy_init;
523 else if (cpu_is_omap3630())
524 omap_clk_soc_init = omap36xx_clk_legacy_init;
525 else if (omap_rev() == OMAP3430_REV_ES1_0)
526 omap_clk_soc_init = omap3430es1_clk_legacy_init;
527 else
528 omap_clk_soc_init = omap3430_clk_legacy_init;
529 }
530}
531
532void __init omap3430_init_early(void)
533{
534 omap3_init_early();
535 if (of_have_populated_dt())
536 omap_clk_soc_init = omap3430_dt_clk_init;
537}
538
539void __init omap35xx_init_early(void)
540{
541 omap3_init_early();
542 if (of_have_populated_dt())
543 omap_clk_soc_init = omap3430_dt_clk_init;
544}
545
546void __init omap3630_init_early(void)
547{
548 omap3_init_early();
549 if (of_have_populated_dt())
550 omap_clk_soc_init = omap3630_dt_clk_init;
551}
552
553void __init am35xx_init_early(void)
554{
555 omap3_init_early();
556 if (of_have_populated_dt())
557 omap_clk_soc_init = am35xx_dt_clk_init;
558}
559
560void __init omap3_init_late(void)
561{
562 omap_common_late_init();
563 omap3_pm_init();
564 omap2_clk_enable_autoidle_all();
565}
566
567void __init omap3430_init_late(void)
568{
569 omap_common_late_init();
570 omap3_pm_init();
571 omap2_clk_enable_autoidle_all();
572}
573
574void __init omap35xx_init_late(void)
575{
576 omap_common_late_init();
577 omap3_pm_init();
578 omap2_clk_enable_autoidle_all();
579}
580
581void __init omap3630_init_late(void)
582{
583 omap_common_late_init();
584 omap3_pm_init();
585 omap2_clk_enable_autoidle_all();
586}
587
588void __init am35xx_init_late(void)
589{
590 omap_common_late_init();
591 omap3_pm_init();
592 omap2_clk_enable_autoidle_all();
593}
594
595void __init ti81xx_init_late(void)
596{
597 omap_common_late_init();
598 omap2_clk_enable_autoidle_all();
599}
600#endif
601
602#ifdef CONFIG_SOC_TI81XX
603void __init ti814x_init_early(void)
604{
605 omap2_set_globals_tap(TI814X_CLASS,
606 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
607 omap2_control_base_init();
608 omap3xxx_check_revision();
609 ti81xx_check_features();
610 omap2_prcm_base_init();
611 omap3xxx_voltagedomains_init();
612 omap3xxx_powerdomains_init();
613 ti814x_clockdomains_init();
614 dm814x_hwmod_init();
615 omap_hwmod_init_postsetup();
616 omap_clk_soc_init = dm814x_dt_clk_init;
617}
618
619void __init ti816x_init_early(void)
620{
621 omap2_set_globals_tap(TI816X_CLASS,
622 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
623 omap2_control_base_init();
624 omap3xxx_check_revision();
625 ti81xx_check_features();
626 omap2_prcm_base_init();
627 omap3xxx_voltagedomains_init();
628 omap3xxx_powerdomains_init();
629 ti816x_clockdomains_init();
630 dm816x_hwmod_init();
631 omap_hwmod_init_postsetup();
632 if (of_have_populated_dt())
633 omap_clk_soc_init = dm816x_dt_clk_init;
634}
635#endif
636
637#ifdef CONFIG_SOC_AM33XX
638void __init am33xx_init_early(void)
639{
640 omap2_set_globals_tap(AM335X_CLASS,
641 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
642 omap2_control_base_init();
643 omap3xxx_check_revision();
644 am33xx_check_features();
645 omap2_prcm_base_init();
646 am33xx_powerdomains_init();
647 am33xx_clockdomains_init();
648 am33xx_hwmod_init();
649 omap_hwmod_init_postsetup();
650 omap_clk_soc_init = am33xx_dt_clk_init;
651}
652
653void __init am33xx_init_late(void)
654{
655 omap_common_late_init();
656}
657#endif
658
659#ifdef CONFIG_SOC_AM43XX
660void __init am43xx_init_early(void)
661{
662 omap2_set_globals_tap(AM335X_CLASS,
663 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
664 omap2_control_base_init();
665 omap3xxx_check_revision();
666 am33xx_check_features();
667 omap2_prcm_base_init();
668 am43xx_powerdomains_init();
669 am43xx_clockdomains_init();
670 am43xx_hwmod_init();
671 omap_hwmod_init_postsetup();
672 omap_l2_cache_init();
673 omap_clk_soc_init = am43xx_dt_clk_init;
674}
675
676void __init am43xx_init_late(void)
677{
678 omap_common_late_init();
679 omap2_clk_enable_autoidle_all();
680}
681#endif
682
683#ifdef CONFIG_ARCH_OMAP4
684void __init omap4430_init_early(void)
685{
686 omap2_set_globals_tap(OMAP443X_CLASS,
687 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
688 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
689 omap2_control_base_init();
690 omap4xxx_check_revision();
691 omap4xxx_check_features();
692 omap2_prcm_base_init();
693 omap4_pm_init_early();
694 omap44xx_voltagedomains_init();
695 omap44xx_powerdomains_init();
696 omap44xx_clockdomains_init();
697 omap44xx_hwmod_init();
698 omap_hwmod_init_postsetup();
699 omap_l2_cache_init();
700 omap_clk_soc_init = omap4xxx_dt_clk_init;
701}
702
703void __init omap4430_init_late(void)
704{
705 omap_common_late_init();
706 omap4_pm_init();
707 omap2_clk_enable_autoidle_all();
708}
709#endif
710
711#ifdef CONFIG_SOC_OMAP5
712void __init omap5_init_early(void)
713{
714 omap2_set_globals_tap(OMAP54XX_CLASS,
715 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
716 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
717 omap2_control_base_init();
718 omap4_pm_init_early();
719 omap2_prcm_base_init();
720 omap5xxx_check_revision();
721 omap54xx_voltagedomains_init();
722 omap54xx_powerdomains_init();
723 omap54xx_clockdomains_init();
724 omap54xx_hwmod_init();
725 omap_hwmod_init_postsetup();
726 omap_clk_soc_init = omap5xxx_dt_clk_init;
727}
728
729void __init omap5_init_late(void)
730{
731 omap_common_late_init();
732 omap4_pm_init();
733 omap2_clk_enable_autoidle_all();
734}
735#endif
736
737#ifdef CONFIG_SOC_DRA7XX
738void __init dra7xx_init_early(void)
739{
740 omap2_set_globals_tap(DRA7XX_CLASS,
741 OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
742 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
743 omap2_control_base_init();
744 omap4_pm_init_early();
745 omap2_prcm_base_init();
746 dra7xxx_check_revision();
747 dra7xx_powerdomains_init();
748 dra7xx_clockdomains_init();
749 dra7xx_hwmod_init();
750 omap_hwmod_init_postsetup();
751 omap_clk_soc_init = dra7xx_dt_clk_init;
752}
753
754void __init dra7xx_init_late(void)
755{
756 omap_common_late_init();
757 omap4_pm_init();
758 omap2_clk_enable_autoidle_all();
759}
760#endif
761
762
763void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
764 struct omap_sdrc_params *sdrc_cs1)
765{
766 omap_sram_init();
767
768 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
769 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
770 _omap2_init_reprogram_sdrc();
771 }
772}
773
774int __init omap_clk_init(void)
775{
776 int ret = 0;
777
778 if (!omap_clk_soc_init)
779 return 0;
780
781 ti_clk_init_features();
782
783 omap2_clk_setup_ll_ops();
784
785 if (of_have_populated_dt()) {
786 ret = omap_control_init();
787 if (ret)
788 return ret;
789
790 ret = omap_prcm_init();
791 if (ret)
792 return ret;
793
794 of_clk_init(NULL);
795
796 ti_dt_clk_init_retry_clks();
797
798 ti_dt_clockdomains_setup();
799 }
800
801 ret = omap_clk_soc_init();
802
803 return ret;
804}