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1/*
2 * OMAP2+ DMA driver
3 *
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
11 *
12 * Copyright (C) 2009 Texas Instruments
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
15 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
16 * Converted DMA library into platform driver
17 * - G, Manjunath Kondaiah <manjugk@ti.com>
18 *
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation.
22 */
23
24#include <linux/err.h>
25#include <linux/io.h>
26#include <linux/slab.h>
27#include <linux/module.h>
28#include <linux/init.h>
29#include <linux/device.h>
30
31#include <plat/omap_hwmod.h>
32#include <plat/omap_device.h>
33#include <plat/dma.h>
34
35#define OMAP2_DMA_STRIDE 0x60
36
37static u32 errata;
38static u8 dma_stride;
39
40static struct omap_dma_dev_attr *d;
41
42static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;
43
44static u16 reg_map[] = {
45 [REVISION] = 0x00,
46 [GCR] = 0x78,
47 [IRQSTATUS_L0] = 0x08,
48 [IRQSTATUS_L1] = 0x0c,
49 [IRQSTATUS_L2] = 0x10,
50 [IRQSTATUS_L3] = 0x14,
51 [IRQENABLE_L0] = 0x18,
52 [IRQENABLE_L1] = 0x1c,
53 [IRQENABLE_L2] = 0x20,
54 [IRQENABLE_L3] = 0x24,
55 [SYSSTATUS] = 0x28,
56 [OCP_SYSCONFIG] = 0x2c,
57 [CAPS_0] = 0x64,
58 [CAPS_2] = 0x6c,
59 [CAPS_3] = 0x70,
60 [CAPS_4] = 0x74,
61
62 /* Common register offsets */
63 [CCR] = 0x80,
64 [CLNK_CTRL] = 0x84,
65 [CICR] = 0x88,
66 [CSR] = 0x8c,
67 [CSDP] = 0x90,
68 [CEN] = 0x94,
69 [CFN] = 0x98,
70 [CSEI] = 0xa4,
71 [CSFI] = 0xa8,
72 [CDEI] = 0xac,
73 [CDFI] = 0xb0,
74 [CSAC] = 0xb4,
75 [CDAC] = 0xb8,
76
77 /* Channel specific register offsets */
78 [CSSA] = 0x9c,
79 [CDSA] = 0xa0,
80 [CCEN] = 0xbc,
81 [CCFN] = 0xc0,
82 [COLOR] = 0xc4,
83
84 /* OMAP4 specific registers */
85 [CDP] = 0xd0,
86 [CNDP] = 0xd4,
87 [CCDN] = 0xd8,
88};
89
90static void __iomem *dma_base;
91static inline void dma_write(u32 val, int reg, int lch)
92{
93 u8 stride;
94 u32 offset;
95
96 stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
97 offset = reg_map[reg] + (stride * lch);
98 __raw_writel(val, dma_base + offset);
99}
100
101static inline u32 dma_read(int reg, int lch)
102{
103 u8 stride;
104 u32 offset, val;
105
106 stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
107 offset = reg_map[reg] + (stride * lch);
108 val = __raw_readl(dma_base + offset);
109 return val;
110}
111
112static inline void omap2_disable_irq_lch(int lch)
113{
114 u32 val;
115
116 val = dma_read(IRQENABLE_L0, lch);
117 val &= ~(1 << lch);
118 dma_write(val, IRQENABLE_L0, lch);
119}
120
121static void omap2_clear_dma(int lch)
122{
123 int i = dma_common_ch_start;
124
125 for (; i <= dma_common_ch_end; i += 1)
126 dma_write(0, i, lch);
127}
128
129static void omap2_show_dma_caps(void)
130{
131 u8 revision = dma_read(REVISION, 0) & 0xff;
132 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
133 revision >> 4, revision & 0xf);
134 return;
135}
136
137static u32 configure_dma_errata(void)
138{
139
140 /*
141 * Errata applicable for OMAP2430ES1.0 and all omap2420
142 *
143 * I.
144 * Erratum ID: Not Available
145 * Inter Frame DMA buffering issue DMA will wrongly
146 * buffer elements if packing and bursting is enabled. This might
147 * result in data gets stalled in FIFO at the end of the block.
148 * Workaround: DMA channels must have BUFFERING_DISABLED bit set to
149 * guarantee no data will stay in the DMA FIFO in case inter frame
150 * buffering occurs
151 *
152 * II.
153 * Erratum ID: Not Available
154 * DMA may hang when several channels are used in parallel
155 * In the following configuration, DMA channel hanging can occur:
156 * a. Channel i, hardware synchronized, is enabled
157 * b. Another channel (Channel x), software synchronized, is enabled.
158 * c. Channel i is disabled before end of transfer
159 * d. Channel i is reenabled.
160 * e. Steps 1 to 4 are repeated a certain number of times.
161 * f. A third channel (Channel y), software synchronized, is enabled.
162 * Channel x and Channel y may hang immediately after step 'f'.
163 * Workaround:
164 * For any channel used - make sure NextLCH_ID is set to the value j.
165 */
166 if (cpu_is_omap2420() || (cpu_is_omap2430() &&
167 (omap_type() == OMAP2430_REV_ES1_0))) {
168
169 SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING);
170 SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS);
171 }
172
173 /*
174 * Erratum ID: i378: OMAP2+: sDMA Channel is not disabled
175 * after a transaction error.
176 * Workaround: SW should explicitely disable the channel.
177 */
178 if (cpu_class_is_omap2())
179 SET_DMA_ERRATA(DMA_ERRATA_i378);
180
181 /*
182 * Erratum ID: i541: sDMA FIFO draining does not finish
183 * If sDMA channel is disabled on the fly, sDMA enters standby even
184 * through FIFO Drain is still in progress
185 * Workaround: Put sDMA in NoStandby more before a logical channel is
186 * disabled, then put it back to SmartStandby right after the channel
187 * finishes FIFO draining.
188 */
189 if (cpu_is_omap34xx())
190 SET_DMA_ERRATA(DMA_ERRATA_i541);
191
192 /*
193 * Erratum ID: i88 : Special programming model needed to disable DMA
194 * before end of block.
195 * Workaround: software must ensure that the DMA is configured in No
196 * Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01")
197 */
198 if (omap_type() == OMAP3430_REV_ES1_0)
199 SET_DMA_ERRATA(DMA_ERRATA_i88);
200
201 /*
202 * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
203 * read before the DMA controller finished disabling the channel.
204 */
205 SET_DMA_ERRATA(DMA_ERRATA_3_3);
206
207 /*
208 * Erratum ID: Not Available
209 * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
210 * after secure sram context save and restore.
211 * Work around: Hence we need to manually clear those IRQs to avoid
212 * spurious interrupts. This affects only secure devices.
213 */
214 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
215 SET_DMA_ERRATA(DMA_ROMCODE_BUG);
216
217 return errata;
218}
219
220/* One time initializations */
221static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
222{
223 struct platform_device *pdev;
224 struct omap_system_dma_plat_info *p;
225 struct resource *mem;
226 char *name = "omap_dma_system";
227
228 dma_stride = OMAP2_DMA_STRIDE;
229 dma_common_ch_start = CSDP;
230
231 p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
232 if (!p) {
233 pr_err("%s: Unable to allocate pdata for %s:%s\n",
234 __func__, name, oh->name);
235 return -ENOMEM;
236 }
237
238 p->dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr;
239 p->disable_irq_lch = omap2_disable_irq_lch;
240 p->show_dma_caps = omap2_show_dma_caps;
241 p->clear_dma = omap2_clear_dma;
242 p->dma_write = dma_write;
243 p->dma_read = dma_read;
244
245 p->clear_lch_regs = NULL;
246
247 p->errata = configure_dma_errata();
248
249 pdev = omap_device_build(name, 0, oh, p, sizeof(*p), NULL, 0, 0);
250 kfree(p);
251 if (IS_ERR(pdev)) {
252 pr_err("%s: Can't build omap_device for %s:%s.\n",
253 __func__, name, oh->name);
254 return PTR_ERR(pdev);
255 }
256
257 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
258 if (!mem) {
259 dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
260 return -EINVAL;
261 }
262 dma_base = ioremap(mem->start, resource_size(mem));
263 if (!dma_base) {
264 dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
265 return -ENOMEM;
266 }
267
268 d = oh->dev_attr;
269 d->chan = kzalloc(sizeof(struct omap_dma_lch) *
270 (d->lch_count), GFP_KERNEL);
271
272 if (!d->chan) {
273 dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
274 return -ENOMEM;
275 }
276
277 /* Check the capabilities register for descriptor loading feature */
278 if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS)
279 dma_common_ch_end = CCDN;
280 else
281 dma_common_ch_end = CCFN;
282
283 return 0;
284}
285
286static int __init omap2_system_dma_init(void)
287{
288 return omap_hwmod_for_each_by_class("dma",
289 omap2_system_dma_init_dev, NULL);
290}
291arch_initcall(omap2_system_dma_init);
1/*
2 * OMAP2+ DMA driver
3 *
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
11 *
12 * Copyright (C) 2009 Texas Instruments
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
15 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
16 * Converted DMA library into platform driver
17 * - G, Manjunath Kondaiah <manjugk@ti.com>
18 *
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation.
22 */
23
24#include <linux/err.h>
25#include <linux/io.h>
26#include <linux/slab.h>
27#include <linux/module.h>
28#include <linux/init.h>
29#include <linux/device.h>
30#include <linux/dma-mapping.h>
31#include <linux/dmaengine.h>
32#include <linux/of.h>
33#include <linux/omap-dma.h>
34
35#include "soc.h"
36#include "omap_hwmod.h"
37#include "omap_device.h"
38
39static enum omap_reg_offsets dma_common_ch_end;
40
41static const struct omap_dma_reg reg_map[] = {
42 [REVISION] = { 0x0000, 0x00, OMAP_DMA_REG_32BIT },
43 [GCR] = { 0x0078, 0x00, OMAP_DMA_REG_32BIT },
44 [IRQSTATUS_L0] = { 0x0008, 0x00, OMAP_DMA_REG_32BIT },
45 [IRQSTATUS_L1] = { 0x000c, 0x00, OMAP_DMA_REG_32BIT },
46 [IRQSTATUS_L2] = { 0x0010, 0x00, OMAP_DMA_REG_32BIT },
47 [IRQSTATUS_L3] = { 0x0014, 0x00, OMAP_DMA_REG_32BIT },
48 [IRQENABLE_L0] = { 0x0018, 0x00, OMAP_DMA_REG_32BIT },
49 [IRQENABLE_L1] = { 0x001c, 0x00, OMAP_DMA_REG_32BIT },
50 [IRQENABLE_L2] = { 0x0020, 0x00, OMAP_DMA_REG_32BIT },
51 [IRQENABLE_L3] = { 0x0024, 0x00, OMAP_DMA_REG_32BIT },
52 [SYSSTATUS] = { 0x0028, 0x00, OMAP_DMA_REG_32BIT },
53 [OCP_SYSCONFIG] = { 0x002c, 0x00, OMAP_DMA_REG_32BIT },
54 [CAPS_0] = { 0x0064, 0x00, OMAP_DMA_REG_32BIT },
55 [CAPS_2] = { 0x006c, 0x00, OMAP_DMA_REG_32BIT },
56 [CAPS_3] = { 0x0070, 0x00, OMAP_DMA_REG_32BIT },
57 [CAPS_4] = { 0x0074, 0x00, OMAP_DMA_REG_32BIT },
58
59 /* Common register offsets */
60 [CCR] = { 0x0080, 0x60, OMAP_DMA_REG_32BIT },
61 [CLNK_CTRL] = { 0x0084, 0x60, OMAP_DMA_REG_32BIT },
62 [CICR] = { 0x0088, 0x60, OMAP_DMA_REG_32BIT },
63 [CSR] = { 0x008c, 0x60, OMAP_DMA_REG_32BIT },
64 [CSDP] = { 0x0090, 0x60, OMAP_DMA_REG_32BIT },
65 [CEN] = { 0x0094, 0x60, OMAP_DMA_REG_32BIT },
66 [CFN] = { 0x0098, 0x60, OMAP_DMA_REG_32BIT },
67 [CSEI] = { 0x00a4, 0x60, OMAP_DMA_REG_32BIT },
68 [CSFI] = { 0x00a8, 0x60, OMAP_DMA_REG_32BIT },
69 [CDEI] = { 0x00ac, 0x60, OMAP_DMA_REG_32BIT },
70 [CDFI] = { 0x00b0, 0x60, OMAP_DMA_REG_32BIT },
71 [CSAC] = { 0x00b4, 0x60, OMAP_DMA_REG_32BIT },
72 [CDAC] = { 0x00b8, 0x60, OMAP_DMA_REG_32BIT },
73
74 /* Channel specific register offsets */
75 [CSSA] = { 0x009c, 0x60, OMAP_DMA_REG_32BIT },
76 [CDSA] = { 0x00a0, 0x60, OMAP_DMA_REG_32BIT },
77 [CCEN] = { 0x00bc, 0x60, OMAP_DMA_REG_32BIT },
78 [CCFN] = { 0x00c0, 0x60, OMAP_DMA_REG_32BIT },
79 [COLOR] = { 0x00c4, 0x60, OMAP_DMA_REG_32BIT },
80
81 /* OMAP4 specific registers */
82 [CDP] = { 0x00d0, 0x60, OMAP_DMA_REG_32BIT },
83 [CNDP] = { 0x00d4, 0x60, OMAP_DMA_REG_32BIT },
84 [CCDN] = { 0x00d8, 0x60, OMAP_DMA_REG_32BIT },
85};
86
87static void __iomem *dma_base;
88static inline void dma_write(u32 val, int reg, int lch)
89{
90 void __iomem *addr = dma_base;
91
92 addr += reg_map[reg].offset;
93 addr += reg_map[reg].stride * lch;
94
95 writel_relaxed(val, addr);
96}
97
98static inline u32 dma_read(int reg, int lch)
99{
100 void __iomem *addr = dma_base;
101
102 addr += reg_map[reg].offset;
103 addr += reg_map[reg].stride * lch;
104
105 return readl_relaxed(addr);
106}
107
108static void omap2_clear_dma(int lch)
109{
110 int i;
111
112 for (i = CSDP; i <= dma_common_ch_end; i += 1)
113 dma_write(0, i, lch);
114}
115
116static void omap2_show_dma_caps(void)
117{
118 u8 revision = dma_read(REVISION, 0) & 0xff;
119 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
120 revision >> 4, revision & 0xf);
121}
122
123static unsigned configure_dma_errata(void)
124{
125 unsigned errata = 0;
126
127 /*
128 * Errata applicable for OMAP2430ES1.0 and all omap2420
129 *
130 * I.
131 * Erratum ID: Not Available
132 * Inter Frame DMA buffering issue DMA will wrongly
133 * buffer elements if packing and bursting is enabled. This might
134 * result in data gets stalled in FIFO at the end of the block.
135 * Workaround: DMA channels must have BUFFERING_DISABLED bit set to
136 * guarantee no data will stay in the DMA FIFO in case inter frame
137 * buffering occurs
138 *
139 * II.
140 * Erratum ID: Not Available
141 * DMA may hang when several channels are used in parallel
142 * In the following configuration, DMA channel hanging can occur:
143 * a. Channel i, hardware synchronized, is enabled
144 * b. Another channel (Channel x), software synchronized, is enabled.
145 * c. Channel i is disabled before end of transfer
146 * d. Channel i is reenabled.
147 * e. Steps 1 to 4 are repeated a certain number of times.
148 * f. A third channel (Channel y), software synchronized, is enabled.
149 * Channel x and Channel y may hang immediately after step 'f'.
150 * Workaround:
151 * For any channel used - make sure NextLCH_ID is set to the value j.
152 */
153 if (cpu_is_omap2420() || (cpu_is_omap2430() &&
154 (omap_type() == OMAP2430_REV_ES1_0))) {
155
156 SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING);
157 SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS);
158 }
159
160 /*
161 * Erratum ID: i378: OMAP2+: sDMA Channel is not disabled
162 * after a transaction error.
163 * Workaround: SW should explicitely disable the channel.
164 */
165 if (cpu_class_is_omap2())
166 SET_DMA_ERRATA(DMA_ERRATA_i378);
167
168 /*
169 * Erratum ID: i541: sDMA FIFO draining does not finish
170 * If sDMA channel is disabled on the fly, sDMA enters standby even
171 * through FIFO Drain is still in progress
172 * Workaround: Put sDMA in NoStandby more before a logical channel is
173 * disabled, then put it back to SmartStandby right after the channel
174 * finishes FIFO draining.
175 */
176 if (cpu_is_omap34xx())
177 SET_DMA_ERRATA(DMA_ERRATA_i541);
178
179 /*
180 * Erratum ID: i88 : Special programming model needed to disable DMA
181 * before end of block.
182 * Workaround: software must ensure that the DMA is configured in No
183 * Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01")
184 */
185 if (omap_type() == OMAP3430_REV_ES1_0)
186 SET_DMA_ERRATA(DMA_ERRATA_i88);
187
188 /*
189 * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
190 * read before the DMA controller finished disabling the channel.
191 */
192 SET_DMA_ERRATA(DMA_ERRATA_3_3);
193
194 /*
195 * Erratum ID: Not Available
196 * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
197 * after secure sram context save and restore.
198 * Work around: Hence we need to manually clear those IRQs to avoid
199 * spurious interrupts. This affects only secure devices.
200 */
201 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
202 SET_DMA_ERRATA(DMA_ROMCODE_BUG);
203
204 return errata;
205}
206
207static const struct dma_slave_map omap24xx_sdma_map[] = {
208 { "omap-gpmc", "rxtx", SDMA_FILTER_PARAM(4) },
209 { "omap-aes", "tx", SDMA_FILTER_PARAM(9) },
210 { "omap-aes", "rx", SDMA_FILTER_PARAM(10) },
211 { "omap-sham", "rx", SDMA_FILTER_PARAM(13) },
212 { "omap2_mcspi.2", "tx0", SDMA_FILTER_PARAM(15) },
213 { "omap2_mcspi.2", "rx0", SDMA_FILTER_PARAM(16) },
214 { "omap-mcbsp.3", "tx", SDMA_FILTER_PARAM(17) },
215 { "omap-mcbsp.3", "rx", SDMA_FILTER_PARAM(18) },
216 { "omap-mcbsp.4", "tx", SDMA_FILTER_PARAM(19) },
217 { "omap-mcbsp.4", "rx", SDMA_FILTER_PARAM(20) },
218 { "omap-mcbsp.5", "tx", SDMA_FILTER_PARAM(21) },
219 { "omap-mcbsp.5", "rx", SDMA_FILTER_PARAM(22) },
220 { "omap2_mcspi.2", "tx1", SDMA_FILTER_PARAM(23) },
221 { "omap2_mcspi.2", "rx1", SDMA_FILTER_PARAM(24) },
222 { "omap_i2c.1", "tx", SDMA_FILTER_PARAM(27) },
223 { "omap_i2c.1", "rx", SDMA_FILTER_PARAM(28) },
224 { "omap_i2c.2", "tx", SDMA_FILTER_PARAM(29) },
225 { "omap_i2c.2", "rx", SDMA_FILTER_PARAM(30) },
226 { "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(31) },
227 { "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(32) },
228 { "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(33) },
229 { "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(34) },
230 { "omap2_mcspi.0", "tx0", SDMA_FILTER_PARAM(35) },
231 { "omap2_mcspi.0", "rx0", SDMA_FILTER_PARAM(36) },
232 { "omap2_mcspi.0", "tx1", SDMA_FILTER_PARAM(37) },
233 { "omap2_mcspi.0", "rx1", SDMA_FILTER_PARAM(38) },
234 { "omap2_mcspi.0", "tx2", SDMA_FILTER_PARAM(39) },
235 { "omap2_mcspi.0", "rx2", SDMA_FILTER_PARAM(40) },
236 { "omap2_mcspi.0", "tx3", SDMA_FILTER_PARAM(41) },
237 { "omap2_mcspi.0", "rx3", SDMA_FILTER_PARAM(42) },
238 { "omap2_mcspi.1", "tx0", SDMA_FILTER_PARAM(43) },
239 { "omap2_mcspi.1", "rx0", SDMA_FILTER_PARAM(44) },
240 { "omap2_mcspi.1", "tx1", SDMA_FILTER_PARAM(45) },
241 { "omap2_mcspi.1", "rx1", SDMA_FILTER_PARAM(46) },
242 { "omap_hsmmc.1", "tx", SDMA_FILTER_PARAM(47) },
243 { "omap_hsmmc.1", "rx", SDMA_FILTER_PARAM(48) },
244 { "omap_uart.0", "tx", SDMA_FILTER_PARAM(49) },
245 { "omap_uart.0", "rx", SDMA_FILTER_PARAM(50) },
246 { "omap_uart.1", "tx", SDMA_FILTER_PARAM(51) },
247 { "omap_uart.1", "rx", SDMA_FILTER_PARAM(52) },
248 { "omap_uart.2", "tx", SDMA_FILTER_PARAM(53) },
249 { "omap_uart.2", "rx", SDMA_FILTER_PARAM(54) },
250 { "omap_hsmmc.0", "tx", SDMA_FILTER_PARAM(61) },
251 { "omap_hsmmc.0", "rx", SDMA_FILTER_PARAM(62) },
252};
253
254static const struct dma_slave_map omap3xxx_sdma_map[] = {
255 { "omap-gpmc", "rxtx", SDMA_FILTER_PARAM(4) },
256 { "omap2_mcspi.2", "tx0", SDMA_FILTER_PARAM(15) },
257 { "omap2_mcspi.2", "rx0", SDMA_FILTER_PARAM(16) },
258 { "omap-mcbsp.3", "tx", SDMA_FILTER_PARAM(17) },
259 { "omap-mcbsp.3", "rx", SDMA_FILTER_PARAM(18) },
260 { "omap-mcbsp.4", "tx", SDMA_FILTER_PARAM(19) },
261 { "omap-mcbsp.4", "rx", SDMA_FILTER_PARAM(20) },
262 { "omap-mcbsp.5", "tx", SDMA_FILTER_PARAM(21) },
263 { "omap-mcbsp.5", "rx", SDMA_FILTER_PARAM(22) },
264 { "omap2_mcspi.2", "tx1", SDMA_FILTER_PARAM(23) },
265 { "omap2_mcspi.2", "rx1", SDMA_FILTER_PARAM(24) },
266 { "omap_i2c.3", "tx", SDMA_FILTER_PARAM(25) },
267 { "omap_i2c.3", "rx", SDMA_FILTER_PARAM(26) },
268 { "omap_i2c.1", "tx", SDMA_FILTER_PARAM(27) },
269 { "omap_i2c.1", "rx", SDMA_FILTER_PARAM(28) },
270 { "omap_i2c.2", "tx", SDMA_FILTER_PARAM(29) },
271 { "omap_i2c.2", "rx", SDMA_FILTER_PARAM(30) },
272 { "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(31) },
273 { "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(32) },
274 { "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(33) },
275 { "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(34) },
276 { "omap2_mcspi.0", "tx0", SDMA_FILTER_PARAM(35) },
277 { "omap2_mcspi.0", "rx0", SDMA_FILTER_PARAM(36) },
278 { "omap2_mcspi.0", "tx1", SDMA_FILTER_PARAM(37) },
279 { "omap2_mcspi.0", "rx1", SDMA_FILTER_PARAM(38) },
280 { "omap2_mcspi.0", "tx2", SDMA_FILTER_PARAM(39) },
281 { "omap2_mcspi.0", "rx2", SDMA_FILTER_PARAM(40) },
282 { "omap2_mcspi.0", "tx3", SDMA_FILTER_PARAM(41) },
283 { "omap2_mcspi.0", "rx3", SDMA_FILTER_PARAM(42) },
284 { "omap2_mcspi.1", "tx0", SDMA_FILTER_PARAM(43) },
285 { "omap2_mcspi.1", "rx0", SDMA_FILTER_PARAM(44) },
286 { "omap2_mcspi.1", "tx1", SDMA_FILTER_PARAM(45) },
287 { "omap2_mcspi.1", "rx1", SDMA_FILTER_PARAM(46) },
288 { "omap_hsmmc.1", "tx", SDMA_FILTER_PARAM(47) },
289 { "omap_hsmmc.1", "rx", SDMA_FILTER_PARAM(48) },
290 { "omap_uart.0", "tx", SDMA_FILTER_PARAM(49) },
291 { "omap_uart.0", "rx", SDMA_FILTER_PARAM(50) },
292 { "omap_uart.1", "tx", SDMA_FILTER_PARAM(51) },
293 { "omap_uart.1", "rx", SDMA_FILTER_PARAM(52) },
294 { "omap_uart.2", "tx", SDMA_FILTER_PARAM(53) },
295 { "omap_uart.2", "rx", SDMA_FILTER_PARAM(54) },
296 { "omap_hsmmc.0", "tx", SDMA_FILTER_PARAM(61) },
297 { "omap_hsmmc.0", "rx", SDMA_FILTER_PARAM(62) },
298 { "omap-aes", "tx", SDMA_FILTER_PARAM(65) },
299 { "omap-aes", "rx", SDMA_FILTER_PARAM(66) },
300 { "omap-sham", "rx", SDMA_FILTER_PARAM(69) },
301 { "omap2_mcspi.3", "tx0", SDMA_FILTER_PARAM(70) },
302 { "omap2_mcspi.3", "rx0", SDMA_FILTER_PARAM(71) },
303 { "omap_hsmmc.2", "tx", SDMA_FILTER_PARAM(77) },
304 { "omap_hsmmc.2", "rx", SDMA_FILTER_PARAM(78) },
305 { "omap_uart.3", "tx", SDMA_FILTER_PARAM(81) },
306 { "omap_uart.3", "rx", SDMA_FILTER_PARAM(82) },
307};
308
309static struct omap_system_dma_plat_info dma_plat_info __initdata = {
310 .reg_map = reg_map,
311 .channel_stride = 0x60,
312 .show_dma_caps = omap2_show_dma_caps,
313 .clear_dma = omap2_clear_dma,
314 .dma_write = dma_write,
315 .dma_read = dma_read,
316};
317
318static struct platform_device_info omap_dma_dev_info = {
319 .name = "omap-dma-engine",
320 .id = -1,
321 .dma_mask = DMA_BIT_MASK(32),
322};
323
324/* One time initializations */
325static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
326{
327 struct platform_device *pdev;
328 struct omap_system_dma_plat_info p;
329 struct omap_dma_dev_attr *d;
330 struct resource *mem;
331 char *name = "omap_dma_system";
332
333 p = dma_plat_info;
334 p.dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr;
335 p.errata = configure_dma_errata();
336
337 if (!of_have_populated_dt()) {
338 if (soc_is_omap24xx()) {
339 p.slave_map = omap24xx_sdma_map;
340 p.slavecnt = ARRAY_SIZE(omap24xx_sdma_map);
341 } else if (soc_is_omap34xx() || soc_is_omap3630()) {
342 p.slave_map = omap3xxx_sdma_map;
343 p.slavecnt = ARRAY_SIZE(omap3xxx_sdma_map);
344 } else {
345 pr_err("%s: The legacy DMA map is not provided!\n",
346 __func__);
347 return -ENODEV;
348 }
349 }
350
351 pdev = omap_device_build(name, 0, oh, &p, sizeof(p));
352 if (IS_ERR(pdev)) {
353 pr_err("%s: Can't build omap_device for %s:%s.\n",
354 __func__, name, oh->name);
355 return PTR_ERR(pdev);
356 }
357
358 omap_dma_dev_info.res = pdev->resource;
359 omap_dma_dev_info.num_res = pdev->num_resources;
360
361 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
362 if (!mem) {
363 dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
364 return -EINVAL;
365 }
366
367 dma_base = ioremap(mem->start, resource_size(mem));
368 if (!dma_base) {
369 dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
370 return -ENOMEM;
371 }
372
373 d = oh->dev_attr;
374
375 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
376 d->dev_caps |= HS_CHANNELS_RESERVED;
377
378 if (platform_get_irq_byname(pdev, "0") < 0)
379 d->dev_caps |= DMA_ENGINE_HANDLE_IRQ;
380
381 /* Check the capabilities register for descriptor loading feature */
382 if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS)
383 dma_common_ch_end = CCDN;
384 else
385 dma_common_ch_end = CCFN;
386
387 return 0;
388}
389
390static int __init omap2_system_dma_init(void)
391{
392 struct platform_device *pdev;
393 int res;
394
395 res = omap_hwmod_for_each_by_class("dma",
396 omap2_system_dma_init_dev, NULL);
397 if (res)
398 return res;
399
400 if (of_have_populated_dt())
401 return res;
402
403 pdev = platform_device_register_full(&omap_dma_dev_info);
404 if (IS_ERR(pdev))
405 return PTR_ERR(pdev);
406
407 return res;
408}
409omap_arch_initcall(omap2_system_dma_init);