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1/* SPDX-License-Identifier: GPL-2.0 */
2/*******************************************************************************
3 *
4 * Intel Ethernet Controller XL710 Family Linux Driver
5 * Copyright(c) 2013 - 2017 Intel Corporation.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 *
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *
26 ******************************************************************************/
27
28#ifndef _I40E_H_
29#define _I40E_H_
30
31#include <net/tcp.h>
32#include <net/udp.h>
33#include <linux/types.h>
34#include <linux/errno.h>
35#include <linux/module.h>
36#include <linux/pci.h>
37#include <linux/aer.h>
38#include <linux/netdevice.h>
39#include <linux/ioport.h>
40#include <linux/iommu.h>
41#include <linux/slab.h>
42#include <linux/list.h>
43#include <linux/hashtable.h>
44#include <linux/string.h>
45#include <linux/in.h>
46#include <linux/ip.h>
47#include <linux/sctp.h>
48#include <linux/pkt_sched.h>
49#include <linux/ipv6.h>
50#include <net/checksum.h>
51#include <net/ip6_checksum.h>
52#include <linux/ethtool.h>
53#include <linux/if_vlan.h>
54#include <linux/if_bridge.h>
55#include <linux/clocksource.h>
56#include <linux/net_tstamp.h>
57#include <linux/ptp_clock_kernel.h>
58#include <net/pkt_cls.h>
59#include <net/tc_act/tc_gact.h>
60#include <net/tc_act/tc_mirred.h>
61#include "i40e_type.h"
62#include "i40e_prototype.h"
63#include "i40e_client.h"
64#include <linux/avf/virtchnl.h>
65#include "i40e_virtchnl_pf.h"
66#include "i40e_txrx.h"
67#include "i40e_dcb.h"
68
69/* Useful i40e defaults */
70#define I40E_MAX_VEB 16
71
72#define I40E_MAX_NUM_DESCRIPTORS 4096
73#define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024)
74#define I40E_DEFAULT_NUM_DESCRIPTORS 512
75#define I40E_REQ_DESCRIPTOR_MULTIPLE 32
76#define I40E_MIN_NUM_DESCRIPTORS 64
77#define I40E_MIN_MSIX 2
78#define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */
79#define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */
80/* max 16 qps */
81#define i40e_default_queues_per_vmdq(pf) \
82 (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1)
83#define I40E_DEFAULT_QUEUES_PER_VF 4
84#define I40E_MAX_VF_QUEUES 16
85#define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */
86#define i40e_pf_get_max_q_per_tc(pf) \
87 (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64)
88#define I40E_FDIR_RING 0
89#define I40E_FDIR_RING_COUNT 32
90#define I40E_MAX_AQ_BUF_SIZE 4096
91#define I40E_AQ_LEN 256
92#define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */
93#define I40E_MAX_USER_PRIORITY 8
94#define I40E_DEFAULT_TRAFFIC_CLASS BIT(0)
95#define I40E_DEFAULT_MSG_ENABLE 4
96#define I40E_QUEUE_WAIT_RETRY_LIMIT 10
97#define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16)
98
99#define I40E_NVM_VERSION_LO_SHIFT 0
100#define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT)
101#define I40E_NVM_VERSION_HI_SHIFT 12
102#define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT)
103#define I40E_OEM_VER_BUILD_MASK 0xffff
104#define I40E_OEM_VER_PATCH_MASK 0xff
105#define I40E_OEM_VER_BUILD_SHIFT 8
106#define I40E_OEM_VER_SHIFT 24
107#define I40E_PHY_DEBUG_ALL \
108 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \
109 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW)
110
111#define I40E_OEM_EETRACK_ID 0xffffffff
112#define I40E_OEM_GEN_SHIFT 24
113#define I40E_OEM_SNAP_MASK 0x00ff0000
114#define I40E_OEM_SNAP_SHIFT 16
115#define I40E_OEM_RELEASE_MASK 0x0000ffff
116
117/* The values in here are decimal coded as hex as is the case in the NVM map*/
118#define I40E_CURRENT_NVM_VERSION_HI 0x2
119#define I40E_CURRENT_NVM_VERSION_LO 0x40
120
121#define I40E_RX_DESC(R, i) \
122 (&(((union i40e_32byte_rx_desc *)((R)->desc))[i]))
123#define I40E_TX_DESC(R, i) \
124 (&(((struct i40e_tx_desc *)((R)->desc))[i]))
125#define I40E_TX_CTXTDESC(R, i) \
126 (&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
127#define I40E_TX_FDIRDESC(R, i) \
128 (&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
129
130/* default to trying for four seconds */
131#define I40E_TRY_LINK_TIMEOUT (4 * HZ)
132
133/* BW rate limiting */
134#define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */
135#define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */
136#define I40E_MAX_BW_INACTIVE_ACCUM 4 /* accumulate 4 credits max */
137
138/* driver state flags */
139enum i40e_state_t {
140 __I40E_TESTING,
141 __I40E_CONFIG_BUSY,
142 __I40E_CONFIG_DONE,
143 __I40E_DOWN,
144 __I40E_SERVICE_SCHED,
145 __I40E_ADMINQ_EVENT_PENDING,
146 __I40E_MDD_EVENT_PENDING,
147 __I40E_VFLR_EVENT_PENDING,
148 __I40E_RESET_RECOVERY_PENDING,
149 __I40E_MISC_IRQ_REQUESTED,
150 __I40E_RESET_INTR_RECEIVED,
151 __I40E_REINIT_REQUESTED,
152 __I40E_PF_RESET_REQUESTED,
153 __I40E_CORE_RESET_REQUESTED,
154 __I40E_GLOBAL_RESET_REQUESTED,
155 __I40E_EMP_RESET_REQUESTED,
156 __I40E_EMP_RESET_INTR_RECEIVED,
157 __I40E_SUSPENDED,
158 __I40E_PTP_TX_IN_PROGRESS,
159 __I40E_BAD_EEPROM,
160 __I40E_DOWN_REQUESTED,
161 __I40E_FD_FLUSH_REQUESTED,
162 __I40E_FD_ATR_AUTO_DISABLED,
163 __I40E_FD_SB_AUTO_DISABLED,
164 __I40E_RESET_FAILED,
165 __I40E_PORT_SUSPENDED,
166 __I40E_VF_DISABLE,
167 __I40E_MACVLAN_SYNC_PENDING,
168 __I40E_UDP_FILTER_SYNC_PENDING,
169 __I40E_TEMP_LINK_POLLING,
170 __I40E_CLIENT_SERVICE_REQUESTED,
171 __I40E_CLIENT_L2_CHANGE,
172 __I40E_CLIENT_RESET,
173 /* This must be last as it determines the size of the BITMAP */
174 __I40E_STATE_SIZE__,
175};
176
177#define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED)
178
179/* VSI state flags */
180enum i40e_vsi_state_t {
181 __I40E_VSI_DOWN,
182 __I40E_VSI_NEEDS_RESTART,
183 __I40E_VSI_SYNCING_FILTERS,
184 __I40E_VSI_OVERFLOW_PROMISC,
185 __I40E_VSI_REINIT_REQUESTED,
186 __I40E_VSI_DOWN_REQUESTED,
187 /* This must be last as it determines the size of the BITMAP */
188 __I40E_VSI_STATE_SIZE__,
189};
190
191enum i40e_interrupt_policy {
192 I40E_INTERRUPT_BEST_CASE,
193 I40E_INTERRUPT_MEDIUM,
194 I40E_INTERRUPT_LOWEST
195};
196
197struct i40e_lump_tracking {
198 u16 num_entries;
199 u16 search_hint;
200 u16 list[0];
201#define I40E_PILE_VALID_BIT 0x8000
202#define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2)
203};
204
205#define I40E_DEFAULT_ATR_SAMPLE_RATE 20
206#define I40E_FDIR_MAX_RAW_PACKET_SIZE 512
207#define I40E_FDIR_BUFFER_FULL_MARGIN 10
208#define I40E_FDIR_BUFFER_HEAD_ROOM 32
209#define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4)
210
211#define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4)
212#define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4)
213#define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4)
214
215enum i40e_fd_stat_idx {
216 I40E_FD_STAT_ATR,
217 I40E_FD_STAT_SB,
218 I40E_FD_STAT_ATR_TUNNEL,
219 I40E_FD_STAT_PF_COUNT
220};
221#define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT)
222#define I40E_FD_ATR_STAT_IDX(pf_id) \
223 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR)
224#define I40E_FD_SB_STAT_IDX(pf_id) \
225 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB)
226#define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \
227 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL)
228
229/* The following structure contains the data parsed from the user-defined
230 * field of the ethtool_rx_flow_spec structure.
231 */
232struct i40e_rx_flow_userdef {
233 bool flex_filter;
234 u16 flex_word;
235 u16 flex_offset;
236};
237
238struct i40e_fdir_filter {
239 struct hlist_node fdir_node;
240 /* filter ipnut set */
241 u8 flow_type;
242 u8 ip4_proto;
243 /* TX packet view of src and dst */
244 __be32 dst_ip;
245 __be32 src_ip;
246 __be16 src_port;
247 __be16 dst_port;
248 __be32 sctp_v_tag;
249
250 /* Flexible data to match within the packet payload */
251 __be16 flex_word;
252 u16 flex_offset;
253 bool flex_filter;
254
255 /* filter control */
256 u16 q_index;
257 u8 flex_off;
258 u8 pctype;
259 u16 dest_vsi;
260 u8 dest_ctl;
261 u8 fd_status;
262 u16 cnt_index;
263 u32 fd_id;
264};
265
266#define I40E_CLOUD_FIELD_OMAC 0x01
267#define I40E_CLOUD_FIELD_IMAC 0x02
268#define I40E_CLOUD_FIELD_IVLAN 0x04
269#define I40E_CLOUD_FIELD_TEN_ID 0x08
270#define I40E_CLOUD_FIELD_IIP 0x10
271
272#define I40E_CLOUD_FILTER_FLAGS_OMAC I40E_CLOUD_FIELD_OMAC
273#define I40E_CLOUD_FILTER_FLAGS_IMAC I40E_CLOUD_FIELD_IMAC
274#define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN (I40E_CLOUD_FIELD_IMAC | \
275 I40E_CLOUD_FIELD_IVLAN)
276#define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
277 I40E_CLOUD_FIELD_TEN_ID)
278#define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \
279 I40E_CLOUD_FIELD_IMAC | \
280 I40E_CLOUD_FIELD_TEN_ID)
281#define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
282 I40E_CLOUD_FIELD_IVLAN | \
283 I40E_CLOUD_FIELD_TEN_ID)
284#define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP
285
286struct i40e_cloud_filter {
287 struct hlist_node cloud_node;
288 unsigned long cookie;
289 /* cloud filter input set follows */
290 u8 dst_mac[ETH_ALEN];
291 u8 src_mac[ETH_ALEN];
292 __be16 vlan_id;
293 u16 seid; /* filter control */
294 __be16 dst_port;
295 __be16 src_port;
296 u32 tenant_id;
297 union {
298 struct {
299 struct in_addr dst_ip;
300 struct in_addr src_ip;
301 } v4;
302 struct {
303 struct in6_addr dst_ip6;
304 struct in6_addr src_ip6;
305 } v6;
306 } ip;
307#define dst_ipv6 ip.v6.dst_ip6.s6_addr32
308#define src_ipv6 ip.v6.src_ip6.s6_addr32
309#define dst_ipv4 ip.v4.dst_ip.s_addr
310#define src_ipv4 ip.v4.src_ip.s_addr
311 u16 n_proto; /* Ethernet Protocol */
312 u8 ip_proto; /* IPPROTO value */
313 u8 flags;
314#define I40E_CLOUD_TNL_TYPE_NONE 0xff
315 u8 tunnel_type;
316};
317
318#define I40E_ETH_P_LLDP 0x88cc
319
320#define I40E_DCB_PRIO_TYPE_STRICT 0
321#define I40E_DCB_PRIO_TYPE_ETS 1
322#define I40E_DCB_STRICT_PRIO_CREDITS 127
323/* DCB per TC information data structure */
324struct i40e_tc_info {
325 u16 qoffset; /* Queue offset from base queue */
326 u16 qcount; /* Total Queues */
327 u8 netdev_tc; /* Netdev TC index if netdev associated */
328};
329
330/* TC configuration data structure */
331struct i40e_tc_configuration {
332 u8 numtc; /* Total number of enabled TCs */
333 u8 enabled_tc; /* TC map */
334 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS];
335};
336
337struct i40e_udp_port_config {
338 /* AdminQ command interface expects port number in Host byte order */
339 u16 port;
340 u8 type;
341};
342
343/* macros related to FLX_PIT */
344#define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \
345 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
346 I40E_PRTQF_FLX_PIT_FSIZE_MASK)
347#define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \
348 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
349 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)
350#define I40E_FLEX_SET_SRC_WORD(src) (((src) << \
351 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
352 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK)
353#define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \
354 I40E_FLEX_SET_FSIZE(fsize) | \
355 I40E_FLEX_SET_SRC_WORD(src))
356
357#define I40E_FLEX_PIT_GET_SRC(flex) (((flex) & \
358 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) >> \
359 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT)
360#define I40E_FLEX_PIT_GET_DST(flex) (((flex) & \
361 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) >> \
362 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT)
363#define I40E_FLEX_PIT_GET_FSIZE(flex) (((flex) & \
364 I40E_PRTQF_FLX_PIT_FSIZE_MASK) >> \
365 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT)
366
367#define I40E_MAX_FLEX_SRC_OFFSET 0x1F
368
369/* macros related to GLQF_ORT */
370#define I40E_ORT_SET_IDX(idx) (((idx) << \
371 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \
372 I40E_GLQF_ORT_PIT_INDX_MASK)
373
374#define I40E_ORT_SET_COUNT(count) (((count) << \
375 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \
376 I40E_GLQF_ORT_FIELD_CNT_MASK)
377
378#define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \
379 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \
380 I40E_GLQF_ORT_FLX_PAYLOAD_MASK)
381
382#define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \
383 I40E_ORT_SET_COUNT(count) | \
384 I40E_ORT_SET_PAYLOAD(payload))
385
386#define I40E_L3_GLQF_ORT_IDX 34
387#define I40E_L4_GLQF_ORT_IDX 35
388
389/* Flex PIT register index */
390#define I40E_FLEX_PIT_IDX_START_L2 0
391#define I40E_FLEX_PIT_IDX_START_L3 3
392#define I40E_FLEX_PIT_IDX_START_L4 6
393
394#define I40E_FLEX_PIT_TABLE_SIZE 3
395
396#define I40E_FLEX_DEST_UNUSED 63
397
398#define I40E_FLEX_INDEX_ENTRIES 8
399
400/* Flex MASK to disable all flexible entries */
401#define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \
402 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \
403 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \
404 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK)
405
406struct i40e_flex_pit {
407 struct list_head list;
408 u16 src_offset;
409 u8 pit_index;
410};
411
412struct i40e_channel {
413 struct list_head list;
414 bool initialized;
415 u8 type;
416 u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */
417 u16 stat_counter_idx;
418 u16 base_queue;
419 u16 num_queue_pairs; /* Requested by user */
420 u16 seid;
421
422 u8 enabled_tc;
423 struct i40e_aqc_vsi_properties_data info;
424
425 u64 max_tx_rate;
426
427 /* track this channel belongs to which VSI */
428 struct i40e_vsi *parent_vsi;
429};
430
431/* struct that defines the Ethernet device */
432struct i40e_pf {
433 struct pci_dev *pdev;
434 struct i40e_hw hw;
435 DECLARE_BITMAP(state, __I40E_STATE_SIZE__);
436 struct msix_entry *msix_entries;
437 bool fc_autoneg_status;
438
439 u16 eeprom_version;
440 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */
441 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */
442 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */
443 u16 num_req_vfs; /* num VFs requested for this PF */
444 u16 num_vf_qps; /* num queue pairs per VF */
445 u16 num_lan_qps; /* num lan queues this PF has set up */
446 u16 num_lan_msix; /* num queue vectors for the base PF vsi */
447 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */
448 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */
449 int iwarp_base_vector;
450 int queues_left; /* queues left unclaimed */
451 u16 alloc_rss_size; /* allocated RSS queues */
452 u16 rss_size_max; /* HW defined max RSS queues */
453 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */
454 u16 num_alloc_vsi; /* num VSIs this driver supports */
455 u8 atr_sample_rate;
456 bool wol_en;
457
458 struct hlist_head fdir_filter_list;
459 u16 fdir_pf_active_filters;
460 unsigned long fd_flush_timestamp;
461 u32 fd_flush_cnt;
462 u32 fd_add_err;
463 u32 fd_atr_cnt;
464
465 /* Book-keeping of side-band filter count per flow-type.
466 * This is used to detect and handle input set changes for
467 * respective flow-type.
468 */
469 u16 fd_tcp4_filter_cnt;
470 u16 fd_udp4_filter_cnt;
471 u16 fd_sctp4_filter_cnt;
472 u16 fd_ip4_filter_cnt;
473
474 /* Flexible filter table values that need to be programmed into
475 * hardware, which expects L3 and L4 to be programmed separately. We
476 * need to ensure that the values are in ascended order and don't have
477 * duplicates, so we track each L3 and L4 values in separate lists.
478 */
479 struct list_head l3_flex_pit_list;
480 struct list_head l4_flex_pit_list;
481
482 struct i40e_udp_port_config udp_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
483 u16 pending_udp_bitmap;
484
485 struct hlist_head cloud_filter_list;
486 u16 num_cloud_filters;
487
488 enum i40e_interrupt_policy int_policy;
489 u16 rx_itr_default;
490 u16 tx_itr_default;
491 u32 msg_enable;
492 char int_name[I40E_INT_NAME_STR_LEN];
493 u16 adminq_work_limit; /* num of admin receive queue desc to process */
494 unsigned long service_timer_period;
495 unsigned long service_timer_previous;
496 struct timer_list service_timer;
497 struct work_struct service_task;
498
499 u32 hw_features;
500#define I40E_HW_RSS_AQ_CAPABLE BIT(0)
501#define I40E_HW_128_QP_RSS_CAPABLE BIT(1)
502#define I40E_HW_ATR_EVICT_CAPABLE BIT(2)
503#define I40E_HW_WB_ON_ITR_CAPABLE BIT(3)
504#define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT(4)
505#define I40E_HW_NO_PCI_LINK_CHECK BIT(5)
506#define I40E_HW_100M_SGMII_CAPABLE BIT(6)
507#define I40E_HW_NO_DCB_SUPPORT BIT(7)
508#define I40E_HW_USE_SET_LLDP_MIB BIT(8)
509#define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT(9)
510#define I40E_HW_PTP_L4_CAPABLE BIT(10)
511#define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT(11)
512#define I40E_HW_MPLS_HDR_OFFLOAD_CAPABLE BIT(12)
513#define I40E_HW_HAVE_CRT_RETIMER BIT(13)
514#define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT(14)
515#define I40E_HW_PHY_CONTROLS_LEDS BIT(15)
516#define I40E_HW_STOP_FW_LLDP BIT(16)
517#define I40E_HW_PORT_ID_VALID BIT(17)
518#define I40E_HW_RESTART_AUTONEG BIT(18)
519#define I40E_HW_STOPPABLE_FW_LLDP BIT(19)
520
521 u32 flags;
522#define I40E_FLAG_RX_CSUM_ENABLED BIT(0)
523#define I40E_FLAG_MSI_ENABLED BIT(1)
524#define I40E_FLAG_MSIX_ENABLED BIT(2)
525#define I40E_FLAG_RSS_ENABLED BIT(3)
526#define I40E_FLAG_VMDQ_ENABLED BIT(4)
527#define I40E_FLAG_SRIOV_ENABLED BIT(5)
528#define I40E_FLAG_DCB_CAPABLE BIT(6)
529#define I40E_FLAG_DCB_ENABLED BIT(7)
530#define I40E_FLAG_FD_SB_ENABLED BIT(8)
531#define I40E_FLAG_FD_ATR_ENABLED BIT(9)
532#define I40E_FLAG_MFP_ENABLED BIT(10)
533#define I40E_FLAG_HW_ATR_EVICT_ENABLED BIT(11)
534#define I40E_FLAG_VEB_MODE_ENABLED BIT(12)
535#define I40E_FLAG_VEB_STATS_ENABLED BIT(13)
536#define I40E_FLAG_LINK_POLLING_ENABLED BIT(14)
537#define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT(15)
538#define I40E_FLAG_LEGACY_RX BIT(16)
539#define I40E_FLAG_PTP BIT(17)
540#define I40E_FLAG_IWARP_ENABLED BIT(18)
541#define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED BIT(19)
542#define I40E_FLAG_SOURCE_PRUNING_DISABLED BIT(20)
543#define I40E_FLAG_TC_MQPRIO BIT(21)
544#define I40E_FLAG_FD_SB_INACTIVE BIT(22)
545#define I40E_FLAG_FD_SB_TO_CLOUD_FILTER BIT(23)
546#define I40E_FLAG_DISABLE_FW_LLDP BIT(24)
547
548 struct i40e_client_instance *cinst;
549 bool stat_offsets_loaded;
550 struct i40e_hw_port_stats stats;
551 struct i40e_hw_port_stats stats_offsets;
552 u32 tx_timeout_count;
553 u32 tx_timeout_recovery_level;
554 unsigned long tx_timeout_last_recovery;
555 u32 tx_sluggish_count;
556 u32 hw_csum_rx_error;
557 u32 led_status;
558 u16 corer_count; /* Core reset count */
559 u16 globr_count; /* Global reset count */
560 u16 empr_count; /* EMP reset count */
561 u16 pfr_count; /* PF reset count */
562 u16 sw_int_count; /* SW interrupt count */
563
564 struct mutex switch_mutex;
565 u16 lan_vsi; /* our default LAN VSI */
566 u16 lan_veb; /* initial relay, if exists */
567#define I40E_NO_VEB 0xffff
568#define I40E_NO_VSI 0xffff
569 u16 next_vsi; /* Next unallocated VSI - 0-based! */
570 struct i40e_vsi **vsi;
571 struct i40e_veb *veb[I40E_MAX_VEB];
572
573 struct i40e_lump_tracking *qp_pile;
574 struct i40e_lump_tracking *irq_pile;
575
576 /* switch config info */
577 u16 pf_seid;
578 u16 main_vsi_seid;
579 u16 mac_seid;
580 struct kobject *switch_kobj;
581#ifdef CONFIG_DEBUG_FS
582 struct dentry *i40e_dbg_pf;
583#endif /* CONFIG_DEBUG_FS */
584 bool cur_promisc;
585
586 u16 instance; /* A unique number per i40e_pf instance in the system */
587
588 /* sr-iov config info */
589 struct i40e_vf *vf;
590 int num_alloc_vfs; /* actual number of VFs allocated */
591 u32 vf_aq_requests;
592 u32 arq_overflows; /* Not fatal, possibly indicative of problems */
593
594 /* DCBx/DCBNL capability for PF that indicates
595 * whether DCBx is managed by firmware or host
596 * based agent (LLDPAD). Also, indicates what
597 * flavor of DCBx protocol (IEEE/CEE) is supported
598 * by the device. For now we're supporting IEEE
599 * mode only.
600 */
601 u16 dcbx_cap;
602
603 struct i40e_filter_control_settings filter_settings;
604
605 struct ptp_clock *ptp_clock;
606 struct ptp_clock_info ptp_caps;
607 struct sk_buff *ptp_tx_skb;
608 unsigned long ptp_tx_start;
609 struct hwtstamp_config tstamp_config;
610 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */
611 u64 ptp_base_adj;
612 u32 tx_hwtstamp_timeouts;
613 u32 tx_hwtstamp_skipped;
614 u32 rx_hwtstamp_cleared;
615 u32 latch_event_flags;
616 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */
617 unsigned long latch_events[4];
618 bool ptp_tx;
619 bool ptp_rx;
620 u16 rss_table_size; /* HW RSS table size */
621 u32 max_bw;
622 u32 min_bw;
623
624 u32 ioremap_len;
625 u32 fd_inv;
626 u16 phy_led_val;
627
628 u16 override_q_count;
629 u16 last_sw_conf_flags;
630 u16 last_sw_conf_valid_flags;
631};
632
633/**
634 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key
635 * @macaddr: the MAC Address as the base key
636 *
637 * Simply copies the address and returns it as a u64 for hashing
638 **/
639static inline u64 i40e_addr_to_hkey(const u8 *macaddr)
640{
641 u64 key = 0;
642
643 ether_addr_copy((u8 *)&key, macaddr);
644 return key;
645}
646
647enum i40e_filter_state {
648 I40E_FILTER_INVALID = 0, /* Invalid state */
649 I40E_FILTER_NEW, /* New, not sent to FW yet */
650 I40E_FILTER_ACTIVE, /* Added to switch by FW */
651 I40E_FILTER_FAILED, /* Rejected by FW */
652 I40E_FILTER_REMOVE, /* To be removed */
653/* There is no 'removed' state; the filter struct is freed */
654};
655struct i40e_mac_filter {
656 struct hlist_node hlist;
657 u8 macaddr[ETH_ALEN];
658#define I40E_VLAN_ANY -1
659 s16 vlan;
660 enum i40e_filter_state state;
661};
662
663/* Wrapper structure to keep track of filters while we are preparing to send
664 * firmware commands. We cannot send firmware commands while holding a
665 * spinlock, since it might sleep. To avoid this, we wrap the added filters in
666 * a separate structure, which will track the state change and update the real
667 * filter while under lock. We can't simply hold the filters in a separate
668 * list, as this opens a window for a race condition when adding new MAC
669 * addresses to all VLANs, or when adding new VLANs to all MAC addresses.
670 */
671struct i40e_new_mac_filter {
672 struct hlist_node hlist;
673 struct i40e_mac_filter *f;
674
675 /* Track future changes to state separately */
676 enum i40e_filter_state state;
677};
678
679struct i40e_veb {
680 struct i40e_pf *pf;
681 u16 idx;
682 u16 veb_idx; /* index of VEB parent */
683 u16 seid;
684 u16 uplink_seid;
685 u16 stats_idx; /* index of VEB parent */
686 u8 enabled_tc;
687 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */
688 u16 flags;
689 u16 bw_limit;
690 u8 bw_max_quanta;
691 bool is_abs_credits;
692 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS];
693 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS];
694 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS];
695 struct kobject *kobj;
696 bool stat_offsets_loaded;
697 struct i40e_eth_stats stats;
698 struct i40e_eth_stats stats_offsets;
699 struct i40e_veb_tc_stats tc_stats;
700 struct i40e_veb_tc_stats tc_stats_offsets;
701};
702
703/* struct that defines a VSI, associated with a dev */
704struct i40e_vsi {
705 struct net_device *netdev;
706 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
707 bool netdev_registered;
708 bool stat_offsets_loaded;
709
710 u32 current_netdev_flags;
711 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__);
712#define I40E_VSI_FLAG_FILTER_CHANGED BIT(0)
713#define I40E_VSI_FLAG_VEB_OWNER BIT(1)
714 unsigned long flags;
715
716 /* Per VSI lock to protect elements/hash (MAC filter) */
717 spinlock_t mac_filter_hash_lock;
718 /* Fixed size hash table with 2^8 buckets for MAC filters */
719 DECLARE_HASHTABLE(mac_filter_hash, 8);
720 bool has_vlan_filter;
721
722 /* VSI stats */
723 struct rtnl_link_stats64 net_stats;
724 struct rtnl_link_stats64 net_stats_offsets;
725 struct i40e_eth_stats eth_stats;
726 struct i40e_eth_stats eth_stats_offsets;
727 u32 tx_restart;
728 u32 tx_busy;
729 u64 tx_linearize;
730 u64 tx_force_wb;
731 u32 rx_buf_failed;
732 u32 rx_page_failed;
733
734 /* These are containers of ring pointers, allocated at run-time */
735 struct i40e_ring **rx_rings;
736 struct i40e_ring **tx_rings;
737 struct i40e_ring **xdp_rings; /* XDP Tx rings */
738
739 u32 active_filters;
740 u32 promisc_threshold;
741
742 u16 work_limit;
743 u16 int_rate_limit; /* value in usecs */
744
745 u16 rss_table_size; /* HW RSS table size */
746 u16 rss_size; /* Allocated RSS queues */
747 u8 *rss_hkey_user; /* User configured hash keys */
748 u8 *rss_lut_user; /* User configured lookup table entries */
749
750
751 u16 max_frame;
752 u16 rx_buf_len;
753
754 struct bpf_prog *xdp_prog;
755
756 /* List of q_vectors allocated to this VSI */
757 struct i40e_q_vector **q_vectors;
758 int num_q_vectors;
759 int base_vector;
760 bool irqs_ready;
761
762 u16 seid; /* HW index of this VSI (absolute index) */
763 u16 id; /* VSI number */
764 u16 uplink_seid;
765
766 u16 base_queue; /* vsi's first queue in hw array */
767 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */
768 u16 req_queue_pairs; /* User requested queue pairs */
769 u16 num_queue_pairs; /* Used tx and rx pairs */
770 u16 num_desc;
771 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */
772 s16 vf_id; /* Virtual function ID for SRIOV VSIs */
773
774 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */
775 struct i40e_tc_configuration tc_config;
776 struct i40e_aqc_vsi_properties_data info;
777
778 /* VSI BW limit (absolute across all TCs) */
779 u16 bw_limit; /* VSI BW Limit (0 = disabled) */
780 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */
781
782 /* Relative TC credits across VSIs */
783 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
784 /* TC BW limit credits within VSI */
785 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
786 /* TC BW limit max quanta within VSI */
787 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
788
789 struct i40e_pf *back; /* Backreference to associated PF */
790 u16 idx; /* index in pf->vsi[] */
791 u16 veb_idx; /* index of VEB parent */
792 struct kobject *kobj; /* sysfs object */
793 bool current_isup; /* Sync 'link up' logging */
794 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */
795
796 /* channel specific fields */
797 u16 cnt_q_avail; /* num of queues available for channel usage */
798 u16 orig_rss_size;
799 u16 current_rss_size;
800 bool reconfig_rss;
801
802 u16 next_base_queue; /* next queue to be used for channel setup */
803
804 struct list_head ch_list;
805 u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS];
806
807 void *priv; /* client driver data reference. */
808
809 /* VSI specific handlers */
810 irqreturn_t (*irq_handler)(int irq, void *data);
811} ____cacheline_internodealigned_in_smp;
812
813struct i40e_netdev_priv {
814 struct i40e_vsi *vsi;
815};
816
817/* struct that defines an interrupt vector */
818struct i40e_q_vector {
819 struct i40e_vsi *vsi;
820
821 u16 v_idx; /* index in the vsi->q_vector array. */
822 u16 reg_idx; /* register index of the interrupt */
823
824 struct napi_struct napi;
825
826 struct i40e_ring_container rx;
827 struct i40e_ring_container tx;
828
829 u8 itr_countdown; /* when 0 should adjust adaptive ITR */
830 u8 num_ringpairs; /* total number of ring pairs in vector */
831
832 cpumask_t affinity_mask;
833 struct irq_affinity_notify affinity_notify;
834
835 struct rcu_head rcu; /* to avoid race with update stats on free */
836 char name[I40E_INT_NAME_STR_LEN];
837 bool arm_wb_state;
838} ____cacheline_internodealigned_in_smp;
839
840/* lan device */
841struct i40e_device {
842 struct list_head list;
843 struct i40e_pf *pf;
844};
845
846/**
847 * i40e_nvm_version_str - format the NVM version strings
848 * @hw: ptr to the hardware info
849 **/
850static inline char *i40e_nvm_version_str(struct i40e_hw *hw)
851{
852 static char buf[32];
853 u32 full_ver;
854
855 full_ver = hw->nvm.oem_ver;
856
857 if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) {
858 u8 gen, snap;
859 u16 release;
860
861 gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT);
862 snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >>
863 I40E_OEM_SNAP_SHIFT);
864 release = (u16)(full_ver & I40E_OEM_RELEASE_MASK);
865
866 snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release);
867 } else {
868 u8 ver, patch;
869 u16 build;
870
871 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT);
872 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) &
873 I40E_OEM_VER_BUILD_MASK);
874 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK);
875
876 snprintf(buf, sizeof(buf),
877 "%x.%02x 0x%x %d.%d.%d",
878 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >>
879 I40E_NVM_VERSION_HI_SHIFT,
880 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >>
881 I40E_NVM_VERSION_LO_SHIFT,
882 hw->nvm.eetrack, ver, build, patch);
883 }
884
885 return buf;
886}
887
888/**
889 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev
890 * @netdev: the corresponding netdev
891 *
892 * Return the PF struct for the given netdev
893 **/
894static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev)
895{
896 struct i40e_netdev_priv *np = netdev_priv(netdev);
897 struct i40e_vsi *vsi = np->vsi;
898
899 return vsi->back;
900}
901
902static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi,
903 irqreturn_t (*irq_handler)(int, void *))
904{
905 vsi->irq_handler = irq_handler;
906}
907
908/**
909 * i40e_get_fd_cnt_all - get the total FD filter space available
910 * @pf: pointer to the PF struct
911 **/
912static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf)
913{
914 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count;
915}
916
917/**
918 * i40e_read_fd_input_set - reads value of flow director input set register
919 * @pf: pointer to the PF struct
920 * @addr: register addr
921 *
922 * This function reads value of flow director input set register
923 * specified by 'addr' (which is specific to flow-type)
924 **/
925static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr)
926{
927 u64 val;
928
929 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1));
930 val <<= 32;
931 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0));
932
933 return val;
934}
935
936/**
937 * i40e_write_fd_input_set - writes value into flow director input set register
938 * @pf: pointer to the PF struct
939 * @addr: register addr
940 * @val: value to be written
941 *
942 * This function writes specified value to the register specified by 'addr'.
943 * This register is input set register based on flow-type.
944 **/
945static inline void i40e_write_fd_input_set(struct i40e_pf *pf,
946 u16 addr, u64 val)
947{
948 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1),
949 (u32)(val >> 32));
950 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0),
951 (u32)(val & 0xFFFFFFFFULL));
952}
953
954/* needed by i40e_ethtool.c */
955int i40e_up(struct i40e_vsi *vsi);
956void i40e_down(struct i40e_vsi *vsi);
957extern const char i40e_driver_name[];
958extern const char i40e_driver_version_str[];
959void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags);
960void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired);
961int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
962int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
963void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
964 u16 rss_table_size, u16 rss_size);
965struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id);
966/**
967 * i40e_find_vsi_by_type - Find and return Flow Director VSI
968 * @pf: PF to search for VSI
969 * @type: Value indicating type of VSI we are looking for
970 **/
971static inline struct i40e_vsi *
972i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type)
973{
974 int i;
975
976 for (i = 0; i < pf->num_alloc_vsi; i++) {
977 struct i40e_vsi *vsi = pf->vsi[i];
978
979 if (vsi && vsi->type == type)
980 return vsi;
981 }
982
983 return NULL;
984}
985void i40e_update_stats(struct i40e_vsi *vsi);
986void i40e_update_eth_stats(struct i40e_vsi *vsi);
987struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi);
988int i40e_fetch_switch_configuration(struct i40e_pf *pf,
989 bool printconfig);
990
991int i40e_add_del_fdir(struct i40e_vsi *vsi,
992 struct i40e_fdir_filter *input, bool add);
993void i40e_fdir_check_and_reenable(struct i40e_pf *pf);
994u32 i40e_get_current_fd_count(struct i40e_pf *pf);
995u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf);
996u32 i40e_get_current_atr_cnt(struct i40e_pf *pf);
997u32 i40e_get_global_fd_count(struct i40e_pf *pf);
998bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features);
999void i40e_set_ethtool_ops(struct net_device *netdev);
1000struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1001 const u8 *macaddr, s16 vlan);
1002void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f);
1003void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan);
1004int i40e_sync_vsi_filters(struct i40e_vsi *vsi);
1005struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
1006 u16 uplink, u32 param1);
1007int i40e_vsi_release(struct i40e_vsi *vsi);
1008void i40e_service_event_schedule(struct i40e_pf *pf);
1009void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id,
1010 u8 *msg, u16 len);
1011
1012int i40e_vsi_start_rings(struct i40e_vsi *vsi);
1013void i40e_vsi_stop_rings(struct i40e_vsi *vsi);
1014void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi);
1015int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi);
1016int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count);
1017struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid,
1018 u16 downlink_seid, u8 enabled_tc);
1019void i40e_veb_release(struct i40e_veb *veb);
1020
1021int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc);
1022int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid);
1023void i40e_vsi_remove_pvid(struct i40e_vsi *vsi);
1024void i40e_vsi_reset_stats(struct i40e_vsi *vsi);
1025void i40e_pf_reset_stats(struct i40e_pf *pf);
1026#ifdef CONFIG_DEBUG_FS
1027void i40e_dbg_pf_init(struct i40e_pf *pf);
1028void i40e_dbg_pf_exit(struct i40e_pf *pf);
1029void i40e_dbg_init(void);
1030void i40e_dbg_exit(void);
1031#else
1032static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {}
1033static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {}
1034static inline void i40e_dbg_init(void) {}
1035static inline void i40e_dbg_exit(void) {}
1036#endif /* CONFIG_DEBUG_FS*/
1037/* needed by client drivers */
1038int i40e_lan_add_device(struct i40e_pf *pf);
1039int i40e_lan_del_device(struct i40e_pf *pf);
1040void i40e_client_subtask(struct i40e_pf *pf);
1041void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi);
1042void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset);
1043void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs);
1044void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id);
1045void i40e_client_update_msix_info(struct i40e_pf *pf);
1046int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id);
1047/**
1048 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
1049 * @vsi: pointer to a vsi
1050 * @vector: enable a particular Hw Interrupt vector, without base_vector
1051 **/
1052static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
1053{
1054 struct i40e_pf *pf = vsi->back;
1055 struct i40e_hw *hw = &pf->hw;
1056 u32 val;
1057
1058 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1059 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1060 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
1061 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val);
1062 /* skip the flush */
1063}
1064
1065void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
1066void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf);
1067int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
1068int i40e_open(struct net_device *netdev);
1069int i40e_close(struct net_device *netdev);
1070int i40e_vsi_open(struct i40e_vsi *vsi);
1071void i40e_vlan_stripping_disable(struct i40e_vsi *vsi);
1072int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1073int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid);
1074void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1075void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid);
1076struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi,
1077 const u8 *macaddr);
1078int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr);
1079bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi);
1080struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr);
1081void i40e_vlan_stripping_enable(struct i40e_vsi *vsi);
1082#ifdef CONFIG_I40E_DCB
1083void i40e_dcbnl_flush_apps(struct i40e_pf *pf,
1084 struct i40e_dcbx_config *old_cfg,
1085 struct i40e_dcbx_config *new_cfg);
1086void i40e_dcbnl_set_all(struct i40e_vsi *vsi);
1087void i40e_dcbnl_setup(struct i40e_vsi *vsi);
1088bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
1089 struct i40e_dcbx_config *old_cfg,
1090 struct i40e_dcbx_config *new_cfg);
1091#endif /* CONFIG_I40E_DCB */
1092void i40e_ptp_rx_hang(struct i40e_pf *pf);
1093void i40e_ptp_tx_hang(struct i40e_pf *pf);
1094void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf);
1095void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index);
1096void i40e_ptp_set_increment(struct i40e_pf *pf);
1097int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1098int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1099void i40e_ptp_init(struct i40e_pf *pf);
1100void i40e_ptp_stop(struct i40e_pf *pf);
1101int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi);
1102i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf);
1103i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf);
1104i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf);
1105void i40e_print_link_message(struct i40e_vsi *vsi, bool isup);
1106
1107static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi)
1108{
1109 return !!vsi->xdp_prog;
1110}
1111
1112int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch);
1113int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate);
1114int i40e_add_del_cloud_filter(struct i40e_vsi *vsi,
1115 struct i40e_cloud_filter *filter,
1116 bool add);
1117int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi,
1118 struct i40e_cloud_filter *filter,
1119 bool add);
1120#endif /* _I40E_H_ */