1/* SPDX-License-Identifier: GPL-2.0 */
  2#ifndef __SDHCI_PCI_H
  3#define __SDHCI_PCI_H
  4
  5/*
  6 * PCI device IDs, sub IDs
  7 */
  8
  9#define PCI_DEVICE_ID_O2_SDS0		0x8420
 10#define PCI_DEVICE_ID_O2_SDS1		0x8421
 11#define PCI_DEVICE_ID_O2_FUJIN2		0x8520
 12#define PCI_DEVICE_ID_O2_SEABIRD0	0x8620
 13#define PCI_DEVICE_ID_O2_SEABIRD1	0x8621
 14
 15#define PCI_DEVICE_ID_INTEL_PCH_SDIO0	0x8809
 16#define PCI_DEVICE_ID_INTEL_PCH_SDIO1	0x880a
 17#define PCI_DEVICE_ID_INTEL_BYT_EMMC	0x0f14
 18#define PCI_DEVICE_ID_INTEL_BYT_SDIO	0x0f15
 19#define PCI_DEVICE_ID_INTEL_BYT_SD	0x0f16
 20#define PCI_DEVICE_ID_INTEL_BYT_EMMC2	0x0f50
 21#define PCI_DEVICE_ID_INTEL_BSW_EMMC	0x2294
 22#define PCI_DEVICE_ID_INTEL_BSW_SDIO	0x2295
 23#define PCI_DEVICE_ID_INTEL_BSW_SD	0x2296
 24#define PCI_DEVICE_ID_INTEL_MRFLD_MMC	0x1190
 25#define PCI_DEVICE_ID_INTEL_CLV_SDIO0	0x08f9
 26#define PCI_DEVICE_ID_INTEL_CLV_SDIO1	0x08fa
 27#define PCI_DEVICE_ID_INTEL_CLV_SDIO2	0x08fb
 28#define PCI_DEVICE_ID_INTEL_CLV_EMMC0	0x08e5
 29#define PCI_DEVICE_ID_INTEL_CLV_EMMC1	0x08e6
 30#define PCI_DEVICE_ID_INTEL_QRK_SD	0x08A7
 31#define PCI_DEVICE_ID_INTEL_SPT_EMMC	0x9d2b
 32#define PCI_DEVICE_ID_INTEL_SPT_SDIO	0x9d2c
 33#define PCI_DEVICE_ID_INTEL_SPT_SD	0x9d2d
 34#define PCI_DEVICE_ID_INTEL_DNV_EMMC	0x19db
 35#define PCI_DEVICE_ID_INTEL_CDF_EMMC	0x18db
 36#define PCI_DEVICE_ID_INTEL_BXT_SD	0x0aca
 37#define PCI_DEVICE_ID_INTEL_BXT_EMMC	0x0acc
 38#define PCI_DEVICE_ID_INTEL_BXT_SDIO	0x0ad0
 39#define PCI_DEVICE_ID_INTEL_BXTM_SD	0x1aca
 40#define PCI_DEVICE_ID_INTEL_BXTM_EMMC	0x1acc
 41#define PCI_DEVICE_ID_INTEL_BXTM_SDIO	0x1ad0
 42#define PCI_DEVICE_ID_INTEL_APL_SD	0x5aca
 43#define PCI_DEVICE_ID_INTEL_APL_EMMC	0x5acc
 44#define PCI_DEVICE_ID_INTEL_APL_SDIO	0x5ad0
 45#define PCI_DEVICE_ID_INTEL_GLK_SD	0x31ca
 46#define PCI_DEVICE_ID_INTEL_GLK_EMMC	0x31cc
 47#define PCI_DEVICE_ID_INTEL_GLK_SDIO	0x31d0
 48#define PCI_DEVICE_ID_INTEL_CNP_EMMC	0x9dc4
 49#define PCI_DEVICE_ID_INTEL_CNP_SD	0x9df5
 50#define PCI_DEVICE_ID_INTEL_CNPH_SD	0xa375
 51
 52#define PCI_DEVICE_ID_SYSKONNECT_8000	0x8000
 53#define PCI_DEVICE_ID_VIA_95D0		0x95d0
 54#define PCI_DEVICE_ID_REALTEK_5250	0x5250
 55
 56#define PCI_SUBDEVICE_ID_NI_7884	0x7884
 57
 58#define PCI_VENDOR_ID_ARASAN		0x16e6
 59#define PCI_DEVICE_ID_ARASAN_PHY_EMMC	0x0670
 60
 61/*
 62 * PCI device class and mask
 63 */
 64
 65#define SYSTEM_SDHCI			(PCI_CLASS_SYSTEM_SDHCI << 8)
 66#define PCI_CLASS_MASK			0xFFFF00
 67
 68/*
 69 * Macros for PCI device-description
 70 */
 71
 72#define _PCI_VEND(vend) PCI_VENDOR_ID_##vend
 73#define _PCI_DEV(vend, dev) PCI_DEVICE_ID_##vend##_##dev
 74#define _PCI_SUBDEV(subvend, subdev) PCI_SUBDEVICE_ID_##subvend##_##subdev
 75
 76#define SDHCI_PCI_DEVICE(vend, dev, cfg) { \
 77	.vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \
 78	.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
 79	.driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
 80}
 81
 82#define SDHCI_PCI_SUBDEVICE(vend, dev, subvend, subdev, cfg) { \
 83	.vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \
 84	.subvendor = _PCI_VEND(subvend), \
 85	.subdevice = _PCI_SUBDEV(subvend, subdev), \
 86	.driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
 87}
 88
 89#define SDHCI_PCI_DEVICE_CLASS(vend, cl, cl_msk, cfg) { \
 90	.vendor = _PCI_VEND(vend), .device = PCI_ANY_ID, \
 91	.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
 92	.class = (cl), .class_mask = (cl_msk), \
 93	.driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
 94}
 95
 96/*
 97 * PCI registers
 98 */
 99
100#define PCI_SDHCI_IFPIO			0x00
101#define PCI_SDHCI_IFDMA			0x01
102#define PCI_SDHCI_IFVENDOR		0x02
103
104#define PCI_SLOT_INFO			0x40	/* 8 bits */
105#define  PCI_SLOT_INFO_SLOTS(x)		((x >> 4) & 7)
106#define  PCI_SLOT_INFO_FIRST_BAR_MASK	0x07
107
108#define MAX_SLOTS			8
109
110struct sdhci_pci_chip;
111struct sdhci_pci_slot;
112
113struct sdhci_pci_fixes {
114	unsigned int		quirks;
115	unsigned int		quirks2;
116	bool			allow_runtime_pm;
117	bool			own_cd_for_runtime_pm;
118
119	int			(*probe) (struct sdhci_pci_chip *);
120
121	int			(*probe_slot) (struct sdhci_pci_slot *);
122	int			(*add_host) (struct sdhci_pci_slot *);
123	void			(*remove_slot) (struct sdhci_pci_slot *, int);
124
125#ifdef CONFIG_PM_SLEEP
126	int			(*suspend) (struct sdhci_pci_chip *);
127	int			(*resume) (struct sdhci_pci_chip *);
128#endif
129#ifdef CONFIG_PM
130	int			(*runtime_suspend) (struct sdhci_pci_chip *);
131	int			(*runtime_resume) (struct sdhci_pci_chip *);
132#endif
133
134	const struct sdhci_ops	*ops;
135	size_t			priv_size;
136};
137
138struct sdhci_pci_slot {
139	struct sdhci_pci_chip	*chip;
140	struct sdhci_host	*host;
141	struct sdhci_pci_data	*data;
142
143	int			rst_n_gpio;
144	int			cd_gpio;
145	int			cd_irq;
146
147	int			cd_idx;
148	bool			cd_override_level;
149
150	void (*hw_reset)(struct sdhci_host *host);
151	unsigned long		private[0] ____cacheline_aligned;
152};
153
154struct sdhci_pci_chip {
155	struct pci_dev		*pdev;
156
157	unsigned int		quirks;
158	unsigned int		quirks2;
159	bool			allow_runtime_pm;
160	bool			pm_retune;
161	bool			rpm_retune;
162	const struct sdhci_pci_fixes *fixes;
163
164	int			num_slots;	/* Slots on controller */
165	struct sdhci_pci_slot	*slots[MAX_SLOTS]; /* Pointers to host slots */
166};
167
168static inline void *sdhci_pci_priv(struct sdhci_pci_slot *slot)
169{
170	return (void *)slot->private;
171}
172
173#ifdef CONFIG_PM_SLEEP
174int sdhci_pci_resume_host(struct sdhci_pci_chip *chip);
175#endif
176int sdhci_pci_enable_dma(struct sdhci_host *host);
177int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot);
178int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip);
179#ifdef CONFIG_PM_SLEEP
180int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip);
181#endif
182
183extern const struct sdhci_pci_fixes sdhci_arasan;
184
185#endif /* __SDHCI_PCI_H */