1/*
   2 * Copyright 2015 Linaro Limited
   3 *
   4 * This software is licensed under the terms of the GNU General Public
   5 * License version 2, as published by the Free Software Foundation, and
   6 * may be copied, distributed, and modified under those terms.
   7 *
   8 * This program is distributed in the hope that it will be useful,
   9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 * GNU General Public License for more details.
  12 */
  13
  14#include <linux/kernel.h>
  15#include <linux/bitops.h>
  16#include <linux/err.h>
  17#include <linux/platform_device.h>
  18#include <linux/module.h>
  19#include <linux/of.h>
  20#include <linux/of_device.h>
  21#include <linux/clk-provider.h>
  22#include <linux/regmap.h>
  23#include <linux/reset-controller.h>
  24
  25#include <dt-bindings/clock/qcom,gcc-msm8916.h>
  26#include <dt-bindings/reset/qcom,gcc-msm8916.h>
  27
  28#include "common.h"
  29#include "clk-regmap.h"
  30#include "clk-pll.h"
  31#include "clk-rcg.h"
  32#include "clk-branch.h"
  33#include "reset.h"
  34#include "gdsc.h"
  35
  36enum {
  37	P_XO,
  38	P_GPLL0,
  39	P_GPLL0_AUX,
  40	P_BIMC,
  41	P_GPLL1,
  42	P_GPLL1_AUX,
  43	P_GPLL2,
  44	P_GPLL2_AUX,
  45	P_SLEEP_CLK,
  46	P_DSI0_PHYPLL_BYTE,
  47	P_DSI0_PHYPLL_DSI,
  48	P_EXT_PRI_I2S,
  49	P_EXT_SEC_I2S,
  50	P_EXT_MCLK,
  51};
  52
  53static const struct parent_map gcc_xo_gpll0_map[] = {
  54	{ P_XO, 0 },
  55	{ P_GPLL0, 1 },
  56};
  57
  58static const char * const gcc_xo_gpll0[] = {
  59	"xo",
  60	"gpll0_vote",
  61};
  62
  63static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
  64	{ P_XO, 0 },
  65	{ P_GPLL0, 1 },
  66	{ P_BIMC, 2 },
  67};
  68
  69static const char * const gcc_xo_gpll0_bimc[] = {
  70	"xo",
  71	"gpll0_vote",
  72	"bimc_pll_vote",
  73};
  74
  75static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map[] = {
  76	{ P_XO, 0 },
  77	{ P_GPLL0_AUX, 3 },
  78	{ P_GPLL1, 1 },
  79	{ P_GPLL2_AUX, 2 },
  80};
  81
  82static const char * const gcc_xo_gpll0a_gpll1_gpll2a[] = {
  83	"xo",
  84	"gpll0_vote",
  85	"gpll1_vote",
  86	"gpll2_vote",
  87};
  88
  89static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
  90	{ P_XO, 0 },
  91	{ P_GPLL0, 1 },
  92	{ P_GPLL2, 2 },
  93};
  94
  95static const char * const gcc_xo_gpll0_gpll2[] = {
  96	"xo",
  97	"gpll0_vote",
  98	"gpll2_vote",
  99};
 100
 101static const struct parent_map gcc_xo_gpll0a_map[] = {
 102	{ P_XO, 0 },
 103	{ P_GPLL0_AUX, 2 },
 104};
 105
 106static const char * const gcc_xo_gpll0a[] = {
 107	"xo",
 108	"gpll0_vote",
 109};
 110
 111static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = {
 112	{ P_XO, 0 },
 113	{ P_GPLL0, 1 },
 114	{ P_GPLL1_AUX, 2 },
 115	{ P_SLEEP_CLK, 6 },
 116};
 117
 118static const char * const gcc_xo_gpll0_gpll1a_sleep[] = {
 119	"xo",
 120	"gpll0_vote",
 121	"gpll1_vote",
 122	"sleep_clk",
 123};
 124
 125static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = {
 126	{ P_XO, 0 },
 127	{ P_GPLL0, 1 },
 128	{ P_GPLL1_AUX, 2 },
 129};
 130
 131static const char * const gcc_xo_gpll0_gpll1a[] = {
 132	"xo",
 133	"gpll0_vote",
 134	"gpll1_vote",
 135};
 136
 137static const struct parent_map gcc_xo_dsibyte_map[] = {
 138	{ P_XO, 0, },
 139	{ P_DSI0_PHYPLL_BYTE, 2 },
 140};
 141
 142static const char * const gcc_xo_dsibyte[] = {
 143	"xo",
 144	"dsi0pllbyte",
 145};
 146
 147static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = {
 148	{ P_XO, 0 },
 149	{ P_GPLL0_AUX, 2 },
 150	{ P_DSI0_PHYPLL_BYTE, 1 },
 151};
 152
 153static const char * const gcc_xo_gpll0a_dsibyte[] = {
 154	"xo",
 155	"gpll0_vote",
 156	"dsi0pllbyte",
 157};
 158
 159static const struct parent_map gcc_xo_gpll0_dsiphy_map[] = {
 160	{ P_XO, 0 },
 161	{ P_GPLL0, 1 },
 162	{ P_DSI0_PHYPLL_DSI, 2 },
 163};
 164
 165static const char * const gcc_xo_gpll0_dsiphy[] = {
 166	"xo",
 167	"gpll0_vote",
 168	"dsi0pll",
 169};
 170
 171static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = {
 172	{ P_XO, 0 },
 173	{ P_GPLL0_AUX, 2 },
 174	{ P_DSI0_PHYPLL_DSI, 1 },
 175};
 176
 177static const char * const gcc_xo_gpll0a_dsiphy[] = {
 178	"xo",
 179	"gpll0_vote",
 180	"dsi0pll",
 181};
 182
 183static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2_map[] = {
 184	{ P_XO, 0 },
 185	{ P_GPLL0_AUX, 1 },
 186	{ P_GPLL1, 3 },
 187	{ P_GPLL2, 2 },
 188};
 189
 190static const char * const gcc_xo_gpll0a_gpll1_gpll2[] = {
 191	"xo",
 192	"gpll0_vote",
 193	"gpll1_vote",
 194	"gpll2_vote",
 195};
 196
 197static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = {
 198	{ P_XO, 0 },
 199	{ P_GPLL0, 1 },
 200	{ P_GPLL1, 2 },
 201	{ P_SLEEP_CLK, 6 }
 202};
 203
 204static const char * const gcc_xo_gpll0_gpll1_sleep[] = {
 205	"xo",
 206	"gpll0_vote",
 207	"gpll1_vote",
 208	"sleep_clk",
 209};
 210
 211static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = {
 212	{ P_XO, 0 },
 213	{ P_GPLL1, 1 },
 214	{ P_EXT_PRI_I2S, 2 },
 215	{ P_EXT_MCLK, 3 },
 216	{ P_SLEEP_CLK, 6 }
 217};
 218
 219static const char * const gcc_xo_gpll1_epi2s_emclk_sleep[] = {
 220	"xo",
 221	"gpll1_vote",
 222	"ext_pri_i2s",
 223	"ext_mclk",
 224	"sleep_clk",
 225};
 226
 227static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = {
 228	{ P_XO, 0 },
 229	{ P_GPLL1, 1 },
 230	{ P_EXT_SEC_I2S, 2 },
 231	{ P_EXT_MCLK, 3 },
 232	{ P_SLEEP_CLK, 6 }
 233};
 234
 235static const char * const gcc_xo_gpll1_esi2s_emclk_sleep[] = {
 236	"xo",
 237	"gpll1_vote",
 238	"ext_sec_i2s",
 239	"ext_mclk",
 240	"sleep_clk",
 241};
 242
 243static const struct parent_map gcc_xo_sleep_map[] = {
 244	{ P_XO, 0 },
 245	{ P_SLEEP_CLK, 6 }
 246};
 247
 248static const char * const gcc_xo_sleep[] = {
 249	"xo",
 250	"sleep_clk",
 251};
 252
 253static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = {
 254	{ P_XO, 0 },
 255	{ P_GPLL1, 1 },
 256	{ P_EXT_MCLK, 2 },
 257	{ P_SLEEP_CLK, 6 }
 258};
 259
 260static const char * const gcc_xo_gpll1_emclk_sleep[] = {
 261	"xo",
 262	"gpll1_vote",
 263	"ext_mclk",
 264	"sleep_clk",
 265};
 266
 267#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
 268
 269static struct clk_pll gpll0 = {
 270	.l_reg = 0x21004,
 271	.m_reg = 0x21008,
 272	.n_reg = 0x2100c,
 273	.config_reg = 0x21014,
 274	.mode_reg = 0x21000,
 275	.status_reg = 0x2101c,
 276	.status_bit = 17,
 277	.clkr.hw.init = &(struct clk_init_data){
 278		.name = "gpll0",
 279		.parent_names = (const char *[]){ "xo" },
 280		.num_parents = 1,
 281		.ops = &clk_pll_ops,
 282	},
 283};
 284
 285static struct clk_regmap gpll0_vote = {
 286	.enable_reg = 0x45000,
 287	.enable_mask = BIT(0),
 288	.hw.init = &(struct clk_init_data){
 289		.name = "gpll0_vote",
 290		.parent_names = (const char *[]){ "gpll0" },
 291		.num_parents = 1,
 292		.ops = &clk_pll_vote_ops,
 293	},
 294};
 295
 296static struct clk_pll gpll1 = {
 297	.l_reg = 0x20004,
 298	.m_reg = 0x20008,
 299	.n_reg = 0x2000c,
 300	.config_reg = 0x20014,
 301	.mode_reg = 0x20000,
 302	.status_reg = 0x2001c,
 303	.status_bit = 17,
 304	.clkr.hw.init = &(struct clk_init_data){
 305		.name = "gpll1",
 306		.parent_names = (const char *[]){ "xo" },
 307		.num_parents = 1,
 308		.ops = &clk_pll_ops,
 309	},
 310};
 311
 312static struct clk_regmap gpll1_vote = {
 313	.enable_reg = 0x45000,
 314	.enable_mask = BIT(1),
 315	.hw.init = &(struct clk_init_data){
 316		.name = "gpll1_vote",
 317		.parent_names = (const char *[]){ "gpll1" },
 318		.num_parents = 1,
 319		.ops = &clk_pll_vote_ops,
 320	},
 321};
 322
 323static struct clk_pll gpll2 = {
 324	.l_reg = 0x4a004,
 325	.m_reg = 0x4a008,
 326	.n_reg = 0x4a00c,
 327	.config_reg = 0x4a014,
 328	.mode_reg = 0x4a000,
 329	.status_reg = 0x4a01c,
 330	.status_bit = 17,
 331	.clkr.hw.init = &(struct clk_init_data){
 332		.name = "gpll2",
 333		.parent_names = (const char *[]){ "xo" },
 334		.num_parents = 1,
 335		.ops = &clk_pll_ops,
 336	},
 337};
 338
 339static struct clk_regmap gpll2_vote = {
 340	.enable_reg = 0x45000,
 341	.enable_mask = BIT(2),
 342	.hw.init = &(struct clk_init_data){
 343		.name = "gpll2_vote",
 344		.parent_names = (const char *[]){ "gpll2" },
 345		.num_parents = 1,
 346		.ops = &clk_pll_vote_ops,
 347	},
 348};
 349
 350static struct clk_pll bimc_pll = {
 351	.l_reg = 0x23004,
 352	.m_reg = 0x23008,
 353	.n_reg = 0x2300c,
 354	.config_reg = 0x23014,
 355	.mode_reg = 0x23000,
 356	.status_reg = 0x2301c,
 357	.status_bit = 17,
 358	.clkr.hw.init = &(struct clk_init_data){
 359		.name = "bimc_pll",
 360		.parent_names = (const char *[]){ "xo" },
 361		.num_parents = 1,
 362		.ops = &clk_pll_ops,
 363	},
 364};
 365
 366static struct clk_regmap bimc_pll_vote = {
 367	.enable_reg = 0x45000,
 368	.enable_mask = BIT(3),
 369	.hw.init = &(struct clk_init_data){
 370		.name = "bimc_pll_vote",
 371		.parent_names = (const char *[]){ "bimc_pll" },
 372		.num_parents = 1,
 373		.ops = &clk_pll_vote_ops,
 374	},
 375};
 376
 377static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
 378	.cmd_rcgr = 0x27000,
 379	.hid_width = 5,
 380	.parent_map = gcc_xo_gpll0_bimc_map,
 381	.clkr.hw.init = &(struct clk_init_data){
 382		.name = "pcnoc_bfdcd_clk_src",
 383		.parent_names = gcc_xo_gpll0_bimc,
 384		.num_parents = 3,
 385		.ops = &clk_rcg2_ops,
 386	},
 387};
 388
 389static struct clk_rcg2 system_noc_bfdcd_clk_src = {
 390	.cmd_rcgr = 0x26004,
 391	.hid_width = 5,
 392	.parent_map = gcc_xo_gpll0_bimc_map,
 393	.clkr.hw.init = &(struct clk_init_data){
 394		.name = "system_noc_bfdcd_clk_src",
 395		.parent_names = gcc_xo_gpll0_bimc,
 396		.num_parents = 3,
 397		.ops = &clk_rcg2_ops,
 398	},
 399};
 400
 401static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = {
 402	F(40000000, P_GPLL0, 10, 1, 2),
 403	F(80000000, P_GPLL0, 10, 0, 0),
 404	{ }
 405};
 406
 407static struct clk_rcg2 camss_ahb_clk_src = {
 408	.cmd_rcgr = 0x5a000,
 409	.mnd_width = 8,
 410	.hid_width = 5,
 411	.parent_map = gcc_xo_gpll0_map,
 412	.freq_tbl = ftbl_gcc_camss_ahb_clk,
 413	.clkr.hw.init = &(struct clk_init_data){
 414		.name = "camss_ahb_clk_src",
 415		.parent_names = gcc_xo_gpll0,
 416		.num_parents = 2,
 417		.ops = &clk_rcg2_ops,
 418	},
 419};
 420
 421static const struct freq_tbl ftbl_apss_ahb_clk[] = {
 422	F(19200000, P_XO, 1, 0, 0),
 423	F(50000000, P_GPLL0, 16, 0, 0),
 424	F(100000000, P_GPLL0, 8, 0, 0),
 425	F(133330000, P_GPLL0, 6, 0, 0),
 426	{ }
 427};
 428
 429static struct clk_rcg2 apss_ahb_clk_src = {
 430	.cmd_rcgr = 0x46000,
 431	.hid_width = 5,
 432	.parent_map = gcc_xo_gpll0_map,
 433	.freq_tbl = ftbl_apss_ahb_clk,
 434	.clkr.hw.init = &(struct clk_init_data){
 435		.name = "apss_ahb_clk_src",
 436		.parent_names = gcc_xo_gpll0,
 437		.num_parents = 2,
 438		.ops = &clk_rcg2_ops,
 439	},
 440};
 441
 442static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = {
 443	F(100000000, P_GPLL0, 8, 0,	0),
 444	F(200000000, P_GPLL0, 4, 0,	0),
 445	{ }
 446};
 447
 448static struct clk_rcg2 csi0_clk_src = {
 449	.cmd_rcgr = 0x4e020,
 450	.hid_width = 5,
 451	.parent_map = gcc_xo_gpll0_map,
 452	.freq_tbl = ftbl_gcc_camss_csi0_1_clk,
 453	.clkr.hw.init = &(struct clk_init_data){
 454		.name = "csi0_clk_src",
 455		.parent_names = gcc_xo_gpll0,
 456		.num_parents = 2,
 457		.ops = &clk_rcg2_ops,
 458	},
 459};
 460
 461static struct clk_rcg2 csi1_clk_src = {
 462	.cmd_rcgr = 0x4f020,
 463	.hid_width = 5,
 464	.parent_map = gcc_xo_gpll0_map,
 465	.freq_tbl = ftbl_gcc_camss_csi0_1_clk,
 466	.clkr.hw.init = &(struct clk_init_data){
 467		.name = "csi1_clk_src",
 468		.parent_names = gcc_xo_gpll0,
 469		.num_parents = 2,
 470		.ops = &clk_rcg2_ops,
 471	},
 472};
 473
 474static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
 475	F(19200000, P_XO, 1, 0, 0),
 476	F(50000000, P_GPLL0_AUX, 16, 0, 0),
 477	F(80000000, P_GPLL0_AUX, 10, 0, 0),
 478	F(100000000, P_GPLL0_AUX, 8, 0, 0),
 479	F(160000000, P_GPLL0_AUX, 5, 0, 0),
 480	F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
 481	F(200000000, P_GPLL0_AUX, 4, 0, 0),
 482	F(266670000, P_GPLL0_AUX, 3, 0, 0),
 483	F(294912000, P_GPLL1, 3, 0, 0),
 484	F(310000000, P_GPLL2, 3, 0, 0),
 485	F(400000000, P_GPLL0_AUX, 2, 0, 0),
 486	{ }
 487};
 488
 489static struct clk_rcg2 gfx3d_clk_src = {
 490	.cmd_rcgr = 0x59000,
 491	.hid_width = 5,
 492	.parent_map = gcc_xo_gpll0a_gpll1_gpll2a_map,
 493	.freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
 494	.clkr.hw.init = &(struct clk_init_data){
 495		.name = "gfx3d_clk_src",
 496		.parent_names = gcc_xo_gpll0a_gpll1_gpll2a,
 497		.num_parents = 4,
 498		.ops = &clk_rcg2_ops,
 499	},
 500};
 501
 502static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = {
 503	F(50000000, P_GPLL0, 16, 0, 0),
 504	F(80000000, P_GPLL0, 10, 0, 0),
 505	F(100000000, P_GPLL0, 8, 0, 0),
 506	F(160000000, P_GPLL0, 5, 0, 0),
 507	F(177780000, P_GPLL0, 4.5, 0, 0),
 508	F(200000000, P_GPLL0, 4, 0, 0),
 509	F(266670000, P_GPLL0, 3, 0, 0),
 510	F(320000000, P_GPLL0, 2.5, 0, 0),
 511	F(400000000, P_GPLL0, 2, 0, 0),
 512	F(465000000, P_GPLL2, 2, 0, 0),
 513	{ }
 514};
 515
 516static struct clk_rcg2 vfe0_clk_src = {
 517	.cmd_rcgr = 0x58000,
 518	.hid_width = 5,
 519	.parent_map = gcc_xo_gpll0_gpll2_map,
 520	.freq_tbl = ftbl_gcc_camss_vfe0_clk,
 521	.clkr.hw.init = &(struct clk_init_data){
 522		.name = "vfe0_clk_src",
 523		.parent_names = gcc_xo_gpll0_gpll2,
 524		.num_parents = 3,
 525		.ops = &clk_rcg2_ops,
 526	},
 527};
 528
 529static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
 530	F(19200000, P_XO, 1, 0, 0),
 531	F(50000000, P_GPLL0, 16, 0, 0),
 532	{ }
 533};
 534
 535static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 536	.cmd_rcgr = 0x0200c,
 537	.hid_width = 5,
 538	.parent_map = gcc_xo_gpll0_map,
 539	.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 540	.clkr.hw.init = &(struct clk_init_data){
 541		.name = "blsp1_qup1_i2c_apps_clk_src",
 542		.parent_names = gcc_xo_gpll0,
 543		.num_parents = 2,
 544		.ops = &clk_rcg2_ops,
 545	},
 546};
 547
 548static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
 549	F(960000, P_XO, 10, 1, 2),
 550	F(4800000, P_XO, 4, 0, 0),
 551	F(9600000, P_XO, 2, 0, 0),
 552	F(16000000, P_GPLL0, 10, 1, 5),
 553	F(19200000, P_XO, 1, 0, 0),
 554	F(25000000, P_GPLL0, 16, 1, 2),
 555	F(50000000, P_GPLL0, 16, 0, 0),
 556	{ }
 557};
 558
 559static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 560	.cmd_rcgr = 0x02024,
 561	.mnd_width = 8,
 562	.hid_width = 5,
 563	.parent_map = gcc_xo_gpll0_map,
 564	.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 565	.clkr.hw.init = &(struct clk_init_data){
 566		.name = "blsp1_qup1_spi_apps_clk_src",
 567		.parent_names = gcc_xo_gpll0,
 568		.num_parents = 2,
 569		.ops = &clk_rcg2_ops,
 570	},
 571};
 572
 573static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 574	.cmd_rcgr = 0x03000,
 575	.hid_width = 5,
 576	.parent_map = gcc_xo_gpll0_map,
 577	.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 578	.clkr.hw.init = &(struct clk_init_data){
 579		.name = "blsp1_qup2_i2c_apps_clk_src",
 580		.parent_names = gcc_xo_gpll0,
 581		.num_parents = 2,
 582		.ops = &clk_rcg2_ops,
 583	},
 584};
 585
 586static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 587	.cmd_rcgr = 0x03014,
 588	.mnd_width = 8,
 589	.hid_width = 5,
 590	.parent_map = gcc_xo_gpll0_map,
 591	.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 592	.clkr.hw.init = &(struct clk_init_data){
 593		.name = "blsp1_qup2_spi_apps_clk_src",
 594		.parent_names = gcc_xo_gpll0,
 595		.num_parents = 2,
 596		.ops = &clk_rcg2_ops,
 597	},
 598};
 599
 600static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 601	.cmd_rcgr = 0x04000,
 602	.hid_width = 5,
 603	.parent_map = gcc_xo_gpll0_map,
 604	.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 605	.clkr.hw.init = &(struct clk_init_data){
 606		.name = "blsp1_qup3_i2c_apps_clk_src",
 607		.parent_names = gcc_xo_gpll0,
 608		.num_parents = 2,
 609		.ops = &clk_rcg2_ops,
 610	},
 611};
 612
 613static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 614	.cmd_rcgr = 0x04024,
 615	.mnd_width = 8,
 616	.hid_width = 5,
 617	.parent_map = gcc_xo_gpll0_map,
 618	.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 619	.clkr.hw.init = &(struct clk_init_data){
 620		.name = "blsp1_qup3_spi_apps_clk_src",
 621		.parent_names = gcc_xo_gpll0,
 622		.num_parents = 2,
 623		.ops = &clk_rcg2_ops,
 624	},
 625};
 626
 627static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 628	.cmd_rcgr = 0x05000,
 629	.hid_width = 5,
 630	.parent_map = gcc_xo_gpll0_map,
 631	.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 632	.clkr.hw.init = &(struct clk_init_data){
 633		.name = "blsp1_qup4_i2c_apps_clk_src",
 634		.parent_names = gcc_xo_gpll0,
 635		.num_parents = 2,
 636		.ops = &clk_rcg2_ops,
 637	},
 638};
 639
 640static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 641	.cmd_rcgr = 0x05024,
 642	.mnd_width = 8,
 643	.hid_width = 5,
 644	.parent_map = gcc_xo_gpll0_map,
 645	.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 646	.clkr.hw.init = &(struct clk_init_data){
 647		.name = "blsp1_qup4_spi_apps_clk_src",
 648		.parent_names = gcc_xo_gpll0,
 649		.num_parents = 2,
 650		.ops = &clk_rcg2_ops,
 651	},
 652};
 653
 654static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 655	.cmd_rcgr = 0x06000,
 656	.hid_width = 5,
 657	.parent_map = gcc_xo_gpll0_map,
 658	.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 659	.clkr.hw.init = &(struct clk_init_data){
 660		.name = "blsp1_qup5_i2c_apps_clk_src",
 661		.parent_names = gcc_xo_gpll0,
 662		.num_parents = 2,
 663		.ops = &clk_rcg2_ops,
 664	},
 665};
 666
 667static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 668	.cmd_rcgr = 0x06024,
 669	.mnd_width = 8,
 670	.hid_width = 5,
 671	.parent_map = gcc_xo_gpll0_map,
 672	.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 673	.clkr.hw.init = &(struct clk_init_data){
 674		.name = "blsp1_qup5_spi_apps_clk_src",
 675		.parent_names = gcc_xo_gpll0,
 676		.num_parents = 2,
 677		.ops = &clk_rcg2_ops,
 678	},
 679};
 680
 681static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 682	.cmd_rcgr = 0x07000,
 683	.hid_width = 5,
 684	.parent_map = gcc_xo_gpll0_map,
 685	.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 686	.clkr.hw.init = &(struct clk_init_data){
 687		.name = "blsp1_qup6_i2c_apps_clk_src",
 688		.parent_names = gcc_xo_gpll0,
 689		.num_parents = 2,
 690		.ops = &clk_rcg2_ops,
 691	},
 692};
 693
 694static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 695	.cmd_rcgr = 0x07024,
 696	.mnd_width = 8,
 697	.hid_width = 5,
 698	.parent_map = gcc_xo_gpll0_map,
 699	.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 700	.clkr.hw.init = &(struct clk_init_data){
 701		.name = "blsp1_qup6_spi_apps_clk_src",
 702		.parent_names = gcc_xo_gpll0,
 703		.num_parents = 2,
 704		.ops = &clk_rcg2_ops,
 705	},
 706};
 707
 708static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
 709	F(3686400, P_GPLL0, 1, 72, 15625),
 710	F(7372800, P_GPLL0, 1, 144, 15625),
 711	F(14745600, P_GPLL0, 1, 288, 15625),
 712	F(16000000, P_GPLL0, 10, 1, 5),
 713	F(19200000, P_XO, 1, 0, 0),
 714	F(24000000, P_GPLL0, 1, 3, 100),
 715	F(25000000, P_GPLL0, 16, 1, 2),
 716	F(32000000, P_GPLL0, 1, 1, 25),
 717	F(40000000, P_GPLL0, 1, 1, 20),
 718	F(46400000, P_GPLL0, 1, 29, 500),
 719	F(48000000, P_GPLL0, 1, 3, 50),
 720	F(51200000, P_GPLL0, 1, 8, 125),
 721	F(56000000, P_GPLL0, 1, 7, 100),
 722	F(58982400, P_GPLL0, 1, 1152, 15625),
 723	F(60000000, P_GPLL0, 1, 3, 40),
 724	{ }
 725};
 726
 727static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 728	.cmd_rcgr = 0x02044,
 729	.mnd_width = 16,
 730	.hid_width = 5,
 731	.parent_map = gcc_xo_gpll0_map,
 732	.freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
 733	.clkr.hw.init = &(struct clk_init_data){
 734		.name = "blsp1_uart1_apps_clk_src",
 735		.parent_names = gcc_xo_gpll0,
 736		.num_parents = 2,
 737		.ops = &clk_rcg2_ops,
 738	},
 739};
 740
 741static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 742	.cmd_rcgr = 0x03034,
 743	.mnd_width = 16,
 744	.hid_width = 5,
 745	.parent_map = gcc_xo_gpll0_map,
 746	.freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
 747	.clkr.hw.init = &(struct clk_init_data){
 748		.name = "blsp1_uart2_apps_clk_src",
 749		.parent_names = gcc_xo_gpll0,
 750		.num_parents = 2,
 751		.ops = &clk_rcg2_ops,
 752	},
 753};
 754
 755static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = {
 756	F(19200000,	P_XO, 1, 0,	0),
 757	{ }
 758};
 759
 760static struct clk_rcg2 cci_clk_src = {
 761	.cmd_rcgr = 0x51000,
 762	.mnd_width = 8,
 763	.hid_width = 5,
 764	.parent_map = gcc_xo_gpll0a_map,
 765	.freq_tbl = ftbl_gcc_camss_cci_clk,
 766	.clkr.hw.init = &(struct clk_init_data){
 767		.name = "cci_clk_src",
 768		.parent_names = gcc_xo_gpll0a,
 769		.num_parents = 2,
 770		.ops = &clk_rcg2_ops,
 771	},
 772};
 773
 774static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
 775	F(100000000, P_GPLL0, 8, 0, 0),
 776	F(200000000, P_GPLL0, 4, 0, 0),
 777	{ }
 778};
 779
 780static struct clk_rcg2 camss_gp0_clk_src = {
 781	.cmd_rcgr = 0x54000,
 782	.mnd_width = 8,
 783	.hid_width = 5,
 784	.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 785	.freq_tbl = ftbl_gcc_camss_gp0_1_clk,
 786	.clkr.hw.init = &(struct clk_init_data){
 787		.name = "camss_gp0_clk_src",
 788		.parent_names = gcc_xo_gpll0_gpll1a_sleep,
 789		.num_parents = 4,
 790		.ops = &clk_rcg2_ops,
 791	},
 792};
 793
 794static struct clk_rcg2 camss_gp1_clk_src = {
 795	.cmd_rcgr = 0x55000,
 796	.mnd_width = 8,
 797	.hid_width = 5,
 798	.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 799	.freq_tbl = ftbl_gcc_camss_gp0_1_clk,
 800	.clkr.hw.init = &(struct clk_init_data){
 801		.name = "camss_gp1_clk_src",
 802		.parent_names = gcc_xo_gpll0_gpll1a_sleep,
 803		.num_parents = 4,
 804		.ops = &clk_rcg2_ops,
 805	},
 806};
 807
 808static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = {
 809	F(133330000, P_GPLL0, 6, 0,	0),
 810	F(266670000, P_GPLL0, 3, 0,	0),
 811	F(320000000, P_GPLL0, 2.5, 0, 0),
 812	{ }
 813};
 814
 815static struct clk_rcg2 jpeg0_clk_src = {
 816	.cmd_rcgr = 0x57000,
 817	.hid_width = 5,
 818	.parent_map = gcc_xo_gpll0_map,
 819	.freq_tbl = ftbl_gcc_camss_jpeg0_clk,
 820	.clkr.hw.init = &(struct clk_init_data){
 821		.name = "jpeg0_clk_src",
 822		.parent_names = gcc_xo_gpll0,
 823		.num_parents = 2,
 824		.ops = &clk_rcg2_ops,
 825	},
 826};
 827
 828static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = {
 829	F(9600000, P_XO, 2, 0, 0),
 830	F(23880000, P_GPLL0, 1, 2, 67),
 831	F(66670000, P_GPLL0, 12, 0, 0),
 832	{ }
 833};
 834
 835static struct clk_rcg2 mclk0_clk_src = {
 836	.cmd_rcgr = 0x52000,
 837	.mnd_width = 8,
 838	.hid_width = 5,
 839	.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 840	.freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
 841	.clkr.hw.init = &(struct clk_init_data){
 842		.name = "mclk0_clk_src",
 843		.parent_names = gcc_xo_gpll0_gpll1a_sleep,
 844		.num_parents = 4,
 845		.ops = &clk_rcg2_ops,
 846	},
 847};
 848
 849static struct clk_rcg2 mclk1_clk_src = {
 850	.cmd_rcgr = 0x53000,
 851	.mnd_width = 8,
 852	.hid_width = 5,
 853	.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 854	.freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
 855	.clkr.hw.init = &(struct clk_init_data){
 856		.name = "mclk1_clk_src",
 857		.parent_names = gcc_xo_gpll0_gpll1a_sleep,
 858		.num_parents = 4,
 859		.ops = &clk_rcg2_ops,
 860	},
 861};
 862
 863static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = {
 864	F(100000000, P_GPLL0, 8, 0,	0),
 865	F(200000000, P_GPLL0, 4, 0,	0),
 866	{ }
 867};
 868
 869static struct clk_rcg2 csi0phytimer_clk_src = {
 870	.cmd_rcgr = 0x4e000,
 871	.hid_width = 5,
 872	.parent_map = gcc_xo_gpll0_gpll1a_map,
 873	.freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
 874	.clkr.hw.init = &(struct clk_init_data){
 875		.name = "csi0phytimer_clk_src",
 876		.parent_names = gcc_xo_gpll0_gpll1a,
 877		.num_parents = 3,
 878		.ops = &clk_rcg2_ops,
 879	},
 880};
 881
 882static struct clk_rcg2 csi1phytimer_clk_src = {
 883	.cmd_rcgr = 0x4f000,
 884	.hid_width = 5,
 885	.parent_map = gcc_xo_gpll0_gpll1a_map,
 886	.freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
 887	.clkr.hw.init = &(struct clk_init_data){
 888		.name = "csi1phytimer_clk_src",
 889		.parent_names = gcc_xo_gpll0_gpll1a,
 890		.num_parents = 3,
 891		.ops = &clk_rcg2_ops,
 892	},
 893};
 894
 895static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = {
 896	F(160000000, P_GPLL0, 5, 0, 0),
 897	F(320000000, P_GPLL0, 2.5, 0, 0),
 898	F(465000000, P_GPLL2, 2, 0, 0),
 899	{ }
 900};
 901
 902static struct clk_rcg2 cpp_clk_src = {
 903	.cmd_rcgr = 0x58018,
 904	.hid_width = 5,
 905	.parent_map = gcc_xo_gpll0_gpll2_map,
 906	.freq_tbl = ftbl_gcc_camss_cpp_clk,
 907	.clkr.hw.init = &(struct clk_init_data){
 908		.name = "cpp_clk_src",
 909		.parent_names = gcc_xo_gpll0_gpll2,
 910		.num_parents = 3,
 911		.ops = &clk_rcg2_ops,
 912	},
 913};
 914
 915static const struct freq_tbl ftbl_gcc_crypto_clk[] = {
 916	F(50000000, P_GPLL0, 16, 0, 0),
 917	F(80000000, P_GPLL0, 10, 0, 0),
 918	F(100000000, P_GPLL0, 8, 0, 0),
 919	F(160000000, P_GPLL0, 5, 0, 0),
 920	{ }
 921};
 922
 923static struct clk_rcg2 crypto_clk_src = {
 924	.cmd_rcgr = 0x16004,
 925	.hid_width = 5,
 926	.parent_map = gcc_xo_gpll0_map,
 927	.freq_tbl = ftbl_gcc_crypto_clk,
 928	.clkr.hw.init = &(struct clk_init_data){
 929		.name = "crypto_clk_src",
 930		.parent_names = gcc_xo_gpll0,
 931		.num_parents = 2,
 932		.ops = &clk_rcg2_ops,
 933	},
 934};
 935
 936static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = {
 937	F(19200000, P_XO, 1, 0,	0),
 938	{ }
 939};
 940
 941static struct clk_rcg2 gp1_clk_src = {
 942	.cmd_rcgr = 0x08004,
 943	.mnd_width = 8,
 944	.hid_width = 5,
 945	.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 946	.freq_tbl = ftbl_gcc_gp1_3_clk,
 947	.clkr.hw.init = &(struct clk_init_data){
 948		.name = "gp1_clk_src",
 949		.parent_names = gcc_xo_gpll0_gpll1a_sleep,
 950		.num_parents = 3,
 951		.ops = &clk_rcg2_ops,
 952	},
 953};
 954
 955static struct clk_rcg2 gp2_clk_src = {
 956	.cmd_rcgr = 0x09004,
 957	.mnd_width = 8,
 958	.hid_width = 5,
 959	.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 960	.freq_tbl = ftbl_gcc_gp1_3_clk,
 961	.clkr.hw.init = &(struct clk_init_data){
 962		.name = "gp2_clk_src",
 963		.parent_names = gcc_xo_gpll0_gpll1a_sleep,
 964		.num_parents = 3,
 965		.ops = &clk_rcg2_ops,
 966	},
 967};
 968
 969static struct clk_rcg2 gp3_clk_src = {
 970	.cmd_rcgr = 0x0a004,
 971	.mnd_width = 8,
 972	.hid_width = 5,
 973	.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 974	.freq_tbl = ftbl_gcc_gp1_3_clk,
 975	.clkr.hw.init = &(struct clk_init_data){
 976		.name = "gp3_clk_src",
 977		.parent_names = gcc_xo_gpll0_gpll1a_sleep,
 978		.num_parents = 3,
 979		.ops = &clk_rcg2_ops,
 980	},
 981};
 982
 983static struct clk_rcg2 byte0_clk_src = {
 984	.cmd_rcgr = 0x4d044,
 985	.hid_width = 5,
 986	.parent_map = gcc_xo_gpll0a_dsibyte_map,
 987	.clkr.hw.init = &(struct clk_init_data){
 988		.name = "byte0_clk_src",
 989		.parent_names = gcc_xo_gpll0a_dsibyte,
 990		.num_parents = 3,
 991		.ops = &clk_byte2_ops,
 992		.flags = CLK_SET_RATE_PARENT,
 993	},
 994};
 995
 996static const struct freq_tbl ftbl_gcc_mdss_esc0_clk[] = {
 997	F(19200000, P_XO, 1, 0, 0),
 998	{ }
 999};
1000
1001static struct clk_rcg2 esc0_clk_src = {
1002	.cmd_rcgr = 0x4d05c,
1003	.hid_width = 5,
1004	.parent_map = gcc_xo_dsibyte_map,
1005	.freq_tbl = ftbl_gcc_mdss_esc0_clk,
1006	.clkr.hw.init = &(struct clk_init_data){
1007		.name = "esc0_clk_src",
1008		.parent_names = gcc_xo_dsibyte,
1009		.num_parents = 2,
1010		.ops = &clk_rcg2_ops,
1011	},
1012};
1013
1014static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
1015	F(50000000, P_GPLL0, 16, 0, 0),
1016	F(80000000, P_GPLL0, 10, 0, 0),
1017	F(100000000, P_GPLL0, 8, 0, 0),
1018	F(160000000, P_GPLL0, 5, 0, 0),
1019	F(177780000, P_GPLL0, 4.5, 0, 0),
1020	F(200000000, P_GPLL0, 4, 0, 0),
1021	F(266670000, P_GPLL0, 3, 0, 0),
1022	F(320000000, P_GPLL0, 2.5, 0, 0),
1023	{ }
1024};
1025
1026static struct clk_rcg2 mdp_clk_src = {
1027	.cmd_rcgr = 0x4d014,
1028	.hid_width = 5,
1029	.parent_map = gcc_xo_gpll0_dsiphy_map,
1030	.freq_tbl = ftbl_gcc_mdss_mdp_clk,
1031	.clkr.hw.init = &(struct clk_init_data){
1032		.name = "mdp_clk_src",
1033		.parent_names = gcc_xo_gpll0_dsiphy,
1034		.num_parents = 3,
1035		.ops = &clk_rcg2_ops,
1036	},
1037};
1038
1039static struct clk_rcg2 pclk0_clk_src = {
1040	.cmd_rcgr = 0x4d000,
1041	.mnd_width = 8,
1042	.hid_width = 5,
1043	.parent_map = gcc_xo_gpll0a_dsiphy_map,
1044	.clkr.hw.init = &(struct clk_init_data){
1045		.name = "pclk0_clk_src",
1046		.parent_names = gcc_xo_gpll0a_dsiphy,
1047		.num_parents = 3,
1048		.ops = &clk_pixel_ops,
1049		.flags = CLK_SET_RATE_PARENT,
1050	},
1051};
1052
1053static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
1054	F(19200000, P_XO, 1, 0,	0),
1055	{ }
1056};
1057
1058static struct clk_rcg2 vsync_clk_src = {
1059	.cmd_rcgr = 0x4d02c,
1060	.hid_width = 5,
1061	.parent_map = gcc_xo_gpll0a_map,
1062	.freq_tbl = ftbl_gcc_mdss_vsync_clk,
1063	.clkr.hw.init = &(struct clk_init_data){
1064		.name = "vsync_clk_src",
1065		.parent_names = gcc_xo_gpll0a,
1066		.num_parents = 2,
1067		.ops = &clk_rcg2_ops,
1068	},
1069};
1070
1071static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
1072	F(64000000, P_GPLL0, 12.5, 0, 0),
1073	{ }
1074};
1075
1076static struct clk_rcg2 pdm2_clk_src = {
1077	.cmd_rcgr = 0x44010,
1078	.hid_width = 5,
1079	.parent_map = gcc_xo_gpll0_map,
1080	.freq_tbl = ftbl_gcc_pdm2_clk,
1081	.clkr.hw.init = &(struct clk_init_data){
1082		.name = "pdm2_clk_src",
1083		.parent_names = gcc_xo_gpll0,
1084		.num_parents = 2,
1085		.ops = &clk_rcg2_ops,
1086	},
1087};
1088
1089static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
1090	F(144000, P_XO, 16, 3, 25),
1091	F(400000, P_XO, 12, 1, 4),
1092	F(20000000, P_GPLL0, 10, 1, 4),
1093	F(25000000, P_GPLL0, 16, 1, 2),
1094	F(50000000, P_GPLL0, 16, 0, 0),
1095	F(100000000, P_GPLL0, 8, 0, 0),
1096	F(177770000, P_GPLL0, 4.5, 0, 0),
1097	{ }
1098};
1099
1100static struct clk_rcg2 sdcc1_apps_clk_src = {
1101	.cmd_rcgr = 0x42004,
1102	.mnd_width = 8,
1103	.hid_width = 5,
1104	.parent_map = gcc_xo_gpll0_map,
1105	.freq_tbl = ftbl_gcc_sdcc1_apps_clk,
1106	.clkr.hw.init = &(struct clk_init_data){
1107		.name = "sdcc1_apps_clk_src",
1108		.parent_names = gcc_xo_gpll0,
1109		.num_parents = 2,
1110		.ops = &clk_rcg2_floor_ops,
1111	},
1112};
1113
1114static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk[] = {
1115	F(144000, P_XO, 16, 3, 25),
1116	F(400000, P_XO, 12, 1, 4),
1117	F(20000000, P_GPLL0, 10, 1, 4),
1118	F(25000000, P_GPLL0, 16, 1, 2),
1119	F(50000000, P_GPLL0, 16, 0, 0),
1120	F(100000000, P_GPLL0, 8, 0, 0),
1121	F(200000000, P_GPLL0, 4, 0, 0),
1122	{ }
1123};
1124
1125static struct clk_rcg2 sdcc2_apps_clk_src = {
1126	.cmd_rcgr = 0x43004,
1127	.mnd_width = 8,
1128	.hid_width = 5,
1129	.parent_map = gcc_xo_gpll0_map,
1130	.freq_tbl = ftbl_gcc_sdcc2_apps_clk,
1131	.clkr.hw.init = &(struct clk_init_data){
1132		.name = "sdcc2_apps_clk_src",
1133		.parent_names = gcc_xo_gpll0,
1134		.num_parents = 2,
1135		.ops = &clk_rcg2_floor_ops,
1136	},
1137};
1138
1139static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = {
1140	F(155000000, P_GPLL2, 6, 0, 0),
1141	F(310000000, P_GPLL2, 3, 0, 0),
1142	F(400000000, P_GPLL0, 2, 0, 0),
1143	{ }
1144};
1145
1146static struct clk_rcg2 apss_tcu_clk_src = {
1147	.cmd_rcgr = 0x1207c,
1148	.hid_width = 5,
1149	.parent_map = gcc_xo_gpll0a_gpll1_gpll2_map,
1150	.freq_tbl = ftbl_gcc_apss_tcu_clk,
1151	.clkr.hw.init = &(struct clk_init_data){
1152		.name = "apss_tcu_clk_src",
1153		.parent_names = gcc_xo_gpll0a_gpll1_gpll2,
1154		.num_parents = 4,
1155		.ops = &clk_rcg2_ops,
1156	},
1157};
1158
1159static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = {
1160	F(19200000, P_XO, 1, 0, 0),
1161	F(100000000, P_GPLL0, 8, 0, 0),
1162	F(200000000, P_GPLL0, 4, 0, 0),
1163	F(266500000, P_BIMC, 4, 0, 0),
1164	F(400000000, P_GPLL0, 2, 0, 0),
1165	F(533000000, P_BIMC, 2, 0, 0),
1166	{ }
1167};
1168
1169static struct clk_rcg2 bimc_gpu_clk_src = {
1170	.cmd_rcgr = 0x31028,
1171	.hid_width = 5,
1172	.parent_map = gcc_xo_gpll0_bimc_map,
1173	.freq_tbl = ftbl_gcc_bimc_gpu_clk,
1174	.clkr.hw.init = &(struct clk_init_data){
1175		.name = "bimc_gpu_clk_src",
1176		.parent_names = gcc_xo_gpll0_bimc,
1177		.num_parents = 3,
1178		.flags = CLK_GET_RATE_NOCACHE,
1179		.ops = &clk_rcg2_ops,
1180	},
1181};
1182
1183static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1184	F(80000000, P_GPLL0, 10, 0, 0),
1185	{ }
1186};
1187
1188static struct clk_rcg2 usb_hs_system_clk_src = {
1189	.cmd_rcgr = 0x41010,
1190	.hid_width = 5,
1191	.parent_map = gcc_xo_gpll0_map,
1192	.freq_tbl = ftbl_gcc_usb_hs_system_clk,
1193	.clkr.hw.init = &(struct clk_init_data){
1194		.name = "usb_hs_system_clk_src",
1195		.parent_names = gcc_xo_gpll0,
1196		.num_parents = 2,
1197		.ops = &clk_rcg2_ops,
1198	},
1199};
1200
1201static const struct freq_tbl ftbl_gcc_ultaudio_ahb_clk[] = {
1202	F(3200000, P_XO, 6, 0, 0),
1203	F(6400000, P_XO, 3, 0, 0),
1204	F(9600000, P_XO, 2, 0, 0),
1205	F(19200000, P_XO, 1, 0, 0),
1206	F(40000000, P_GPLL0, 10, 1, 2),
1207	F(66670000, P_GPLL0, 12, 0, 0),
1208	F(80000000, P_GPLL0, 10, 0, 0),
1209	F(100000000, P_GPLL0, 8, 0, 0),
1210	{ }
1211};
1212
1213static struct clk_rcg2 ultaudio_ahbfabric_clk_src = {
1214	.cmd_rcgr = 0x1c010,
1215	.hid_width = 5,
1216	.mnd_width = 8,
1217	.parent_map = gcc_xo_gpll0_gpll1_sleep_map,
1218	.freq_tbl = ftbl_gcc_ultaudio_ahb_clk,
1219	.clkr.hw.init = &(struct clk_init_data){
1220		.name = "ultaudio_ahbfabric_clk_src",
1221		.parent_names = gcc_xo_gpll0_gpll1_sleep,
1222		.num_parents = 4,
1223		.ops = &clk_rcg2_ops,
1224	},
1225};
1226
1227static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = {
1228	.halt_reg = 0x1c028,
1229	.clkr = {
1230		.enable_reg = 0x1c028,
1231		.enable_mask = BIT(0),
1232		.hw.init = &(struct clk_init_data){
1233			.name = "gcc_ultaudio_ahbfabric_ixfabric_clk",
1234			.parent_names = (const char *[]){
1235				"ultaudio_ahbfabric_clk_src",
1236			},
1237			.num_parents = 1,
1238			.flags = CLK_SET_RATE_PARENT,
1239			.ops = &clk_branch2_ops,
1240		},
1241	},
1242};
1243
1244static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = {
1245	.halt_reg = 0x1c024,
1246	.clkr = {
1247		.enable_reg = 0x1c024,
1248		.enable_mask = BIT(0),
1249		.hw.init = &(struct clk_init_data){
1250			.name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk",
1251			.parent_names = (const char *[]){
1252				"ultaudio_ahbfabric_clk_src",
1253			},
1254			.num_parents = 1,
1255			.flags = CLK_SET_RATE_PARENT,
1256			.ops = &clk_branch2_ops,
1257		},
1258	},
1259};
1260
1261static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = {
1262	F(128000, P_XO, 10, 1, 15),
1263	F(256000, P_XO, 5, 1, 15),
1264	F(384000, P_XO, 5, 1, 10),
1265	F(512000, P_XO, 5, 2, 15),
1266	F(576000, P_XO, 5, 3, 20),
1267	F(705600, P_GPLL1, 16, 1, 80),
1268	F(768000, P_XO, 5, 1, 5),
1269	F(800000, P_XO, 5, 5, 24),
1270	F(1024000, P_XO, 5, 4, 15),
1271	F(1152000, P_XO, 1, 3, 50),
1272	F(1411200, P_GPLL1, 16, 1, 40),
1273	F(1536000, P_XO, 1, 2, 25),
1274	F(1600000, P_XO, 12, 0, 0),
1275	F(1728000, P_XO, 5, 9, 20),
1276	F(2048000, P_XO, 5, 8, 15),
1277	F(2304000, P_XO, 5, 3, 5),
1278	F(2400000, P_XO, 8, 0, 0),
1279	F(2822400, P_GPLL1, 16, 1, 20),
1280	F(3072000, P_XO, 5, 4, 5),
1281	F(4096000, P_GPLL1, 9, 2, 49),
1282	F(4800000, P_XO, 4, 0, 0),
1283	F(5644800, P_GPLL1, 16, 1, 10),
1284	F(6144000, P_GPLL1, 7, 1, 21),
1285	F(8192000, P_GPLL1, 9, 4, 49),
1286	F(9600000, P_XO, 2, 0, 0),
1287	F(11289600, P_GPLL1, 16, 1, 5),
1288	F(12288000, P_GPLL1, 7, 2, 21),
1289	{ }
1290};
1291
1292static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = {
1293	.cmd_rcgr = 0x1c054,
1294	.hid_width = 5,
1295	.mnd_width = 8,
1296	.parent_map = gcc_xo_gpll1_epi2s_emclk_sleep_map,
1297	.freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1298	.clkr.hw.init = &(struct clk_init_data){
1299		.name = "ultaudio_lpaif_pri_i2s_clk_src",
1300		.parent_names = gcc_xo_gpll1_epi2s_emclk_sleep,
1301		.num_parents = 5,
1302		.ops = &clk_rcg2_ops,
1303	},
1304};
1305
1306static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk = {
1307	.halt_reg = 0x1c068,
1308	.clkr = {
1309		.enable_reg = 0x1c068,
1310		.enable_mask = BIT(0),
1311		.hw.init = &(struct clk_init_data){
1312			.name = "gcc_ultaudio_lpaif_pri_i2s_clk",
1313			.parent_names = (const char *[]){
1314				"ultaudio_lpaif_pri_i2s_clk_src",
1315			},
1316			.num_parents = 1,
1317			.flags = CLK_SET_RATE_PARENT,
1318			.ops = &clk_branch2_ops,
1319		},
1320	},
1321};
1322
1323static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = {
1324	.cmd_rcgr = 0x1c06c,
1325	.hid_width = 5,
1326	.mnd_width = 8,
1327	.parent_map = gcc_xo_gpll1_esi2s_emclk_sleep_map,
1328	.freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1329	.clkr.hw.init = &(struct clk_init_data){
1330		.name = "ultaudio_lpaif_sec_i2s_clk_src",
1331		.parent_names = gcc_xo_gpll1_esi2s_emclk_sleep,
1332		.num_parents = 5,
1333		.ops = &clk_rcg2_ops,
1334	},
1335};
1336
1337static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk = {
1338	.halt_reg = 0x1c080,
1339	.clkr = {
1340		.enable_reg = 0x1c080,
1341		.enable_mask = BIT(0),
1342		.hw.init = &(struct clk_init_data){
1343			.name = "gcc_ultaudio_lpaif_sec_i2s_clk",
1344			.parent_names = (const char *[]){
1345				"ultaudio_lpaif_sec_i2s_clk_src",
1346			},
1347			.num_parents = 1,
1348			.flags = CLK_SET_RATE_PARENT,
1349			.ops = &clk_branch2_ops,
1350		},
1351	},
1352};
1353
1354static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = {
1355	.cmd_rcgr = 0x1c084,
1356	.hid_width = 5,
1357	.mnd_width = 8,
1358	.parent_map = gcc_xo_gpll1_emclk_sleep_map,
1359	.freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1360	.clkr.hw.init = &(struct clk_init_data){
1361		.name = "ultaudio_lpaif_aux_i2s_clk_src",
1362		.parent_names = gcc_xo_gpll1_esi2s_emclk_sleep,
1363		.num_parents = 5,
1364		.ops = &clk_rcg2_ops,
1365	},
1366};
1367
1368static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk = {
1369	.halt_reg = 0x1c098,
1370	.clkr = {
1371		.enable_reg = 0x1c098,
1372		.enable_mask = BIT(0),
1373		.hw.init = &(struct clk_init_data){
1374			.name = "gcc_ultaudio_lpaif_aux_i2s_clk",
1375			.parent_names = (const char *[]){
1376				"ultaudio_lpaif_aux_i2s_clk_src",
1377			},
1378			.num_parents = 1,
1379			.flags = CLK_SET_RATE_PARENT,
1380			.ops = &clk_branch2_ops,
1381		},
1382	},
1383};
1384
1385static const struct freq_tbl ftbl_gcc_ultaudio_xo_clk[] = {
1386	F(19200000, P_XO, 1, 0, 0),
1387	{ }
1388};
1389
1390static struct clk_rcg2 ultaudio_xo_clk_src = {
1391	.cmd_rcgr = 0x1c034,
1392	.hid_width = 5,
1393	.parent_map = gcc_xo_sleep_map,
1394	.freq_tbl = ftbl_gcc_ultaudio_xo_clk,
1395	.clkr.hw.init = &(struct clk_init_data){
1396		.name = "ultaudio_xo_clk_src",
1397		.parent_names = gcc_xo_sleep,
1398		.num_parents = 2,
1399		.ops = &clk_rcg2_ops,
1400	},
1401};
1402
1403static struct clk_branch gcc_ultaudio_avsync_xo_clk = {
1404	.halt_reg = 0x1c04c,
1405	.clkr = {
1406		.enable_reg = 0x1c04c,
1407		.enable_mask = BIT(0),
1408		.hw.init = &(struct clk_init_data){
1409			.name = "gcc_ultaudio_avsync_xo_clk",
1410			.parent_names = (const char *[]){
1411				"ultaudio_xo_clk_src",
1412			},
1413			.num_parents = 1,
1414			.flags = CLK_SET_RATE_PARENT,
1415			.ops = &clk_branch2_ops,
1416		},
1417	},
1418};
1419
1420static struct clk_branch gcc_ultaudio_stc_xo_clk = {
1421	.halt_reg = 0x1c050,
1422	.clkr = {
1423		.enable_reg = 0x1c050,
1424		.enable_mask = BIT(0),
1425		.hw.init = &(struct clk_init_data){
1426			.name = "gcc_ultaudio_stc_xo_clk",
1427			.parent_names = (const char *[]){
1428				"ultaudio_xo_clk_src",
1429			},
1430			.num_parents = 1,
1431			.flags = CLK_SET_RATE_PARENT,
1432			.ops = &clk_branch2_ops,
1433		},
1434	},
1435};
1436
1437static const struct freq_tbl ftbl_codec_clk[] = {
1438	F(9600000, P_XO, 2, 0, 0),
1439	F(12288000, P_XO, 1, 16, 25),
1440	F(19200000, P_XO, 1, 0, 0),
1441	F(11289600, P_EXT_MCLK, 1, 0, 0),
1442	{ }
1443};
1444
1445static struct clk_rcg2 codec_digcodec_clk_src = {
1446	.cmd_rcgr = 0x1c09c,
1447	.mnd_width = 8,
1448	.hid_width = 5,
1449	.parent_map = gcc_xo_gpll1_emclk_sleep_map,
1450	.freq_tbl = ftbl_codec_clk,
1451	.clkr.hw.init = &(struct clk_init_data){
1452		.name = "codec_digcodec_clk_src",
1453		.parent_names = gcc_xo_gpll1_emclk_sleep,
1454		.num_parents = 4,
1455		.ops = &clk_rcg2_ops,
1456	},
1457};
1458
1459static struct clk_branch gcc_codec_digcodec_clk = {
1460	.halt_reg = 0x1c0b0,
1461	.clkr = {
1462		.enable_reg = 0x1c0b0,
1463		.enable_mask = BIT(0),
1464		.hw.init = &(struct clk_init_data){
1465			.name = "gcc_ultaudio_codec_digcodec_clk",
1466			.parent_names = (const char *[]){
1467				"codec_digcodec_clk_src",
1468			},
1469			.num_parents = 1,
1470			.flags = CLK_SET_RATE_PARENT,
1471			.ops = &clk_branch2_ops,
1472		},
1473	},
1474};
1475
1476static struct clk_branch gcc_ultaudio_pcnoc_mport_clk = {
1477	.halt_reg = 0x1c000,
1478	.clkr = {
1479		.enable_reg = 0x1c000,
1480		.enable_mask = BIT(0),
1481		.hw.init = &(struct clk_init_data){
1482			.name = "gcc_ultaudio_pcnoc_mport_clk",
1483			.parent_names = (const char *[]){
1484				"pcnoc_bfdcd_clk_src",
1485			},
1486			.num_parents = 1,
1487			.ops = &clk_branch2_ops,
1488		},
1489	},
1490};
1491
1492static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = {
1493	.halt_reg = 0x1c004,
1494	.clkr = {
1495		.enable_reg = 0x1c004,
1496		.enable_mask = BIT(0),
1497		.hw.init = &(struct clk_init_data){
1498			.name = "gcc_ultaudio_pcnoc_sway_clk",
1499			.parent_names = (const char *[]){
1500				"pcnoc_bfdcd_clk_src",
1501			},
1502			.num_parents = 1,
1503			.ops = &clk_branch2_ops,
1504		},
1505	},
1506};
1507
1508static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
1509	F(100000000, P_GPLL0, 8, 0, 0),
1510	F(160000000, P_GPLL0, 5, 0, 0),
1511	F(228570000, P_GPLL0, 3.5, 0, 0),
1512	{ }
1513};
1514
1515static struct clk_rcg2 vcodec0_clk_src = {
1516	.cmd_rcgr = 0x4C000,
1517	.mnd_width = 8,
1518	.hid_width = 5,
1519	.parent_map = gcc_xo_gpll0_map,
1520	.freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
1521	.clkr.hw.init = &(struct clk_init_data){
1522		.name = "vcodec0_clk_src",
1523		.parent_names = gcc_xo_gpll0,
1524		.num_parents = 2,
1525		.ops = &clk_rcg2_ops,
1526	},
1527};
1528
1529static struct clk_branch gcc_blsp1_ahb_clk = {
1530	.halt_reg = 0x01008,
1531	.halt_check = BRANCH_HALT_VOTED,
1532	.clkr = {
1533		.enable_reg = 0x45004,
1534		.enable_mask = BIT(10),
1535		.hw.init = &(struct clk_init_data){
1536			.name = "gcc_blsp1_ahb_clk",
1537			.parent_names = (const char *[]){
1538				"pcnoc_bfdcd_clk_src",
1539			},
1540			.num_parents = 1,
1541			.ops = &clk_branch2_ops,
1542		},
1543	},
1544};
1545
1546static struct clk_branch gcc_blsp1_sleep_clk = {
1547	.halt_reg = 0x01004,
1548	.clkr = {
1549		.enable_reg = 0x01004,
1550		.enable_mask = BIT(0),
1551		.hw.init = &(struct clk_init_data){
1552			.name = "gcc_blsp1_sleep_clk",
1553			.parent_names = (const char *[]){
1554				"sleep_clk_src",
1555			},
1556			.num_parents = 1,
1557			.flags = CLK_SET_RATE_PARENT,
1558			.ops = &clk_branch2_ops,
1559		},
1560	},
1561};
1562
1563static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1564	.halt_reg = 0x02008,
1565	.clkr = {
1566		.enable_reg = 0x02008,
1567		.enable_mask = BIT(0),
1568		.hw.init = &(struct clk_init_data){
1569			.name = "gcc_blsp1_qup1_i2c_apps_clk",
1570			.parent_names = (const char *[]){
1571				"blsp1_qup1_i2c_apps_clk_src",
1572			},
1573			.num_parents = 1,
1574			.flags = CLK_SET_RATE_PARENT,
1575			.ops = &clk_branch2_ops,
1576		},
1577	},
1578};
1579
1580static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1581	.halt_reg = 0x02004,
1582	.clkr = {
1583		.enable_reg = 0x02004,
1584		.enable_mask = BIT(0),
1585		.hw.init = &(struct clk_init_data){
1586			.name = "gcc_blsp1_qup1_spi_apps_clk",
1587			.parent_names = (const char *[]){
1588				"blsp1_qup1_spi_apps_clk_src",
1589			},
1590			.num_parents = 1,
1591			.flags = CLK_SET_RATE_PARENT,
1592			.ops = &clk_branch2_ops,
1593		},
1594	},
1595};
1596
1597static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1598	.halt_reg = 0x03010,
1599	.clkr = {
1600		.enable_reg = 0x03010,
1601		.enable_mask = BIT(0),
1602		.hw.init = &(struct clk_init_data){
1603			.name = "gcc_blsp1_qup2_i2c_apps_clk",
1604			.parent_names = (const char *[]){
1605				"blsp1_qup2_i2c_apps_clk_src",
1606			},
1607			.num_parents = 1,
1608			.flags = CLK_SET_RATE_PARENT,
1609			.ops = &clk_branch2_ops,
1610		},
1611	},
1612};
1613
1614static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1615	.halt_reg = 0x0300c,
1616	.clkr = {
1617		.enable_reg = 0x0300c,
1618		.enable_mask = BIT(0),
1619		.hw.init = &(struct clk_init_data){
1620			.name = "gcc_blsp1_qup2_spi_apps_clk",
1621			.parent_names = (const char *[]){
1622				"blsp1_qup2_spi_apps_clk_src",
1623			},
1624			.num_parents = 1,
1625			.flags = CLK_SET_RATE_PARENT,
1626			.ops = &clk_branch2_ops,
1627		},
1628	},
1629};
1630
1631static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1632	.halt_reg = 0x04020,
1633	.clkr = {
1634		.enable_reg = 0x04020,
1635		.enable_mask = BIT(0),
1636		.hw.init = &(struct clk_init_data){
1637			.name = "gcc_blsp1_qup3_i2c_apps_clk",
1638			.parent_names = (const char *[]){
1639				"blsp1_qup3_i2c_apps_clk_src",
1640			},
1641			.num_parents = 1,
1642			.flags = CLK_SET_RATE_PARENT,
1643			.ops = &clk_branch2_ops,
1644		},
1645	},
1646};
1647
1648static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1649	.halt_reg = 0x0401c,
1650	.clkr = {
1651		.enable_reg = 0x0401c,
1652		.enable_mask = BIT(0),
1653		.hw.init = &(struct clk_init_data){
1654			.name = "gcc_blsp1_qup3_spi_apps_clk",
1655			.parent_names = (const char *[]){
1656				"blsp1_qup3_spi_apps_clk_src",
1657			},
1658			.num_parents = 1,
1659			.flags = CLK_SET_RATE_PARENT,
1660			.ops = &clk_branch2_ops,
1661		},
1662	},
1663};
1664
1665static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1666	.halt_reg = 0x05020,
1667	.clkr = {
1668		.enable_reg = 0x05020,
1669		.enable_mask = BIT(0),
1670		.hw.init = &(struct clk_init_data){
1671			.name = "gcc_blsp1_qup4_i2c_apps_clk",
1672			.parent_names = (const char *[]){
1673				"blsp1_qup4_i2c_apps_clk_src",
1674			},
1675			.num_parents = 1,
1676			.flags = CLK_SET_RATE_PARENT,
1677			.ops = &clk_branch2_ops,
1678		},
1679	},
1680};
1681
1682static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1683	.halt_reg = 0x0501c,
1684	.clkr = {
1685		.enable_reg = 0x0501c,
1686		.enable_mask = BIT(0),
1687		.hw.init = &(struct clk_init_data){
1688			.name = "gcc_blsp1_qup4_spi_apps_clk",
1689			.parent_names = (const char *[]){
1690				"blsp1_qup4_spi_apps_clk_src",
1691			},
1692			.num_parents = 1,
1693			.flags = CLK_SET_RATE_PARENT,
1694			.ops = &clk_branch2_ops,
1695		},
1696	},
1697};
1698
1699static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1700	.halt_reg = 0x06020,
1701	.clkr = {
1702		.enable_reg = 0x06020,
1703		.enable_mask = BIT(0),
1704		.hw.init = &(struct clk_init_data){
1705			.name = "gcc_blsp1_qup5_i2c_apps_clk",
1706			.parent_names = (const char *[]){
1707				"blsp1_qup5_i2c_apps_clk_src",
1708			},
1709			.num_parents = 1,
1710			.flags = CLK_SET_RATE_PARENT,
1711			.ops = &clk_branch2_ops,
1712		},
1713	},
1714};
1715
1716static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1717	.halt_reg = 0x0601c,
1718	.clkr = {
1719		.enable_reg = 0x0601c,
1720		.enable_mask = BIT(0),
1721		.hw.init = &(struct clk_init_data){
1722			.name = "gcc_blsp1_qup5_spi_apps_clk",
1723			.parent_names = (const char *[]){
1724				"blsp1_qup5_spi_apps_clk_src",
1725			},
1726			.num_parents = 1,
1727			.flags = CLK_SET_RATE_PARENT,
1728			.ops = &clk_branch2_ops,
1729		},
1730	},
1731};
1732
1733static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1734	.halt_reg = 0x07020,
1735	.clkr = {
1736		.enable_reg = 0x07020,
1737		.enable_mask = BIT(0),
1738		.hw.init = &(struct clk_init_data){
1739			.name = "gcc_blsp1_qup6_i2c_apps_clk",
1740			.parent_names = (const char *[]){
1741				"blsp1_qup6_i2c_apps_clk_src",
1742			},
1743			.num_parents = 1,
1744			.flags = CLK_SET_RATE_PARENT,
1745			.ops = &clk_branch2_ops,
1746		},
1747	},
1748};
1749
1750static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1751	.halt_reg = 0x0701c,
1752	.clkr = {
1753		.enable_reg = 0x0701c,
1754		.enable_mask = BIT(0),
1755		.hw.init = &(struct clk_init_data){
1756			.name = "gcc_blsp1_qup6_spi_apps_clk",
1757			.parent_names = (const char *[]){
1758				"blsp1_qup6_spi_apps_clk_src",
1759			},
1760			.num_parents = 1,
1761			.flags = CLK_SET_RATE_PARENT,
1762			.ops = &clk_branch2_ops,
1763		},
1764	},
1765};
1766
1767static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1768	.halt_reg = 0x0203c,
1769	.clkr = {
1770		.enable_reg = 0x0203c,
1771		.enable_mask = BIT(0),
1772		.hw.init = &(struct clk_init_data){
1773			.name = "gcc_blsp1_uart1_apps_clk",
1774			.parent_names = (const char *[]){
1775				"blsp1_uart1_apps_clk_src",
1776			},
1777			.num_parents = 1,
1778			.flags = CLK_SET_RATE_PARENT,
1779			.ops = &clk_branch2_ops,
1780		},
1781	},
1782};
1783
1784static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1785	.halt_reg = 0x0302c,
1786	.clkr = {
1787		.enable_reg = 0x0302c,
1788		.enable_mask = BIT(0),
1789		.hw.init = &(struct clk_init_data){
1790			.name = "gcc_blsp1_uart2_apps_clk",
1791			.parent_names = (const char *[]){
1792				"blsp1_uart2_apps_clk_src",
1793			},
1794			.num_parents = 1,
1795			.flags = CLK_SET_RATE_PARENT,
1796			.ops = &clk_branch2_ops,
1797		},
1798	},
1799};
1800
1801static struct clk_branch gcc_boot_rom_ahb_clk = {
1802	.halt_reg = 0x1300c,
1803	.halt_check = BRANCH_HALT_VOTED,
1804	.clkr = {
1805		.enable_reg = 0x45004,
1806		.enable_mask = BIT(7),
1807		.hw.init = &(struct clk_init_data){
1808			.name = "gcc_boot_rom_ahb_clk",
1809			.parent_names = (const char *[]){
1810				"pcnoc_bfdcd_clk_src",
1811			},
1812			.num_parents = 1,
1813			.ops = &clk_branch2_ops,
1814		},
1815	},
1816};
1817
1818static struct clk_branch gcc_camss_cci_ahb_clk = {
1819	.halt_reg = 0x5101c,
1820	.clkr = {
1821		.enable_reg = 0x5101c,
1822		.enable_mask = BIT(0),
1823		.hw.init = &(struct clk_init_data){
1824			.name = "gcc_camss_cci_ahb_clk",
1825			.parent_names = (const char *[]){
1826				"camss_ahb_clk_src",
1827			},
1828			.num_parents = 1,
1829			.flags = CLK_SET_RATE_PARENT,
1830			.ops = &clk_branch2_ops,
1831		},
1832	},
1833};
1834
1835static struct clk_branch gcc_camss_cci_clk = {
1836	.halt_reg = 0x51018,
1837	.clkr = {
1838		.enable_reg = 0x51018,
1839		.enable_mask = BIT(0),
1840		.hw.init = &(struct clk_init_data){
1841			.name = "gcc_camss_cci_clk",
1842			.parent_names = (const char *[]){
1843				"cci_clk_src",
1844			},
1845			.num_parents = 1,
1846			.flags = CLK_SET_RATE_PARENT,
1847			.ops = &clk_branch2_ops,
1848		},
1849	},
1850};
1851
1852static struct clk_branch gcc_camss_csi0_ahb_clk = {
1853	.halt_reg = 0x4e040,
1854	.clkr = {
1855		.enable_reg = 0x4e040,
1856		.enable_mask = BIT(0),
1857		.hw.init = &(struct clk_init_data){
1858			.name = "gcc_camss_csi0_ahb_clk",
1859			.parent_names = (const char *[]){
1860				"camss_ahb_clk_src",
1861			},
1862			.num_parents = 1,
1863			.flags = CLK_SET_RATE_PARENT,
1864			.ops = &clk_branch2_ops,
1865		},
1866	},
1867};
1868
1869static struct clk_branch gcc_camss_csi0_clk = {
1870	.halt_reg = 0x4e03c,
1871	.clkr = {
1872		.enable_reg = 0x4e03c,
1873		.enable_mask = BIT(0),
1874		.hw.init = &(struct clk_init_data){
1875			.name = "gcc_camss_csi0_clk",
1876			.parent_names = (const char *[]){
1877				"csi0_clk_src",
1878			},
1879			.num_parents = 1,
1880			.flags = CLK_SET_RATE_PARENT,
1881			.ops = &clk_branch2_ops,
1882		},
1883	},
1884};
1885
1886static struct clk_branch gcc_camss_csi0phy_clk = {
1887	.halt_reg = 0x4e048,
1888	.clkr = {
1889		.enable_reg = 0x4e048,
1890		.enable_mask = BIT(0),
1891		.hw.init = &(struct clk_init_data){
1892			.name = "gcc_camss_csi0phy_clk",
1893			.parent_names = (const char *[]){
1894				"csi0_clk_src",
1895			},
1896			.num_parents = 1,
1897			.flags = CLK_SET_RATE_PARENT,
1898			.ops = &clk_branch2_ops,
1899		},
1900	},
1901};
1902
1903static struct clk_branch gcc_camss_csi0pix_clk = {
1904	.halt_reg = 0x4e058,
1905	.clkr = {
1906		.enable_reg = 0x4e058,
1907		.enable_mask = BIT(0),
1908		.hw.init = &(struct clk_init_data){
1909			.name = "gcc_camss_csi0pix_clk",
1910			.parent_names = (const char *[]){
1911				"csi0_clk_src",
1912			},
1913			.num_parents = 1,
1914			.flags = CLK_SET_RATE_PARENT,
1915			.ops = &clk_branch2_ops,
1916		},
1917	},
1918};
1919
1920static struct clk_branch gcc_camss_csi0rdi_clk = {
1921	.halt_reg = 0x4e050,
1922	.clkr = {
1923		.enable_reg = 0x4e050,
1924		.enable_mask = BIT(0),
1925		.hw.init = &(struct clk_init_data){
1926			.name = "gcc_camss_csi0rdi_clk",
1927			.parent_names = (const char *[]){
1928				"csi0_clk_src",
1929			},
1930			.num_parents = 1,
1931			.flags = CLK_SET_RATE_PARENT,
1932			.ops = &clk_branch2_ops,
1933		},
1934	},
1935};
1936
1937static struct clk_branch gcc_camss_csi1_ahb_clk = {
1938	.halt_reg = 0x4f040,
1939	.clkr = {
1940		.enable_reg = 0x4f040,
1941		.enable_mask = BIT(0),
1942		.hw.init = &(struct clk_init_data){
1943			.name = "gcc_camss_csi1_ahb_clk",
1944			.parent_names = (const char *[]){
1945				"camss_ahb_clk_src",
1946			},
1947			.num_parents = 1,
1948			.flags = CLK_SET_RATE_PARENT,
1949			.ops = &clk_branch2_ops,
1950		},
1951	},
1952};
1953
1954static struct clk_branch gcc_camss_csi1_clk = {
1955	.halt_reg = 0x4f03c,
1956	.clkr = {
1957		.enable_reg = 0x4f03c,
1958		.enable_mask = BIT(0),
1959		.hw.init = &(struct clk_init_data){
1960			.name = "gcc_camss_csi1_clk",
1961			.parent_names = (const char *[]){
1962				"csi1_clk_src",
1963			},
1964			.num_parents = 1,
1965			.flags = CLK_SET_RATE_PARENT,
1966			.ops = &clk_branch2_ops,
1967		},
1968	},
1969};
1970
1971static struct clk_branch gcc_camss_csi1phy_clk = {
1972	.halt_reg = 0x4f048,
1973	.clkr = {
1974		.enable_reg = 0x4f048,
1975		.enable_mask = BIT(0),
1976		.hw.init = &(struct clk_init_data){
1977			.name = "gcc_camss_csi1phy_clk",
1978			.parent_names = (const char *[]){
1979				"csi1_clk_src",
1980			},
1981			.num_parents = 1,
1982			.flags = CLK_SET_RATE_PARENT,
1983			.ops = &clk_branch2_ops,
1984		},
1985	},
1986};
1987
1988static struct clk_branch gcc_camss_csi1pix_clk = {
1989	.halt_reg = 0x4f058,
1990	.clkr = {
1991		.enable_reg = 0x4f058,
1992		.enable_mask = BIT(0),
1993		.hw.init = &(struct clk_init_data){
1994			.name = "gcc_camss_csi1pix_clk",
1995			.parent_names = (const char *[]){
1996				"csi1_clk_src",
1997			},
1998			.num_parents = 1,
1999			.flags = CLK_SET_RATE_PARENT,
2000			.ops = &clk_branch2_ops,
2001		},
2002	},
2003};
2004
2005static struct clk_branch gcc_camss_csi1rdi_clk = {
2006	.halt_reg = 0x4f050,
2007	.clkr = {
2008		.enable_reg = 0x4f050,
2009		.enable_mask = BIT(0),
2010		.hw.init = &(struct clk_init_data){
2011			.name = "gcc_camss_csi1rdi_clk",
2012			.parent_names = (const char *[]){
2013				"csi1_clk_src",
2014			},
2015			.num_parents = 1,
2016			.flags = CLK_SET_RATE_PARENT,
2017			.ops = &clk_branch2_ops,
2018		},
2019	},
2020};
2021
2022static struct clk_branch gcc_camss_csi_vfe0_clk = {
2023	.halt_reg = 0x58050,
2024	.clkr = {
2025		.enable_reg = 0x58050,
2026		.enable_mask = BIT(0),
2027		.hw.init = &(struct clk_init_data){
2028			.name = "gcc_camss_csi_vfe0_clk",
2029			.parent_names = (const char *[]){
2030				"vfe0_clk_src",
2031			},
2032			.num_parents = 1,
2033			.flags = CLK_SET_RATE_PARENT,
2034			.ops = &clk_branch2_ops,
2035		},
2036	},
2037};
2038
2039static struct clk_branch gcc_camss_gp0_clk = {
2040	.halt_reg = 0x54018,
2041	.clkr = {
2042		.enable_reg = 0x54018,
2043		.enable_mask = BIT(0),
2044		.hw.init = &(struct clk_init_data){
2045			.name = "gcc_camss_gp0_clk",
2046			.parent_names = (const char *[]){
2047				"camss_gp0_clk_src",
2048			},
2049			.num_parents = 1,
2050			.flags = CLK_SET_RATE_PARENT,
2051			.ops = &clk_branch2_ops,
2052		},
2053	},
2054};
2055
2056static struct clk_branch gcc_camss_gp1_clk = {
2057	.halt_reg = 0x55018,
2058	.clkr = {
2059		.enable_reg = 0x55018,
2060		.enable_mask = BIT(0),
2061		.hw.init = &(struct clk_init_data){
2062			.name = "gcc_camss_gp1_clk",
2063			.parent_names = (const char *[]){
2064				"camss_gp1_clk_src",
2065			},
2066			.num_parents = 1,
2067			.flags = CLK_SET_RATE_PARENT,
2068			.ops = &clk_branch2_ops,
2069		},
2070	},
2071};
2072
2073static struct clk_branch gcc_camss_ispif_ahb_clk = {
2074	.halt_reg = 0x50004,
2075	.clkr = {
2076		.enable_reg = 0x50004,
2077		.enable_mask = BIT(0),
2078		.hw.init = &(struct clk_init_data){
2079			.name = "gcc_camss_ispif_ahb_clk",
2080			.parent_names = (const char *[]){
2081				"camss_ahb_clk_src",
2082			},
2083			.num_parents = 1,
2084			.flags = CLK_SET_RATE_PARENT,
2085			.ops = &clk_branch2_ops,
2086		},
2087	},
2088};
2089
2090static struct clk_branch gcc_camss_jpeg0_clk = {
2091	.halt_reg = 0x57020,
2092	.clkr = {
2093		.enable_reg = 0x57020,
2094		.enable_mask = BIT(0),
2095		.hw.init = &(struct clk_init_data){
2096			.name = "gcc_camss_jpeg0_clk",
2097			.parent_names = (const char *[]){
2098				"jpeg0_clk_src",
2099			},
2100			.num_parents = 1,
2101			.flags = CLK_SET_RATE_PARENT,
2102			.ops = &clk_branch2_ops,
2103		},
2104	},
2105};
2106
2107static struct clk_branch gcc_camss_jpeg_ahb_clk = {
2108	.halt_reg = 0x57024,
2109	.clkr = {
2110		.enable_reg = 0x57024,
2111		.enable_mask = BIT(0),
2112		.hw.init = &(struct clk_init_data){
2113			.name = "gcc_camss_jpeg_ahb_clk",
2114			.parent_names = (const char *[]){
2115				"camss_ahb_clk_src",
2116			},
2117			.num_parents = 1,
2118			.flags = CLK_SET_RATE_PARENT,
2119			.ops = &clk_branch2_ops,
2120		},
2121	},
2122};
2123
2124static struct clk_branch gcc_camss_jpeg_axi_clk = {
2125	.halt_reg = 0x57028,
2126	.clkr = {
2127		.enable_reg = 0x57028,
2128		.enable_mask = BIT(0),
2129		.hw.init = &(struct clk_init_data){
2130			.name = "gcc_camss_jpeg_axi_clk",
2131			.parent_names = (const char *[]){
2132				"system_noc_bfdcd_clk_src",
2133			},
2134			.num_parents = 1,
2135			.flags = CLK_SET_RATE_PARENT,
2136			.ops = &clk_branch2_ops,
2137		},
2138	},
2139};
2140
2141static struct clk_branch gcc_camss_mclk0_clk = {
2142	.halt_reg = 0x52018,
2143	.clkr = {
2144		.enable_reg = 0x52018,
2145		.enable_mask = BIT(0),
2146		.hw.init = &(struct clk_init_data){
2147			.name = "gcc_camss_mclk0_clk",
2148			.parent_names = (const char *[]){
2149				"mclk0_clk_src",
2150			},
2151			.num_parents = 1,
2152			.flags = CLK_SET_RATE_PARENT,
2153			.ops = &clk_branch2_ops,
2154		},
2155	},
2156};
2157
2158static struct clk_branch gcc_camss_mclk1_clk = {
2159	.halt_reg = 0x53018,
2160	.clkr = {
2161		.enable_reg = 0x53018,
2162		.enable_mask = BIT(0),
2163		.hw.init = &(struct clk_init_data){
2164			.name = "gcc_camss_mclk1_clk",
2165			.parent_names = (const char *[]){
2166				"mclk1_clk_src",
2167			},
2168			.num_parents = 1,
2169			.flags = CLK_SET_RATE_PARENT,
2170			.ops = &clk_branch2_ops,
2171		},
2172	},
2173};
2174
2175static struct clk_branch gcc_camss_micro_ahb_clk = {
2176	.halt_reg = 0x5600c,
2177	.clkr = {
2178		.enable_reg = 0x5600c,
2179		.enable_mask = BIT(0),
2180		.hw.init = &(struct clk_init_data){
2181			.name = "gcc_camss_micro_ahb_clk",
2182			.parent_names = (const char *[]){
2183				"camss_ahb_clk_src",
2184			},
2185			.num_parents = 1,
2186			.flags = CLK_SET_RATE_PARENT,
2187			.ops = &clk_branch2_ops,
2188		},
2189	},
2190};
2191
2192static struct clk_branch gcc_camss_csi0phytimer_clk = {
2193	.halt_reg = 0x4e01c,
2194	.clkr = {
2195		.enable_reg = 0x4e01c,
2196		.enable_mask = BIT(0),
2197		.hw.init = &(struct clk_init_data){
2198			.name = "gcc_camss_csi0phytimer_clk",
2199			.parent_names = (const char *[]){
2200				"csi0phytimer_clk_src",
2201			},
2202			.num_parents = 1,
2203			.flags = CLK_SET_RATE_PARENT,
2204			.ops = &clk_branch2_ops,
2205		},
2206	},
2207};
2208
2209static struct clk_branch gcc_camss_csi1phytimer_clk = {
2210	.halt_reg = 0x4f01c,
2211	.clkr = {
2212		.enable_reg = 0x4f01c,
2213		.enable_mask = BIT(0),
2214		.hw.init = &(struct clk_init_data){
2215			.name = "gcc_camss_csi1phytimer_clk",
2216			.parent_names = (const char *[]){
2217				"csi1phytimer_clk_src",
2218			},
2219			.num_parents = 1,
2220			.flags = CLK_SET_RATE_PARENT,
2221			.ops = &clk_branch2_ops,
2222		},
2223	},
2224};
2225
2226static struct clk_branch gcc_camss_ahb_clk = {
2227	.halt_reg = 0x5a014,
2228	.clkr = {
2229		.enable_reg = 0x5a014,
2230		.enable_mask = BIT(0),
2231		.hw.init = &(struct clk_init_data){
2232			.name = "gcc_camss_ahb_clk",
2233			.parent_names = (const char *[]){
2234				"camss_ahb_clk_src",
2235			},
2236			.num_parents = 1,
2237			.flags = CLK_SET_RATE_PARENT,
2238			.ops = &clk_branch2_ops,
2239		},
2240	},
2241};
2242
2243static struct clk_branch gcc_camss_top_ahb_clk = {
2244	.halt_reg = 0x56004,
2245	.clkr = {
2246		.enable_reg = 0x56004,
2247		.enable_mask = BIT(0),
2248		.hw.init = &(struct clk_init_data){
2249			.name = "gcc_camss_top_ahb_clk",
2250			.parent_names = (const char *[]){
2251				"pcnoc_bfdcd_clk_src",
2252			},
2253			.num_parents = 1,
2254			.flags = CLK_SET_RATE_PARENT,
2255			.ops = &clk_branch2_ops,
2256		},
2257	},
2258};
2259
2260static struct clk_branch gcc_camss_cpp_ahb_clk = {
2261	.halt_reg = 0x58040,
2262	.clkr = {
2263		.enable_reg = 0x58040,
2264		.enable_mask = BIT(0),
2265		.hw.init = &(struct clk_init_data){
2266			.name = "gcc_camss_cpp_ahb_clk",
2267			.parent_names = (const char *[]){
2268				"camss_ahb_clk_src",
2269			},
2270			.num_parents = 1,
2271			.flags = CLK_SET_RATE_PARENT,
2272			.ops = &clk_branch2_ops,
2273		},
2274	},
2275};
2276
2277static struct clk_branch gcc_camss_cpp_clk = {
2278	.halt_reg = 0x5803c,
2279	.clkr = {
2280		.enable_reg = 0x5803c,
2281		.enable_mask = BIT(0),
2282		.hw.init = &(struct clk_init_data){
2283			.name = "gcc_camss_cpp_clk",
2284			.parent_names = (const char *[]){
2285				"cpp_clk_src",
2286			},
2287			.num_parents = 1,
2288			.flags = CLK_SET_RATE_PARENT,
2289			.ops = &clk_branch2_ops,
2290		},
2291	},
2292};
2293
2294static struct clk_branch gcc_camss_vfe0_clk = {
2295	.halt_reg = 0x58038,
2296	.clkr = {
2297		.enable_reg = 0x58038,
2298		.enable_mask = BIT(0),
2299		.hw.init = &(struct clk_init_data){
2300			.name = "gcc_camss_vfe0_clk",
2301			.parent_names = (const char *[]){
2302				"vfe0_clk_src",
2303			},
2304			.num_parents = 1,
2305			.flags = CLK_SET_RATE_PARENT,
2306			.ops = &clk_branch2_ops,
2307		},
2308	},
2309};
2310
2311static struct clk_branch gcc_camss_vfe_ahb_clk = {
2312	.halt_reg = 0x58044,
2313	.clkr = {
2314		.enable_reg = 0x58044,
2315		.enable_mask = BIT(0),
2316		.hw.init = &(struct clk_init_data){
2317			.name = "gcc_camss_vfe_ahb_clk",
2318			.parent_names = (const char *[]){
2319				"camss_ahb_clk_src",
2320			},
2321			.num_parents = 1,
2322			.flags = CLK_SET_RATE_PARENT,
2323			.ops = &clk_branch2_ops,
2324		},
2325	},
2326};
2327
2328static struct clk_branch gcc_camss_vfe_axi_clk = {
2329	.halt_reg = 0x58048,
2330	.clkr = {
2331		.enable_reg = 0x58048,
2332		.enable_mask = BIT(0),
2333		.hw.init = &(struct clk_init_data){
2334			.name = "gcc_camss_vfe_axi_clk",
2335			.parent_names = (const char *[]){
2336				"system_noc_bfdcd_clk_src",
2337			},
2338			.num_parents = 1,
2339			.flags = CLK_SET_RATE_PARENT,
2340			.ops = &clk_branch2_ops,
2341		},
2342	},
2343};
2344
2345static struct clk_branch gcc_crypto_ahb_clk = {
2346	.halt_reg = 0x16024,
2347	.halt_check = BRANCH_HALT_VOTED,
2348	.clkr = {
2349		.enable_reg = 0x45004,
2350		.enable_mask = BIT(0),
2351		.hw.init = &(struct clk_init_data){
2352			.name = "gcc_crypto_ahb_clk",
2353			.parent_names = (const char *[]){
2354				"pcnoc_bfdcd_clk_src",
2355			},
2356			.num_parents = 1,
2357			.flags = CLK_SET_RATE_PARENT,
2358			.ops = &clk_branch2_ops,
2359		},
2360	},
2361};
2362
2363static struct clk_branch gcc_crypto_axi_clk = {
2364	.halt_reg = 0x16020,
2365	.halt_check = BRANCH_HALT_VOTED,
2366	.clkr = {
2367		.enable_reg = 0x45004,
2368		.enable_mask = BIT(1),
2369		.hw.init = &(struct clk_init_data){
2370			.name = "gcc_crypto_axi_clk",
2371			.parent_names = (const char *[]){
2372				"pcnoc_bfdcd_clk_src",
2373			},
2374			.num_parents = 1,
2375			.flags = CLK_SET_RATE_PARENT,
2376			.ops = &clk_branch2_ops,
2377		},
2378	},
2379};
2380
2381static struct clk_branch gcc_crypto_clk = {
2382	.halt_reg = 0x1601c,
2383	.halt_check = BRANCH_HALT_VOTED,
2384	.clkr = {
2385		.enable_reg = 0x45004,
2386		.enable_mask = BIT(2),
2387		.hw.init = &(struct clk_init_data){
2388			.name = "gcc_crypto_clk",
2389			.parent_names = (const char *[]){
2390				"crypto_clk_src",
2391			},
2392			.num_parents = 1,
2393			.flags = CLK_SET_RATE_PARENT,
2394			.ops = &clk_branch2_ops,
2395		},
2396	},
2397};
2398
2399static struct clk_branch gcc_oxili_gmem_clk = {
2400	.halt_reg = 0x59024,
2401	.clkr = {
2402		.enable_reg = 0x59024,
2403		.enable_mask = BIT(0),
2404		.hw.init = &(struct clk_init_data){
2405			.name = "gcc_oxili_gmem_clk",
2406			.parent_names = (const char *[]){
2407				"gfx3d_clk_src",
2408			},
2409			.num_parents = 1,
2410			.flags = CLK_SET_RATE_PARENT,
2411			.ops = &clk_branch2_ops,
2412		},
2413	},
2414};
2415
2416static struct clk_branch gcc_gp1_clk = {
2417	.halt_reg = 0x08000,
2418	.clkr = {
2419		.enable_reg = 0x08000,
2420		.enable_mask = BIT(0),
2421		.hw.init = &(struct clk_init_data){
2422			.name = "gcc_gp1_clk",
2423			.parent_names = (const char *[]){
2424				"gp1_clk_src",
2425			},
2426			.num_parents = 1,
2427			.flags = CLK_SET_RATE_PARENT,
2428			.ops = &clk_branch2_ops,
2429		},
2430	},
2431};
2432
2433static struct clk_branch gcc_gp2_clk = {
2434	.halt_reg = 0x09000,
2435	.clkr = {
2436		.enable_reg = 0x09000,
2437		.enable_mask = BIT(0),
2438		.hw.init = &(struct clk_init_data){
2439			.name = "gcc_gp2_clk",
2440			.parent_names = (const char *[]){
2441				"gp2_clk_src",
2442			},
2443			.num_parents = 1,
2444			.flags = CLK_SET_RATE_PARENT,
2445			.ops = &clk_branch2_ops,
2446		},
2447	},
2448};
2449
2450static struct clk_branch gcc_gp3_clk = {
2451	.halt_reg = 0x0a000,
2452	.clkr = {
2453		.enable_reg = 0x0a000,
2454		.enable_mask = BIT(0),
2455		.hw.init = &(struct clk_init_data){
2456			.name = "gcc_gp3_clk",
2457			.parent_names = (const char *[]){
2458				"gp3_clk_src",
2459			},
2460			.num_parents = 1,
2461			.flags = CLK_SET_RATE_PARENT,
2462			.ops = &clk_branch2_ops,
2463		},
2464	},
2465};
2466
2467static struct clk_branch gcc_mdss_ahb_clk = {
2468	.halt_reg = 0x4d07c,
2469	.clkr = {
2470		.enable_reg = 0x4d07c,
2471		.enable_mask = BIT(0),
2472		.hw.init = &(struct clk_init_data){
2473			.name = "gcc_mdss_ahb_clk",
2474			.parent_names = (const char *[]){
2475				"pcnoc_bfdcd_clk_src",
2476			},
2477			.num_parents = 1,
2478			.flags = CLK_SET_RATE_PARENT,
2479			.ops = &clk_branch2_ops,
2480		},
2481	},
2482};
2483
2484static struct clk_branch gcc_mdss_axi_clk = {
2485	.halt_reg = 0x4d080,
2486	.clkr = {
2487		.enable_reg = 0x4d080,
2488		.enable_mask = BIT(0),
2489		.hw.init = &(struct clk_init_data){
2490			.name = "gcc_mdss_axi_clk",
2491			.parent_names = (const char *[]){
2492				"system_noc_bfdcd_clk_src",
2493			},
2494			.num_parents = 1,
2495			.flags = CLK_SET_RATE_PARENT,
2496			.ops = &clk_branch2_ops,
2497		},
2498	},
2499};
2500
2501static struct clk_branch gcc_mdss_byte0_clk = {
2502	.halt_reg = 0x4d094,
2503	.clkr = {
2504		.enable_reg = 0x4d094,
2505		.enable_mask = BIT(0),
2506		.hw.init = &(struct clk_init_data){
2507			.name = "gcc_mdss_byte0_clk",
2508			.parent_names = (const char *[]){
2509				"byte0_clk_src",
2510			},
2511			.num_parents = 1,
2512			.flags = CLK_SET_RATE_PARENT,
2513			.ops = &clk_branch2_ops,
2514		},
2515	},
2516};
2517
2518static struct clk_branch gcc_mdss_esc0_clk = {
2519	.halt_reg = 0x4d098,
2520	.clkr = {
2521		.enable_reg = 0x4d098,
2522		.enable_mask = BIT(0),
2523		.hw.init = &(struct clk_init_data){
2524			.name = "gcc_mdss_esc0_clk",
2525			.parent_names = (const char *[]){
2526				"esc0_clk_src",
2527			},
2528			.num_parents = 1,
2529			.flags = CLK_SET_RATE_PARENT,
2530			.ops = &clk_branch2_ops,
2531		},
2532	},
2533};
2534
2535static struct clk_branch gcc_mdss_mdp_clk = {
2536	.halt_reg = 0x4D088,
2537	.clkr = {
2538		.enable_reg = 0x4D088,
2539		.enable_mask = BIT(0),
2540		.hw.init = &(struct clk_init_data){
2541			.name = "gcc_mdss_mdp_clk",
2542			.parent_names = (const char *[]){
2543				"mdp_clk_src",
2544			},
2545			.num_parents = 1,
2546			.flags = CLK_SET_RATE_PARENT,
2547			.ops = &clk_branch2_ops,
2548		},
2549	},
2550};
2551
2552static struct clk_branch gcc_mdss_pclk0_clk = {
2553	.halt_reg = 0x4d084,
2554	.clkr = {
2555		.enable_reg = 0x4d084,
2556		.enable_mask = BIT(0),
2557		.hw.init = &(struct clk_init_data){
2558			.name = "gcc_mdss_pclk0_clk",
2559			.parent_names = (const char *[]){
2560				"pclk0_clk_src",
2561			},
2562			.num_parents = 1,
2563			.flags = CLK_SET_RATE_PARENT,
2564			.ops = &clk_branch2_ops,
2565		},
2566	},
2567};
2568
2569static struct clk_branch gcc_mdss_vsync_clk = {
2570	.halt_reg = 0x4d090,
2571	.clkr = {
2572		.enable_reg = 0x4d090,
2573		.enable_mask = BIT(0),
2574		.hw.init = &(struct clk_init_data){
2575			.name = "gcc_mdss_vsync_clk",
2576			.parent_names = (const char *[]){
2577				"vsync_clk_src",
2578			},
2579			.num_parents = 1,
2580			.flags = CLK_SET_RATE_PARENT,
2581			.ops = &clk_branch2_ops,
2582		},
2583	},
2584};
2585
2586static struct clk_branch gcc_mss_cfg_ahb_clk = {
2587	.halt_reg = 0x49000,
2588	.clkr = {
2589		.enable_reg = 0x49000,
2590		.enable_mask = BIT(0),
2591		.hw.init = &(struct clk_init_data){
2592			.name = "gcc_mss_cfg_ahb_clk",
2593			.parent_names = (const char *[]){
2594				"pcnoc_bfdcd_clk_src",
2595			},
2596			.num_parents = 1,
2597			.flags = CLK_SET_RATE_PARENT,
2598			.ops = &clk_branch2_ops,
2599		},
2600	},
2601};
2602
2603static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
2604	.halt_reg = 0x49004,
2605	.clkr = {
2606		.enable_reg = 0x49004,
2607		.enable_mask = BIT(0),
2608		.hw.init = &(struct clk_init_data){
2609			.name = "gcc_mss_q6_bimc_axi_clk",
2610			.parent_names = (const char *[]){
2611				"bimc_ddr_clk_src",
2612			},
2613			.num_parents = 1,
2614			.flags = CLK_SET_RATE_PARENT,
2615			.ops = &clk_branch2_ops,
2616		},
2617	},
2618};
2619
2620static struct clk_branch gcc_oxili_ahb_clk = {
2621	.halt_reg = 0x59028,
2622	.clkr = {
2623		.enable_reg = 0x59028,
2624		.enable_mask = BIT(0),
2625		.hw.init = &(struct clk_init_data){
2626			.name = "gcc_oxili_ahb_clk",
2627			.parent_names = (const char *[]){
2628				"pcnoc_bfdcd_clk_src",
2629			},
2630			.num_parents = 1,
2631			.flags = CLK_SET_RATE_PARENT,
2632			.ops = &clk_branch2_ops,
2633		},
2634	},
2635};
2636
2637static struct clk_branch gcc_oxili_gfx3d_clk = {
2638	.halt_reg = 0x59020,
2639	.clkr = {
2640		.enable_reg = 0x59020,
2641		.enable_mask = BIT(0),
2642		.hw.init = &(struct clk_init_data){
2643			.name = "gcc_oxili_gfx3d_clk",
2644			.parent_names = (const char *[]){
2645				"gfx3d_clk_src",
2646			},
2647			.num_parents = 1,
2648			.flags = CLK_SET_RATE_PARENT,
2649			.ops = &clk_branch2_ops,
2650		},
2651	},
2652};
2653
2654static struct clk_branch gcc_pdm2_clk = {
2655	.halt_reg = 0x4400c,
2656	.clkr = {
2657		.enable_reg = 0x4400c,
2658		.enable_mask = BIT(0),
2659		.hw.init = &(struct clk_init_data){
2660			.name = "gcc_pdm2_clk",
2661			.parent_names = (const char *[]){
2662				"pdm2_clk_src",
2663			},
2664			.num_parents = 1,
2665			.flags = CLK_SET_RATE_PARENT,
2666			.ops = &clk_branch2_ops,
2667		},
2668	},
2669};
2670
2671static struct clk_branch gcc_pdm_ahb_clk = {
2672	.halt_reg = 0x44004,
2673	.clkr = {
2674		.enable_reg = 0x44004,
2675		.enable_mask = BIT(0),
2676		.hw.init = &(struct clk_init_data){
2677			.name = "gcc_pdm_ahb_clk",
2678			.parent_names = (const char *[]){
2679				"pcnoc_bfdcd_clk_src",
2680			},
2681			.num_parents = 1,
2682			.flags = CLK_SET_RATE_PARENT,
2683			.ops = &clk_branch2_ops,
2684		},
2685	},
2686};
2687
2688static struct clk_branch gcc_prng_ahb_clk = {
2689	.halt_reg = 0x13004,
2690	.halt_check = BRANCH_HALT_VOTED,
2691	.clkr = {
2692		.enable_reg = 0x45004,
2693		.enable_mask = BIT(8),
2694		.hw.init = &(struct clk_init_data){
2695			.name = "gcc_prng_ahb_clk",
2696			.parent_names = (const char *[]){
2697				"pcnoc_bfdcd_clk_src",
2698			},
2699			.num_parents = 1,
2700			.ops = &clk_branch2_ops,
2701		},
2702	},
2703};
2704
2705static struct clk_branch gcc_sdcc1_ahb_clk = {
2706	.halt_reg = 0x4201c,
2707	.clkr = {
2708		.enable_reg = 0x4201c,
2709		.enable_mask = BIT(0),
2710		.hw.init = &(struct clk_init_data){
2711			.name = "gcc_sdcc1_ahb_clk",
2712			.parent_names = (const char *[]){
2713				"pcnoc_bfdcd_clk_src",
2714			},
2715			.num_parents = 1,
2716			.flags = CLK_SET_RATE_PARENT,
2717			.ops = &clk_branch2_ops,
2718		},
2719	},
2720};
2721
2722static struct clk_branch gcc_sdcc1_apps_clk = {
2723	.halt_reg = 0x42018,
2724	.clkr = {
2725		.enable_reg = 0x42018,
2726		.enable_mask = BIT(0),
2727		.hw.init = &(struct clk_init_data){
2728			.name = "gcc_sdcc1_apps_clk",
2729			.parent_names = (const char *[]){
2730				"sdcc1_apps_clk_src",
2731			},
2732			.num_parents = 1,
2733			.flags = CLK_SET_RATE_PARENT,
2734			.ops = &clk_branch2_ops,
2735		},
2736	},
2737};
2738
2739static struct clk_branch gcc_sdcc2_ahb_clk = {
2740	.halt_reg = 0x4301c,
2741	.clkr = {
2742		.enable_reg = 0x4301c,
2743		.enable_mask = BIT(0),
2744		.hw.init = &(struct clk_init_data){
2745			.name = "gcc_sdcc2_ahb_clk",
2746			.parent_names = (const char *[]){
2747				"pcnoc_bfdcd_clk_src",
2748			},
2749			.num_parents = 1,
2750			.flags = CLK_SET_RATE_PARENT,
2751			.ops = &clk_branch2_ops,
2752		},
2753	},
2754};
2755
2756static struct clk_branch gcc_sdcc2_apps_clk = {
2757	.halt_reg = 0x43018,
2758	.clkr = {
2759		.enable_reg = 0x43018,
2760		.enable_mask = BIT(0),
2761		.hw.init = &(struct clk_init_data){
2762			.name = "gcc_sdcc2_apps_clk",
2763			.parent_names = (const char *[]){
2764				"sdcc2_apps_clk_src",
2765			},
2766			.num_parents = 1,
2767			.flags = CLK_SET_RATE_PARENT,
2768			.ops = &clk_branch2_ops,
2769		},
2770	},
2771};
2772
2773static struct clk_rcg2 bimc_ddr_clk_src = {
2774	.cmd_rcgr = 0x32004,
2775	.hid_width = 5,
2776	.parent_map = gcc_xo_gpll0_bimc_map,
2777	.clkr.hw.init = &(struct clk_init_data){
2778		.name = "bimc_ddr_clk_src",
2779		.parent_names = gcc_xo_gpll0_bimc,
2780		.num_parents = 3,
2781		.ops = &clk_rcg2_ops,
2782		.flags = CLK_GET_RATE_NOCACHE,
2783	},
2784};
2785
2786static struct clk_branch gcc_apss_tcu_clk = {
2787	.halt_reg = 0x12018,
2788	.clkr = {
2789		.enable_reg = 0x4500c,
2790		.enable_mask = BIT(1),
2791		.hw.init = &(struct clk_init_data){
2792			.name = "gcc_apss_tcu_clk",
2793			.parent_names = (const char *[]){
2794				"bimc_ddr_clk_src",
2795			},
2796			.num_parents = 1,
2797			.ops = &clk_branch2_ops,
2798		},
2799	},
2800};
2801
2802static struct clk_branch gcc_gfx_tcu_clk = {
2803	.halt_reg = 0x12020,
2804	.clkr = {
2805		.enable_reg = 0x4500c,
2806		.enable_mask = BIT(2),
2807		.hw.init = &(struct clk_init_data){
2808			.name = "gcc_gfx_tcu_clk",
2809			.parent_names = (const char *[]){
2810				"bimc_ddr_clk_src",
2811			},
2812			.num_parents = 1,
2813			.ops = &clk_branch2_ops,
2814		},
2815	},
2816};
2817
2818static struct clk_branch gcc_gtcu_ahb_clk = {
2819	.halt_reg = 0x12044,
2820	.clkr = {
2821		.enable_reg = 0x4500c,
2822		.enable_mask = BIT(13),
2823		.hw.init = &(struct clk_init_data){
2824			.name = "gcc_gtcu_ahb_clk",
2825			.parent_names = (const char *[]){
2826				"pcnoc_bfdcd_clk_src",
2827			},
2828			.num_parents = 1,
2829			.flags = CLK_SET_RATE_PARENT,
2830			.ops = &clk_branch2_ops,
2831		},
2832	},
2833};
2834
2835static struct clk_branch gcc_bimc_gfx_clk = {
2836	.halt_reg = 0x31024,
2837	.clkr = {
2838		.enable_reg = 0x31024,
2839		.enable_mask = BIT(0),
2840		.hw.init = &(struct clk_init_data){
2841			.name = "gcc_bimc_gfx_clk",
2842			.parent_names = (const char *[]){
2843				"bimc_gpu_clk_src",
2844			},
2845			.num_parents = 1,
2846			.flags = CLK_SET_RATE_PARENT,
2847			.ops = &clk_branch2_ops,
2848		},
2849	},
2850};
2851
2852static struct clk_branch gcc_bimc_gpu_clk = {
2853	.halt_reg = 0x31040,
2854	.clkr = {
2855		.enable_reg = 0x31040,
2856		.enable_mask = BIT(0),
2857		.hw.init = &(struct clk_init_data){
2858			.name = "gcc_bimc_gpu_clk",
2859			.parent_names = (const char *[]){
2860				"bimc_gpu_clk_src",
2861			},
2862			.num_parents = 1,
2863			.flags = CLK_SET_RATE_PARENT,
2864			.ops = &clk_branch2_ops,
2865		},
2866	},
2867};
2868
2869static struct clk_branch gcc_jpeg_tbu_clk = {
2870	.halt_reg = 0x12034,
2871	.clkr = {
2872		.enable_reg = 0x4500c,
2873		.enable_mask = BIT(10),
2874		.hw.init = &(struct clk_init_data){
2875			.name = "gcc_jpeg_tbu_clk",
2876			.parent_names = (const char *[]){
2877				"system_noc_bfdcd_clk_src",
2878			},
2879			.num_parents = 1,
2880			.flags = CLK_SET_RATE_PARENT,
2881			.ops = &clk_branch2_ops,
2882		},
2883	},
2884};
2885
2886static struct clk_branch gcc_mdp_tbu_clk = {
2887	.halt_reg = 0x1201c,
2888	.clkr = {
2889		.enable_reg = 0x4500c,
2890		.enable_mask = BIT(4),
2891		.hw.init = &(struct clk_init_data){
2892			.name = "gcc_mdp_tbu_clk",
2893			.parent_names = (const char *[]){
2894				"system_noc_bfdcd_clk_src",
2895			},
2896			.num_parents = 1,
2897			.flags = CLK_SET_RATE_PARENT,
2898			.ops = &clk_branch2_ops,
2899		},
2900	},
2901};
2902
2903static struct clk_branch gcc_smmu_cfg_clk = {
2904	.halt_reg = 0x12038,
2905	.clkr = {
2906		.enable_reg = 0x4500c,
2907		.enable_mask = BIT(12),
2908		.hw.init = &(struct clk_init_data){
2909			.name = "gcc_smmu_cfg_clk",
2910			.parent_names = (const char *[]){
2911				"pcnoc_bfdcd_clk_src",
2912			},
2913			.num_parents = 1,
2914			.flags = CLK_SET_RATE_PARENT,
2915			.ops = &clk_branch2_ops,
2916		},
2917	},
2918};
2919
2920static struct clk_branch gcc_venus_tbu_clk = {
2921	.halt_reg = 0x12014,
2922	.clkr = {
2923		.enable_reg = 0x4500c,
2924		.enable_mask = BIT(5),
2925		.hw.init = &(struct clk_init_data){
2926			.name = "gcc_venus_tbu_clk",
2927			.parent_names = (const char *[]){
2928				"system_noc_bfdcd_clk_src",
2929			},
2930			.num_parents = 1,
2931			.flags = CLK_SET_RATE_PARENT,
2932			.ops = &clk_branch2_ops,
2933		},
2934	},
2935};
2936
2937static struct clk_branch gcc_vfe_tbu_clk = {
2938	.halt_reg = 0x1203c,
2939	.clkr = {
2940		.enable_reg = 0x4500c,
2941		.enable_mask = BIT(9),
2942		.hw.init = &(struct clk_init_data){
2943			.name = "gcc_vfe_tbu_clk",
2944			.parent_names = (const char *[]){
2945				"system_noc_bfdcd_clk_src",
2946			},
2947			.num_parents = 1,
2948			.flags = CLK_SET_RATE_PARENT,
2949			.ops = &clk_branch2_ops,
2950		},
2951	},
2952};
2953
2954static struct clk_branch gcc_usb2a_phy_sleep_clk = {
2955	.halt_reg = 0x4102c,
2956	.clkr = {
2957		.enable_reg = 0x4102c,
2958		.enable_mask = BIT(0),
2959		.hw.init = &(struct clk_init_data){
2960			.name = "gcc_usb2a_phy_sleep_clk",
2961			.parent_names = (const char *[]){
2962				"sleep_clk_src",
2963			},
2964			.num_parents = 1,
2965			.flags = CLK_SET_RATE_PARENT,
2966			.ops = &clk_branch2_ops,
2967		},
2968	},
2969};
2970
2971static struct clk_branch gcc_usb_hs_ahb_clk = {
2972	.halt_reg = 0x41008,
2973	.clkr = {
2974		.enable_reg = 0x41008,
2975		.enable_mask = BIT(0),
2976		.hw.init = &(struct clk_init_data){
2977			.name = "gcc_usb_hs_ahb_clk",
2978			.parent_names = (const char *[]){
2979				"pcnoc_bfdcd_clk_src",
2980			},
2981			.num_parents = 1,
2982			.flags = CLK_SET_RATE_PARENT,
2983			.ops = &clk_branch2_ops,
2984		},
2985	},
2986};
2987
2988static struct clk_branch gcc_usb_hs_system_clk = {
2989	.halt_reg = 0x41004,
2990	.clkr = {
2991		.enable_reg = 0x41004,
2992		.enable_mask = BIT(0),
2993		.hw.init = &(struct clk_init_data){
2994			.name = "gcc_usb_hs_system_clk",
2995			.parent_names = (const char *[]){
2996				"usb_hs_system_clk_src",
2997			},
2998			.num_parents = 1,
2999			.flags = CLK_SET_RATE_PARENT,
3000			.ops = &clk_branch2_ops,
3001		},
3002	},
3003};
3004
3005static struct clk_branch gcc_venus0_ahb_clk = {
3006	.halt_reg = 0x4c020,
3007	.clkr = {
3008		.enable_reg = 0x4c020,
3009		.enable_mask = BIT(0),
3010		.hw.init = &(struct clk_init_data){
3011			.name = "gcc_venus0_ahb_clk",
3012			.parent_names = (const char *[]){
3013				"pcnoc_bfdcd_clk_src",
3014			},
3015			.num_parents = 1,
3016			.flags = CLK_SET_RATE_PARENT,
3017			.ops = &clk_branch2_ops,
3018		},
3019	},
3020};
3021
3022static struct clk_branch gcc_venus0_axi_clk = {
3023	.halt_reg = 0x4c024,
3024	.clkr = {
3025		.enable_reg = 0x4c024,
3026		.enable_mask = BIT(0),
3027		.hw.init = &(struct clk_init_data){
3028			.name = "gcc_venus0_axi_clk",
3029			.parent_names = (const char *[]){
3030				"system_noc_bfdcd_clk_src",
3031			},
3032			.num_parents = 1,
3033			.flags = CLK_SET_RATE_PARENT,
3034			.ops = &clk_branch2_ops,
3035		},
3036	},
3037};
3038
3039static struct clk_branch gcc_venus0_vcodec0_clk = {
3040	.halt_reg = 0x4c01c,
3041	.clkr = {
3042		.enable_reg = 0x4c01c,
3043		.enable_mask = BIT(0),
3044		.hw.init = &(struct clk_init_data){
3045			.name = "gcc_venus0_vcodec0_clk",
3046			.parent_names = (const char *[]){
3047				"vcodec0_clk_src",
3048			},
3049			.num_parents = 1,
3050			.flags = CLK_SET_RATE_PARENT,
3051			.ops = &clk_branch2_ops,
3052		},
3053	},
3054};
3055
3056static struct gdsc venus_gdsc = {
3057	.gdscr = 0x4c018,
3058	.pd = {
3059		.name = "venus",
3060	},
3061	.pwrsts = PWRSTS_OFF_ON,
3062};
3063
3064static struct gdsc mdss_gdsc = {
3065	.gdscr = 0x4d078,
3066	.pd = {
3067		.name = "mdss",
3068	},
3069	.pwrsts = PWRSTS_OFF_ON,
3070};
3071
3072static struct gdsc jpeg_gdsc = {
3073	.gdscr = 0x5701c,
3074	.pd = {
3075		.name = "jpeg",
3076	},
3077	.pwrsts = PWRSTS_OFF_ON,
3078};
3079
3080static struct gdsc vfe_gdsc = {
3081	.gdscr = 0x58034,
3082	.pd = {
3083		.name = "vfe",
3084	},
3085	.pwrsts = PWRSTS_OFF_ON,
3086};
3087
3088static struct gdsc oxili_gdsc = {
3089	.gdscr = 0x5901c,
3090	.pd = {
3091		.name = "oxili",
3092	},
3093	.pwrsts = PWRSTS_OFF_ON,
3094};
3095
3096static struct clk_regmap *gcc_msm8916_clocks[] = {
3097	[GPLL0] = &gpll0.clkr,
3098	[GPLL0_VOTE] = &gpll0_vote,
3099	[BIMC_PLL] = &bimc_pll.clkr,
3100	[BIMC_PLL_VOTE] = &bimc_pll_vote,
3101	[GPLL1] = &gpll1.clkr,
3102	[GPLL1_VOTE] = &gpll1_vote,
3103	[GPLL2] = &gpll2.clkr,
3104	[GPLL2_VOTE] = &gpll2_vote,
3105	[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
3106	[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
3107	[CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr,
3108	[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
3109	[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3110	[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3111	[GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3112	[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3113	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3114	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3115	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3116	[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3117	[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3118	[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3119	[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3120	[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3121	[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3122	[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3123	[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3124	[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3125	[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3126	[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3127	[CCI_CLK_SRC] = &cci_clk_src.clkr,
3128	[CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3129	[CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3130	[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3131	[MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3132	[MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3133	[CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3134	[CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3135	[CPP_CLK_SRC] = &cpp_clk_src.clkr,
3136	[CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
3137	[GP1_CLK_SRC] = &gp1_clk_src.clkr,
3138	[GP2_CLK_SRC] = &gp2_clk_src.clkr,
3139	[GP3_CLK_SRC] = &gp3_clk_src.clkr,
3140	[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3141	[ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3142	[MDP_CLK_SRC] = &mdp_clk_src.clkr,
3143	[PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3144	[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3145	[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3146	[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3147	[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3148	[APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr,
3149	[USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
3150	[VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3151	[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3152	[GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
3153	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3154	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3155	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3156	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3157	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3158	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3159	[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3160	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3161	[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3162	[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3163	[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3164	[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3165	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3166	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3167	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3168	[GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
3169	[GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
3170	[GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
3171	[GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
3172	[GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
3173	[GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
3174	[GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
3175	[GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
3176	[GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
3177	[GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
3178	[GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
3179	[GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
3180	[GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
3181	[GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
3182	[GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
3183	[GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
3184	[GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
3185	[GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
3186	[GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
3187	[GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
3188	[GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
3189	[GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
3190	[GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
3191	[GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
3192	[GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
3193	[GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
3194	[GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
3195	[GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
3196	[GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
3197	[GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr,
3198	[GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr,
3199	[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
3200	[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
3201	[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
3202	[GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr,
3203	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3204	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3205	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3206	[GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
3207	[GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
3208	[GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
3209	[GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
3210	[GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
3211	[GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
3212	[GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
3213	[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3214	[GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
3215	[GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
3216	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3217	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3218	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3219	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3220	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3221	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3222	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3223	[GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
3224	[GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
3225	[GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
3226	[GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
3227	[GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
3228	[GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
3229	[GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
3230	[GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
3231	[GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
3232	[GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
3233	[GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
3234	[GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
3235	[BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr,
3236	[GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
3237	[GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
3238	[BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr,
3239	[GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
3240	[GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
3241	[ULTAUDIO_AHBFABRIC_CLK_SRC] = &ultaudio_ahbfabric_clk_src.clkr,
3242	[ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC] = &ultaudio_lpaif_pri_i2s_clk_src.clkr,
3243	[ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC] = &ultaudio_lpaif_sec_i2s_clk_src.clkr,
3244	[ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC] = &ultaudio_lpaif_aux_i2s_clk_src.clkr,
3245	[ULTAUDIO_XO_CLK_SRC] = &ultaudio_xo_clk_src.clkr,
3246	[CODEC_DIGCODEC_CLK_SRC] = &codec_digcodec_clk_src.clkr,
3247	[GCC_ULTAUDIO_PCNOC_MPORT_CLK] = &gcc_ultaudio_pcnoc_mport_clk.clkr,
3248	[GCC_ULTAUDIO_PCNOC_SWAY_CLK] = &gcc_ultaudio_pcnoc_sway_clk.clkr,
3249	[GCC_ULTAUDIO_AVSYNC_XO_CLK] = &gcc_ultaudio_avsync_xo_clk.clkr,
3250	[GCC_ULTAUDIO_STC_XO_CLK] = &gcc_ultaudio_stc_xo_clk.clkr,
3251	[GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK] =	&gcc_ultaudio_ahbfabric_ixfabric_clk.clkr,
3252	[GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_lpm_clk.clkr,
3253	[GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK] = &gcc_ultaudio_lpaif_pri_i2s_clk.clkr,
3254	[GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK] = &gcc_ultaudio_lpaif_sec_i2s_clk.clkr,
3255	[GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK] = &gcc_ultaudio_lpaif_aux_i2s_clk.clkr,
3256	[GCC_CODEC_DIGCODEC_CLK] = &gcc_codec_digcodec_clk.clkr,
3257	[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
3258};
3259
3260static struct gdsc *gcc_msm8916_gdscs[] = {
3261	[VENUS_GDSC] = &venus_gdsc,
3262	[MDSS_GDSC] = &mdss_gdsc,
3263	[JPEG_GDSC] = &jpeg_gdsc,
3264	[VFE_GDSC] = &vfe_gdsc,
3265	[OXILI_GDSC] = &oxili_gdsc,
3266};
3267
3268static const struct qcom_reset_map gcc_msm8916_resets[] = {
3269	[GCC_BLSP1_BCR] = { 0x01000 },
3270	[GCC_BLSP1_QUP1_BCR] = { 0x02000 },
3271	[GCC_BLSP1_UART1_BCR] = { 0x02038 },
3272	[GCC_BLSP1_QUP2_BCR] = { 0x03008 },
3273	[GCC_BLSP1_UART2_BCR] = { 0x03028 },
3274	[GCC_BLSP1_QUP3_BCR] = { 0x04018 },
3275	[GCC_BLSP1_QUP4_BCR] = { 0x05018 },
3276	[GCC_BLSP1_QUP5_BCR] = { 0x06018 },
3277	[GCC_BLSP1_QUP6_BCR] = { 0x07018 },
3278	[GCC_IMEM_BCR] = { 0x0e000 },
3279	[GCC_SMMU_BCR] = { 0x12000 },
3280	[GCC_APSS_TCU_BCR] = { 0x12050 },
3281	[GCC_SMMU_XPU_BCR] = { 0x12054 },
3282	[GCC_PCNOC_TBU_BCR] = { 0x12058 },
3283	[GCC_PRNG_BCR] = { 0x13000 },
3284	[GCC_BOOT_ROM_BCR] = { 0x13008 },
3285	[GCC_CRYPTO_BCR] = { 0x16000 },
3286	[GCC_SEC_CTRL_BCR] = { 0x1a000 },
3287	[GCC_AUDIO_CORE_BCR] = { 0x1c008 },
3288	[GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
3289	[GCC_DEHR_BCR] = { 0x1f000 },
3290	[GCC_SYSTEM_NOC_BCR] = { 0x26000 },
3291	[GCC_PCNOC_BCR] = { 0x27018 },
3292	[GCC_TCSR_BCR] = { 0x28000 },
3293	[GCC_QDSS_BCR] = { 0x29000 },
3294	[GCC_DCD_BCR] = { 0x2a000 },
3295	[GCC_MSG_RAM_BCR] = { 0x2b000 },
3296	[GCC_MPM_BCR] = { 0x2c000 },
3297	[GCC_SPMI_BCR] = { 0x2e000 },
3298	[GCC_SPDM_BCR] = { 0x2f000 },
3299	[GCC_MM_SPDM_BCR] = { 0x2f024 },
3300	[GCC_BIMC_BCR] = { 0x31000 },
3301	[GCC_RBCPR_BCR] = { 0x33000 },
3302	[GCC_TLMM_BCR] = { 0x34000 },
3303	[GCC_USB_HS_BCR] = { 0x41000 },
3304	[GCC_USB2A_PHY_BCR] = { 0x41028 },
3305	[GCC_SDCC1_BCR] = { 0x42000 },
3306	[GCC_SDCC2_BCR] = { 0x43000 },
3307	[GCC_PDM_BCR] = { 0x44000 },
3308	[GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
3309	[GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
3310	[GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
3311	[GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
3312	[GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
3313	[GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
3314	[GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
3315	[GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
3316	[GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
3317	[GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
3318	[GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
3319	[GCC_MMSS_BCR] = { 0x4b000 },
3320	[GCC_VENUS0_BCR] = { 0x4c014 },
3321	[GCC_MDSS_BCR] = { 0x4d074 },
3322	[GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
3323	[GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
3324	[GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
3325	[GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
3326	[GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
3327	[GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
3328	[GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
3329	[GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
3330	[GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
3331	[GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
3332	[GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
3333	[GCC_CAMSS_CCI_BCR] = { 0x51014 },
3334	[GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
3335	[GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
3336	[GCC_CAMSS_GP0_BCR] = { 0x54014 },
3337	[GCC_CAMSS_GP1_BCR] = { 0x55014 },
3338	[GCC_CAMSS_TOP_BCR] = { 0x56000 },
3339	[GCC_CAMSS_MICRO_BCR] = { 0x56008 },
3340	[GCC_CAMSS_JPEG_BCR] = { 0x57018 },
3341	[GCC_CAMSS_VFE_BCR] = { 0x58030 },
3342	[GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
3343	[GCC_OXILI_BCR] = { 0x59018 },
3344	[GCC_GMEM_BCR] = { 0x5902c },
3345	[GCC_CAMSS_AHB_BCR] = { 0x5a018 },
3346	[GCC_MDP_TBU_BCR] = { 0x62000 },
3347	[GCC_GFX_TBU_BCR] = { 0x63000 },
3348	[GCC_GFX_TCU_BCR] = { 0x64000 },
3349	[GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
3350	[GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
3351	[GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
3352	[GCC_GTCU_AHB_BCR] = { 0x68000 },
3353	[GCC_SMMU_CFG_BCR] = { 0x69000 },
3354	[GCC_VFE_TBU_BCR] = { 0x6a000 },
3355	[GCC_VENUS_TBU_BCR] = { 0x6b000 },
3356	[GCC_JPEG_TBU_BCR] = { 0x6c000 },
3357	[GCC_PRONTO_TBU_BCR] = { 0x6d000 },
3358	[GCC_SMMU_CATS_BCR] = { 0x7c000 },
3359};
3360
3361static const struct regmap_config gcc_msm8916_regmap_config = {
3362	.reg_bits	= 32,
3363	.reg_stride	= 4,
3364	.val_bits	= 32,
3365	.max_register	= 0x80000,
3366	.fast_io	= true,
3367};
3368
3369static const struct qcom_cc_desc gcc_msm8916_desc = {
3370	.config = &gcc_msm8916_regmap_config,
3371	.clks = gcc_msm8916_clocks,
3372	.num_clks = ARRAY_SIZE(gcc_msm8916_clocks),
3373	.resets = gcc_msm8916_resets,
3374	.num_resets = ARRAY_SIZE(gcc_msm8916_resets),
3375	.gdscs = gcc_msm8916_gdscs,
3376	.num_gdscs = ARRAY_SIZE(gcc_msm8916_gdscs),
3377};
3378
3379static const struct of_device_id gcc_msm8916_match_table[] = {
3380	{ .compatible = "qcom,gcc-msm8916" },
3381	{ }
3382};
3383MODULE_DEVICE_TABLE(of, gcc_msm8916_match_table);
3384
3385static int gcc_msm8916_probe(struct platform_device *pdev)
3386{
3387	int ret;
3388	struct device *dev = &pdev->dev;
3389
3390	ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000);
3391	if (ret)
3392		return ret;
3393
3394	ret = qcom_cc_register_sleep_clk(dev);
3395	if (ret)
3396		return ret;
3397
3398	return qcom_cc_probe(pdev, &gcc_msm8916_desc);
3399}
3400
3401static struct platform_driver gcc_msm8916_driver = {
3402	.probe		= gcc_msm8916_probe,
3403	.driver		= {
3404		.name	= "gcc-msm8916",
3405		.of_match_table = gcc_msm8916_match_table,
3406	},
3407};
3408
3409static int __init gcc_msm8916_init(void)
3410{
3411	return platform_driver_register(&gcc_msm8916_driver);
3412}
3413core_initcall(gcc_msm8916_init);
3414
3415static void __exit gcc_msm8916_exit(void)
3416{
3417	platform_driver_unregister(&gcc_msm8916_driver);
3418}
3419module_exit(gcc_msm8916_exit);
3420
3421MODULE_DESCRIPTION("Qualcomm GCC MSM8916 Driver");
3422MODULE_LICENSE("GPL v2");
3423MODULE_ALIAS("platform:gcc-msm8916");