1/*
  2 * 'traps.c' handles hardware traps and faults after we have saved some
  3 * state in 'entry.S'.
  4 *
  5 *  SuperH version: Copyright (C) 1999 Niibe Yutaka
  6 *                  Copyright (C) 2000 Philipp Rumpf
  7 *                  Copyright (C) 2000 David Howells
  8 *                  Copyright (C) 2002 - 2010 Paul Mundt
  9 *
 10 * This file is subject to the terms and conditions of the GNU General Public
 11 * License.  See the file "COPYING" in the main directory of this archive
 12 * for more details.
 13 */
 14#include <linux/kernel.h>
 15#include <linux/ptrace.h>
 16#include <linux/hardirq.h>
 17#include <linux/init.h>
 18#include <linux/spinlock.h>
 19#include <linux/module.h>
 20#include <linux/kallsyms.h>
 21#include <linux/io.h>
 22#include <linux/bug.h>
 23#include <linux/debug_locks.h>
 24#include <linux/kdebug.h>
 25#include <linux/kexec.h>
 26#include <linux/limits.h>
 27#include <linux/sysfs.h>
 28#include <linux/uaccess.h>
 29#include <linux/perf_event.h>
 
 
 30#include <asm/alignment.h>
 31#include <asm/fpu.h>
 32#include <asm/kprobes.h>
 33#include <asm/traps.h>
 34#include <asm/bl_bit.h>
 35
 36#ifdef CONFIG_CPU_SH2
 37# define TRAP_RESERVED_INST	4
 38# define TRAP_ILLEGAL_SLOT_INST	6
 39# define TRAP_ADDRESS_ERROR	9
 40# ifdef CONFIG_CPU_SH2A
 41#  define TRAP_UBC		12
 42#  define TRAP_FPU_ERROR	13
 43#  define TRAP_DIVZERO_ERROR	17
 44#  define TRAP_DIVOVF_ERROR	18
 45# endif
 46#else
 47#define TRAP_RESERVED_INST	12
 48#define TRAP_ILLEGAL_SLOT_INST	13
 49#endif
 50
 51static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
 52{
 53	unsigned long p;
 54	int i;
 55
 56	printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
 57
 58	for (p = bottom & ~31; p < top; ) {
 59		printk("%04lx: ", p & 0xffff);
 60
 61		for (i = 0; i < 8; i++, p += 4) {
 62			unsigned int val;
 63
 64			if (p < bottom || p >= top)
 65				printk("         ");
 66			else {
 67				if (__get_user(val, (unsigned int __user *)p)) {
 68					printk("\n");
 69					return;
 70				}
 71				printk("%08x ", val);
 72			}
 73		}
 74		printk("\n");
 75	}
 76}
 77
 78static DEFINE_SPINLOCK(die_lock);
 79
 80void die(const char * str, struct pt_regs * regs, long err)
 81{
 82	static int die_counter;
 83
 84	oops_enter();
 85
 86	spin_lock_irq(&die_lock);
 87	console_verbose();
 88	bust_spinlocks(1);
 89
 90	printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
 91	print_modules();
 92	show_regs(regs);
 93
 94	printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm,
 95			task_pid_nr(current), task_stack_page(current) + 1);
 96
 97	if (!user_mode(regs) || in_interrupt())
 98		dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
 99			 (unsigned long)task_stack_page(current));
100
101	notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV);
102
103	bust_spinlocks(0);
104	add_taint(TAINT_DIE);
105	spin_unlock_irq(&die_lock);
106	oops_exit();
107
108	if (kexec_should_crash(current))
109		crash_kexec(regs);
110
111	if (in_interrupt())
112		panic("Fatal exception in interrupt");
113
114	if (panic_on_oops)
115		panic("Fatal exception");
116
117	do_exit(SIGSEGV);
118}
119
120static inline void die_if_kernel(const char *str, struct pt_regs *regs,
121				 long err)
122{
123	if (!user_mode(regs))
124		die(str, regs, err);
125}
126
127/*
128 * try and fix up kernelspace address errors
129 * - userspace errors just cause EFAULT to be returned, resulting in SEGV
130 * - kernel/userspace interfaces cause a jump to an appropriate handler
131 * - other kernel errors are bad
132 */
133static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
134{
135	if (!user_mode(regs)) {
136		const struct exception_table_entry *fixup;
137		fixup = search_exception_tables(regs->pc);
138		if (fixup) {
139			regs->pc = fixup->fixup;
140			return;
141		}
142
143		die(str, regs, err);
144	}
145}
146
147static inline void sign_extend(unsigned int count, unsigned char *dst)
148{
149#ifdef __LITTLE_ENDIAN__
150	if ((count == 1) && dst[0] & 0x80) {
151		dst[1] = 0xff;
152		dst[2] = 0xff;
153		dst[3] = 0xff;
154	}
155	if ((count == 2) && dst[1] & 0x80) {
156		dst[2] = 0xff;
157		dst[3] = 0xff;
158	}
159#else
160	if ((count == 1) && dst[3] & 0x80) {
161		dst[2] = 0xff;
162		dst[1] = 0xff;
163		dst[0] = 0xff;
164	}
165	if ((count == 2) && dst[2] & 0x80) {
166		dst[1] = 0xff;
167		dst[0] = 0xff;
168	}
169#endif
170}
171
172static struct mem_access user_mem_access = {
173	copy_from_user,
174	copy_to_user,
175};
176
177/*
178 * handle an instruction that does an unaligned memory access by emulating the
179 * desired behaviour
180 * - note that PC _may not_ point to the faulting instruction
181 *   (if that instruction is in a branch delay slot)
182 * - return 0 if emulation okay, -EFAULT on existential error
183 */
184static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs,
185				struct mem_access *ma)
186{
187	int ret, index, count;
188	unsigned long *rm, *rn;
189	unsigned char *src, *dst;
190	unsigned char __user *srcu, *dstu;
191
192	index = (instruction>>8)&15;	/* 0x0F00 */
193	rn = &regs->regs[index];
194
195	index = (instruction>>4)&15;	/* 0x00F0 */
196	rm = &regs->regs[index];
197
198	count = 1<<(instruction&3);
199
200	switch (count) {
201	case 1: inc_unaligned_byte_access(); break;
202	case 2: inc_unaligned_word_access(); break;
203	case 4: inc_unaligned_dword_access(); break;
204	case 8: inc_unaligned_multi_access(); break;
205	}
206
207	ret = -EFAULT;
208	switch (instruction>>12) {
209	case 0: /* mov.[bwl] to/from memory via r0+rn */
210		if (instruction & 8) {
211			/* from memory */
212			srcu = (unsigned char __user *)*rm;
213			srcu += regs->regs[0];
214			dst = (unsigned char *)rn;
215			*(unsigned long *)dst = 0;
216
217#if !defined(__LITTLE_ENDIAN__)
218			dst += 4-count;
219#endif
220			if (ma->from(dst, srcu, count))
221				goto fetch_fault;
222
223			sign_extend(count, dst);
224		} else {
225			/* to memory */
226			src = (unsigned char *)rm;
227#if !defined(__LITTLE_ENDIAN__)
228			src += 4-count;
229#endif
230			dstu = (unsigned char __user *)*rn;
231			dstu += regs->regs[0];
232
233			if (ma->to(dstu, src, count))
234				goto fetch_fault;
235		}
236		ret = 0;
237		break;
238
239	case 1: /* mov.l Rm,@(disp,Rn) */
240		src = (unsigned char*) rm;
241		dstu = (unsigned char __user *)*rn;
242		dstu += (instruction&0x000F)<<2;
243
244		if (ma->to(dstu, src, 4))
245			goto fetch_fault;
246		ret = 0;
247		break;
248
249	case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
250		if (instruction & 4)
251			*rn -= count;
252		src = (unsigned char*) rm;
253		dstu = (unsigned char __user *)*rn;
254#if !defined(__LITTLE_ENDIAN__)
255		src += 4-count;
256#endif
257		if (ma->to(dstu, src, count))
258			goto fetch_fault;
259		ret = 0;
260		break;
261
262	case 5: /* mov.l @(disp,Rm),Rn */
263		srcu = (unsigned char __user *)*rm;
264		srcu += (instruction & 0x000F) << 2;
265		dst = (unsigned char *)rn;
266		*(unsigned long *)dst = 0;
267
268		if (ma->from(dst, srcu, 4))
269			goto fetch_fault;
270		ret = 0;
271		break;
272
273	case 6:	/* mov.[bwl] from memory, possibly with post-increment */
274		srcu = (unsigned char __user *)*rm;
275		if (instruction & 4)
276			*rm += count;
277		dst = (unsigned char*) rn;
278		*(unsigned long*)dst = 0;
279
280#if !defined(__LITTLE_ENDIAN__)
281		dst += 4-count;
282#endif
283		if (ma->from(dst, srcu, count))
284			goto fetch_fault;
285		sign_extend(count, dst);
286		ret = 0;
287		break;
288
289	case 8:
290		switch ((instruction&0xFF00)>>8) {
291		case 0x81: /* mov.w R0,@(disp,Rn) */
292			src = (unsigned char *) &regs->regs[0];
293#if !defined(__LITTLE_ENDIAN__)
294			src += 2;
295#endif
296			dstu = (unsigned char __user *)*rm; /* called Rn in the spec */
297			dstu += (instruction & 0x000F) << 1;
298
299			if (ma->to(dstu, src, 2))
300				goto fetch_fault;
301			ret = 0;
302			break;
303
304		case 0x85: /* mov.w @(disp,Rm),R0 */
305			srcu = (unsigned char __user *)*rm;
306			srcu += (instruction & 0x000F) << 1;
307			dst = (unsigned char *) &regs->regs[0];
308			*(unsigned long *)dst = 0;
309
310#if !defined(__LITTLE_ENDIAN__)
311			dst += 2;
312#endif
313			if (ma->from(dst, srcu, 2))
314				goto fetch_fault;
315			sign_extend(2, dst);
316			ret = 0;
317			break;
318		}
319		break;
320
321	case 9: /* mov.w @(disp,PC),Rn */
322		srcu = (unsigned char __user *)regs->pc;
323		srcu += 4;
324		srcu += (instruction & 0x00FF) << 1;
325		dst = (unsigned char *)rn;
326		*(unsigned long *)dst = 0;
327
328#if !defined(__LITTLE_ENDIAN__)
329		dst += 2;
330#endif
331
332		if (ma->from(dst, srcu, 2))
333			goto fetch_fault;
334		sign_extend(2, dst);
335		ret = 0;
336		break;
337
338	case 0xd: /* mov.l @(disp,PC),Rn */
339		srcu = (unsigned char __user *)(regs->pc & ~0x3);
340		srcu += 4;
341		srcu += (instruction & 0x00FF) << 2;
342		dst = (unsigned char *)rn;
343		*(unsigned long *)dst = 0;
344
345		if (ma->from(dst, srcu, 4))
346			goto fetch_fault;
347		ret = 0;
348		break;
349	}
350	return ret;
351
352 fetch_fault:
353	/* Argh. Address not only misaligned but also non-existent.
354	 * Raise an EFAULT and see if it's trapped
355	 */
356	die_if_no_fixup("Fault in unaligned fixup", regs, 0);
357	return -EFAULT;
358}
359
360/*
361 * emulate the instruction in the delay slot
362 * - fetches the instruction from PC+2
363 */
364static inline int handle_delayslot(struct pt_regs *regs,
365				   insn_size_t old_instruction,
366				   struct mem_access *ma)
367{
368	insn_size_t instruction;
369	void __user *addr = (void __user *)(regs->pc +
370		instruction_size(old_instruction));
371
372	if (copy_from_user(&instruction, addr, sizeof(instruction))) {
373		/* the instruction-fetch faulted */
374		if (user_mode(regs))
375			return -EFAULT;
376
377		/* kernel */
378		die("delay-slot-insn faulting in handle_unaligned_delayslot",
379		    regs, 0);
380	}
381
382	return handle_unaligned_ins(instruction, regs, ma);
383}
384
385/*
386 * handle an instruction that does an unaligned memory access
387 * - have to be careful of branch delay-slot instructions that fault
388 *  SH3:
389 *   - if the branch would be taken PC points to the branch
390 *   - if the branch would not be taken, PC points to delay-slot
391 *  SH4:
392 *   - PC always points to delayed branch
393 * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
394 */
395
396/* Macros to determine offset from current PC for branch instructions */
397/* Explicit type coercion is used to force sign extension where needed */
398#define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
399#define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
400
401int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
402			    struct mem_access *ma, int expected,
403			    unsigned long address)
404{
405	u_int rm;
406	int ret, index;
407
408	/*
409	 * XXX: We can't handle mixed 16/32-bit instructions yet
410	 */
411	if (instruction_size(instruction) != 2)
412		return -EINVAL;
413
414	index = (instruction>>8)&15;	/* 0x0F00 */
415	rm = regs->regs[index];
416
417	/*
418	 * Log the unexpected fixups, and then pass them on to perf.
419	 *
420	 * We intentionally don't report the expected cases to perf as
421	 * otherwise the trapped I/O case will skew the results too much
422	 * to be useful.
423	 */
424	if (!expected) {
425		unaligned_fixups_notify(current, instruction, regs);
426		perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1,
427			      regs, address);
428	}
429
430	ret = -EFAULT;
431	switch (instruction&0xF000) {
432	case 0x0000:
433		if (instruction==0x000B) {
434			/* rts */
435			ret = handle_delayslot(regs, instruction, ma);
436			if (ret==0)
437				regs->pc = regs->pr;
438		}
439		else if ((instruction&0x00FF)==0x0023) {
440			/* braf @Rm */
441			ret = handle_delayslot(regs, instruction, ma);
442			if (ret==0)
443				regs->pc += rm + 4;
444		}
445		else if ((instruction&0x00FF)==0x0003) {
446			/* bsrf @Rm */
447			ret = handle_delayslot(regs, instruction, ma);
448			if (ret==0) {
449				regs->pr = regs->pc + 4;
450				regs->pc += rm + 4;
451			}
452		}
453		else {
454			/* mov.[bwl] to/from memory via r0+rn */
455			goto simple;
456		}
457		break;
458
459	case 0x1000: /* mov.l Rm,@(disp,Rn) */
460		goto simple;
461
462	case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
463		goto simple;
464
465	case 0x4000:
466		if ((instruction&0x00FF)==0x002B) {
467			/* jmp @Rm */
468			ret = handle_delayslot(regs, instruction, ma);
469			if (ret==0)
470				regs->pc = rm;
471		}
472		else if ((instruction&0x00FF)==0x000B) {
473			/* jsr @Rm */
474			ret = handle_delayslot(regs, instruction, ma);
475			if (ret==0) {
476				regs->pr = regs->pc + 4;
477				regs->pc = rm;
478			}
479		}
480		else {
481			/* mov.[bwl] to/from memory via r0+rn */
482			goto simple;
483		}
484		break;
485
486	case 0x5000: /* mov.l @(disp,Rm),Rn */
487		goto simple;
488
489	case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
490		goto simple;
491
492	case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
493		switch (instruction&0x0F00) {
494		case 0x0100: /* mov.w R0,@(disp,Rm) */
495			goto simple;
496		case 0x0500: /* mov.w @(disp,Rm),R0 */
497			goto simple;
498		case 0x0B00: /* bf   lab - no delayslot*/
499			ret = 0;
500			break;
501		case 0x0F00: /* bf/s lab */
502			ret = handle_delayslot(regs, instruction, ma);
503			if (ret==0) {
504#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
505				if ((regs->sr & 0x00000001) != 0)
506					regs->pc += 4; /* next after slot */
507				else
508#endif
509					regs->pc += SH_PC_8BIT_OFFSET(instruction);
510			}
511			break;
512		case 0x0900: /* bt   lab - no delayslot */
513			ret = 0;
514			break;
515		case 0x0D00: /* bt/s lab */
516			ret = handle_delayslot(regs, instruction, ma);
517			if (ret==0) {
518#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
519				if ((regs->sr & 0x00000001) == 0)
520					regs->pc += 4; /* next after slot */
521				else
522#endif
523					regs->pc += SH_PC_8BIT_OFFSET(instruction);
524			}
525			break;
526		}
527		break;
528
529	case 0x9000: /* mov.w @(disp,Rm),Rn */
530		goto simple;
531
532	case 0xA000: /* bra label */
533		ret = handle_delayslot(regs, instruction, ma);
534		if (ret==0)
535			regs->pc += SH_PC_12BIT_OFFSET(instruction);
536		break;
537
538	case 0xB000: /* bsr label */
539		ret = handle_delayslot(regs, instruction, ma);
540		if (ret==0) {
541			regs->pr = regs->pc + 4;
542			regs->pc += SH_PC_12BIT_OFFSET(instruction);
543		}
544		break;
545
546	case 0xD000: /* mov.l @(disp,Rm),Rn */
547		goto simple;
548	}
549	return ret;
550
551	/* handle non-delay-slot instruction */
552 simple:
553	ret = handle_unaligned_ins(instruction, regs, ma);
554	if (ret==0)
555		regs->pc += instruction_size(instruction);
556	return ret;
557}
558
559/*
560 * Handle various address error exceptions:
561 *  - instruction address error:
562 *       misaligned PC
563 *       PC >= 0x80000000 in user mode
564 *  - data address error (read and write)
565 *       misaligned data access
566 *       access to >= 0x80000000 is user mode
567 * Unfortuntaly we can't distinguish between instruction address error
568 * and data address errors caused by read accesses.
569 */
570asmlinkage void do_address_error(struct pt_regs *regs,
571				 unsigned long writeaccess,
572				 unsigned long address)
573{
574	unsigned long error_code = 0;
575	mm_segment_t oldfs;
576	siginfo_t info;
577	insn_size_t instruction;
578	int tmp;
579
580	/* Intentional ifdef */
581#ifdef CONFIG_CPU_HAS_SR_RB
582	error_code = lookup_exception_vector();
583#endif
584
585	oldfs = get_fs();
586
587	if (user_mode(regs)) {
588		int si_code = BUS_ADRERR;
589		unsigned int user_action;
590
591		local_irq_enable();
592		inc_unaligned_user_access();
593
594		set_fs(USER_DS);
595		if (copy_from_user(&instruction, (insn_size_t *)(regs->pc & ~1),
596				   sizeof(instruction))) {
597			set_fs(oldfs);
598			goto uspace_segv;
599		}
600		set_fs(oldfs);
601
602		/* shout about userspace fixups */
603		unaligned_fixups_notify(current, instruction, regs);
604
605		user_action = unaligned_user_action();
606		if (user_action & UM_FIXUP)
607			goto fixup;
608		if (user_action & UM_SIGNAL)
609			goto uspace_segv;
610		else {
611			/* ignore */
612			regs->pc += instruction_size(instruction);
613			return;
614		}
615
616fixup:
617		/* bad PC is not something we can fix */
618		if (regs->pc & 1) {
619			si_code = BUS_ADRALN;
620			goto uspace_segv;
621		}
622
623		set_fs(USER_DS);
624		tmp = handle_unaligned_access(instruction, regs,
625					      &user_mem_access, 0,
626					      address);
627		set_fs(oldfs);
628
629		if (tmp == 0)
630			return; /* sorted */
631uspace_segv:
632		printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
633		       "access (PC %lx PR %lx)\n", current->comm, regs->pc,
634		       regs->pr);
635
636		info.si_signo = SIGBUS;
637		info.si_errno = 0;
638		info.si_code = si_code;
639		info.si_addr = (void __user *)address;
640		force_sig_info(SIGBUS, &info, current);
641	} else {
642		inc_unaligned_kernel_access();
643
644		if (regs->pc & 1)
645			die("unaligned program counter", regs, error_code);
646
647		set_fs(KERNEL_DS);
648		if (copy_from_user(&instruction, (void __user *)(regs->pc),
649				   sizeof(instruction))) {
650			/* Argh. Fault on the instruction itself.
651			   This should never happen non-SMP
652			*/
653			set_fs(oldfs);
654			die("insn faulting in do_address_error", regs, 0);
655		}
656
657		unaligned_fixups_notify(current, instruction, regs);
658
659		handle_unaligned_access(instruction, regs, &user_mem_access,
660					0, address);
661		set_fs(oldfs);
662	}
663}
664
665#ifdef CONFIG_SH_DSP
666/*
667 *	SH-DSP support gerg@snapgear.com.
668 */
669int is_dsp_inst(struct pt_regs *regs)
670{
671	unsigned short inst = 0;
672
673	/*
674	 * Safe guard if DSP mode is already enabled or we're lacking
675	 * the DSP altogether.
676	 */
677	if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
678		return 0;
679
680	get_user(inst, ((unsigned short *) regs->pc));
681
682	inst &= 0xf000;
683
684	/* Check for any type of DSP or support instruction */
685	if ((inst == 0xf000) || (inst == 0x4000))
686		return 1;
687
688	return 0;
689}
690#else
691#define is_dsp_inst(regs)	(0)
692#endif /* CONFIG_SH_DSP */
693
694#ifdef CONFIG_CPU_SH2A
695asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
696				unsigned long r6, unsigned long r7,
697				struct pt_regs __regs)
698{
699	siginfo_t info;
700
701	switch (r4) {
702	case TRAP_DIVZERO_ERROR:
703		info.si_code = FPE_INTDIV;
704		break;
705	case TRAP_DIVOVF_ERROR:
706		info.si_code = FPE_INTOVF;
707		break;
708	}
709
710	force_sig_info(SIGFPE, &info, current);
 
711}
712#endif
713
714asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
715				unsigned long r6, unsigned long r7,
716				struct pt_regs __regs)
717{
718	struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
719	unsigned long error_code;
720	struct task_struct *tsk = current;
721
722#ifdef CONFIG_SH_FPU_EMU
723	unsigned short inst = 0;
724	int err;
725
726	get_user(inst, (unsigned short*)regs->pc);
727
728	err = do_fpu_inst(inst, regs);
729	if (!err) {
730		regs->pc += instruction_size(inst);
731		return;
732	}
733	/* not a FPU inst. */
734#endif
735
736#ifdef CONFIG_SH_DSP
737	/* Check if it's a DSP instruction */
738	if (is_dsp_inst(regs)) {
739		/* Enable DSP mode, and restart instruction. */
740		regs->sr |= SR_DSP;
741		/* Save DSP mode */
742		tsk->thread.dsp_status.status |= SR_DSP;
743		return;
744	}
745#endif
746
747	error_code = lookup_exception_vector();
748
749	local_irq_enable();
750	force_sig(SIGILL, tsk);
751	die_if_no_fixup("reserved instruction", regs, error_code);
752}
753
754#ifdef CONFIG_SH_FPU_EMU
755static int emulate_branch(unsigned short inst, struct pt_regs *regs)
756{
757	/*
758	 * bfs: 8fxx: PC+=d*2+4;
759	 * bts: 8dxx: PC+=d*2+4;
760	 * bra: axxx: PC+=D*2+4;
761	 * bsr: bxxx: PC+=D*2+4  after PR=PC+4;
762	 * braf:0x23: PC+=Rn*2+4;
763	 * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
764	 * jmp: 4x2b: PC=Rn;
765	 * jsr: 4x0b: PC=Rn      after PR=PC+4;
766	 * rts: 000b: PC=PR;
767	 */
768	if (((inst & 0xf000) == 0xb000)  ||	/* bsr */
769	    ((inst & 0xf0ff) == 0x0003)  ||	/* bsrf */
770	    ((inst & 0xf0ff) == 0x400b))	/* jsr */
771		regs->pr = regs->pc + 4;
772
773	if ((inst & 0xfd00) == 0x8d00) {	/* bfs, bts */
774		regs->pc += SH_PC_8BIT_OFFSET(inst);
775		return 0;
776	}
777
778	if ((inst & 0xe000) == 0xa000) {	/* bra, bsr */
779		regs->pc += SH_PC_12BIT_OFFSET(inst);
780		return 0;
781	}
782
783	if ((inst & 0xf0df) == 0x0003) {	/* braf, bsrf */
784		regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
785		return 0;
786	}
787
788	if ((inst & 0xf0df) == 0x400b) {	/* jmp, jsr */
789		regs->pc = regs->regs[(inst & 0x0f00) >> 8];
790		return 0;
791	}
792
793	if ((inst & 0xffff) == 0x000b) {	/* rts */
794		regs->pc = regs->pr;
795		return 0;
796	}
797
798	return 1;
799}
800#endif
801
802asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
803				unsigned long r6, unsigned long r7,
804				struct pt_regs __regs)
805{
806	struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
807	unsigned long inst;
808	struct task_struct *tsk = current;
809
810	if (kprobe_handle_illslot(regs->pc) == 0)
811		return;
812
813#ifdef CONFIG_SH_FPU_EMU
814	get_user(inst, (unsigned short *)regs->pc + 1);
815	if (!do_fpu_inst(inst, regs)) {
816		get_user(inst, (unsigned short *)regs->pc);
817		if (!emulate_branch(inst, regs))
818			return;
819		/* fault in branch.*/
820	}
821	/* not a FPU inst. */
822#endif
823
824	inst = lookup_exception_vector();
825
826	local_irq_enable();
827	force_sig(SIGILL, tsk);
828	die_if_no_fixup("illegal slot instruction", regs, inst);
829}
830
831asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
832				   unsigned long r6, unsigned long r7,
833				   struct pt_regs __regs)
834{
835	struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
836	long ex;
837
838	ex = lookup_exception_vector();
839	die_if_kernel("exception", regs, ex);
840}
841
842void __cpuinit per_cpu_trap_init(void)
843{
844	extern void *vbr_base;
845
846	/* NOTE: The VBR value should be at P1
847	   (or P2, virtural "fixed" address space).
848	   It's definitely should not in physical address.  */
849
850	asm volatile("ldc	%0, vbr"
851		     : /* no output */
852		     : "r" (&vbr_base)
853		     : "memory");
854
855	/* disable exception blocking now when the vbr has been setup */
856	clear_bl_bit();
857}
858
859void *set_exception_table_vec(unsigned int vec, void *handler)
860{
861	extern void *exception_handling_table[];
862	void *old_handler;
863
864	old_handler = exception_handling_table[vec];
865	exception_handling_table[vec] = handler;
866	return old_handler;
867}
868
869void __init trap_init(void)
870{
871	set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
872	set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
873
874#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
875    defined(CONFIG_SH_FPU_EMU)
876	/*
877	 * For SH-4 lacking an FPU, treat floating point instructions as
878	 * reserved. They'll be handled in the math-emu case, or faulted on
879	 * otherwise.
880	 */
881	set_exception_table_evt(0x800, do_reserved_inst);
882	set_exception_table_evt(0x820, do_illegal_slot_inst);
883#elif defined(CONFIG_SH_FPU)
884	set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
885	set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
886#endif
887
888#ifdef CONFIG_CPU_SH2
889	set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
890#endif
891#ifdef CONFIG_CPU_SH2A
892	set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
893	set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
894#ifdef CONFIG_SH_FPU
895	set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler);
896#endif
897#endif
898
899#ifdef TRAP_UBC
900	set_exception_table_vec(TRAP_UBC, breakpoint_trap_handler);
901#endif
902}
903
904void show_stack(struct task_struct *tsk, unsigned long *sp)
905{
906	unsigned long stack;
907
908	if (!tsk)
909		tsk = current;
910	if (tsk == current)
911		sp = (unsigned long *)current_stack_pointer;
912	else
913		sp = (unsigned long *)tsk->thread.sp;
914
915	stack = (unsigned long)sp;
916	dump_mem("Stack: ", stack, THREAD_SIZE +
917		 (unsigned long)task_stack_page(tsk));
918	show_trace(tsk, sp, NULL);
919}
920
921void dump_stack(void)
922{
923	show_stack(NULL, NULL);
924}
925EXPORT_SYMBOL(dump_stack);