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1/*
2 * RouterBoard 500 Platform devices
3 *
4 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17#include <linux/kernel.h>
18#include <linux/export.h>
19#include <linux/init.h>
20#include <linux/ctype.h>
21#include <linux/string.h>
22#include <linux/platform_device.h>
23#include <linux/mtd/nand.h>
24#include <linux/mtd/mtd.h>
25#include <linux/mtd/partitions.h>
26#include <linux/gpio_keys.h>
27#include <linux/input.h>
28#include <linux/serial_8250.h>
29
30#include <asm/bootinfo.h>
31
32#include <asm/mach-rc32434/rc32434.h>
33#include <asm/mach-rc32434/dma.h>
34#include <asm/mach-rc32434/dma_v.h>
35#include <asm/mach-rc32434/eth.h>
36#include <asm/mach-rc32434/rb.h>
37#include <asm/mach-rc32434/integ.h>
38#include <asm/mach-rc32434/gpio.h>
39#include <asm/mach-rc32434/irq.h>
40
41#define ETH0_RX_DMA_ADDR (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET)
42#define ETH0_TX_DMA_ADDR (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET)
43
44extern unsigned int idt_cpu_freq;
45
46static struct mpmc_device dev3;
47
48void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
49{
50 unsigned long flags;
51
52 spin_lock_irqsave(&dev3.lock, flags);
53
54 dev3.state = (dev3.state | or_mask) & ~nand_mask;
55 writeb(dev3.state, dev3.base);
56
57 spin_unlock_irqrestore(&dev3.lock, flags);
58}
59EXPORT_SYMBOL(set_latch_u5);
60
61unsigned char get_latch_u5(void)
62{
63 return dev3.state;
64}
65EXPORT_SYMBOL(get_latch_u5);
66
67static struct resource korina_dev0_res[] = {
68 {
69 .name = "korina_regs",
70 .start = ETH0_BASE_ADDR,
71 .end = ETH0_BASE_ADDR + sizeof(struct eth_regs),
72 .flags = IORESOURCE_MEM,
73 }, {
74 .name = "korina_rx",
75 .start = ETH0_DMA_RX_IRQ,
76 .end = ETH0_DMA_RX_IRQ,
77 .flags = IORESOURCE_IRQ
78 }, {
79 .name = "korina_tx",
80 .start = ETH0_DMA_TX_IRQ,
81 .end = ETH0_DMA_TX_IRQ,
82 .flags = IORESOURCE_IRQ
83 }, {
84 .name = "korina_ovr",
85 .start = ETH0_RX_OVR_IRQ,
86 .end = ETH0_RX_OVR_IRQ,
87 .flags = IORESOURCE_IRQ
88 }, {
89 .name = "korina_und",
90 .start = ETH0_TX_UND_IRQ,
91 .end = ETH0_TX_UND_IRQ,
92 .flags = IORESOURCE_IRQ
93 }, {
94 .name = "korina_dma_rx",
95 .start = ETH0_RX_DMA_ADDR,
96 .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
97 .flags = IORESOURCE_MEM,
98 }, {
99 .name = "korina_dma_tx",
100 .start = ETH0_TX_DMA_ADDR,
101 .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
102 .flags = IORESOURCE_MEM,
103 }
104};
105
106static struct korina_device korina_dev0_data = {
107 .name = "korina0",
108 .mac = {0xde, 0xca, 0xff, 0xc0, 0xff, 0xee}
109};
110
111static struct platform_device korina_dev0 = {
112 .id = -1,
113 .name = "korina",
114 .resource = korina_dev0_res,
115 .num_resources = ARRAY_SIZE(korina_dev0_res),
116};
117
118static struct resource cf_slot0_res[] = {
119 {
120 .name = "cf_membase",
121 .flags = IORESOURCE_MEM
122 }, {
123 .name = "cf_irq",
124 .start = (8 + 4 * 32 + CF_GPIO_NUM), /* 149 */
125 .end = (8 + 4 * 32 + CF_GPIO_NUM),
126 .flags = IORESOURCE_IRQ
127 }
128};
129
130static struct cf_device cf_slot0_data = {
131 .gpio_pin = CF_GPIO_NUM
132};
133
134static struct platform_device cf_slot0 = {
135 .id = -1,
136 .name = "pata-rb532-cf",
137 .dev.platform_data = &cf_slot0_data,
138 .resource = cf_slot0_res,
139 .num_resources = ARRAY_SIZE(cf_slot0_res),
140};
141
142/* Resources and device for NAND */
143static int rb532_dev_ready(struct mtd_info *mtd)
144{
145 return gpio_get_value(GPIO_RDY);
146}
147
148static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
149{
150 struct nand_chip *chip = mtd->priv;
151 unsigned char orbits, nandbits;
152
153 if (ctrl & NAND_CTRL_CHANGE) {
154 orbits = (ctrl & NAND_CLE) << 1;
155 orbits |= (ctrl & NAND_ALE) >> 1;
156
157 nandbits = (~ctrl & NAND_CLE) << 1;
158 nandbits |= (~ctrl & NAND_ALE) >> 1;
159
160 set_latch_u5(orbits, nandbits);
161 }
162 if (cmd != NAND_CMD_NONE)
163 writeb(cmd, chip->IO_ADDR_W);
164}
165
166static struct resource nand_slot0_res[] = {
167 [0] = {
168 .name = "nand_membase",
169 .flags = IORESOURCE_MEM
170 }
171};
172
173static struct platform_nand_data rb532_nand_data = {
174 .ctrl.dev_ready = rb532_dev_ready,
175 .ctrl.cmd_ctrl = rb532_cmd_ctrl,
176};
177
178static struct platform_device nand_slot0 = {
179 .name = "gen_nand",
180 .id = -1,
181 .resource = nand_slot0_res,
182 .num_resources = ARRAY_SIZE(nand_slot0_res),
183 .dev.platform_data = &rb532_nand_data,
184};
185
186static struct mtd_partition rb532_partition_info[] = {
187 {
188 .name = "Routerboard NAND boot",
189 .offset = 0,
190 .size = 4 * 1024 * 1024,
191 }, {
192 .name = "rootfs",
193 .offset = MTDPART_OFS_NXTBLK,
194 .size = MTDPART_SIZ_FULL,
195 }
196};
197
198static struct platform_device rb532_led = {
199 .name = "rb532-led",
200 .id = -1,
201};
202
203static struct platform_device rb532_button = {
204 .name = "rb532-button",
205 .id = -1,
206};
207
208static struct resource rb532_wdt_res[] = {
209 {
210 .name = "rb532_wdt_res",
211 .start = INTEG0_BASE_ADDR,
212 .end = INTEG0_BASE_ADDR + sizeof(struct integ),
213 .flags = IORESOURCE_MEM,
214 }
215};
216
217static struct platform_device rb532_wdt = {
218 .name = "rc32434_wdt",
219 .id = -1,
220 .resource = rb532_wdt_res,
221 .num_resources = ARRAY_SIZE(rb532_wdt_res),
222};
223
224static struct plat_serial8250_port rb532_uart_res[] = {
225 {
226 .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
227 .irq = UART0_IRQ,
228 .regshift = 2,
229 .iotype = UPIO_MEM,
230 .flags = UPF_BOOT_AUTOCONF,
231 },
232 {
233 .flags = 0,
234 }
235};
236
237static struct platform_device rb532_uart = {
238 .name = "serial8250",
239 .id = PLAT8250_DEV_PLATFORM,
240 .dev.platform_data = &rb532_uart_res,
241};
242
243static struct platform_device *rb532_devs[] = {
244 &korina_dev0,
245 &nand_slot0,
246 &cf_slot0,
247 &rb532_led,
248 &rb532_button,
249 &rb532_uart,
250 &rb532_wdt
251};
252
253static void __init parse_mac_addr(char *macstr)
254{
255 int i, h, l;
256
257 for (i = 0; i < 6; i++) {
258 if (i != 5 && *(macstr + 2) != ':')
259 return;
260
261 h = hex_to_bin(*macstr++);
262 if (h == -1)
263 return;
264
265 l = hex_to_bin(*macstr++);
266 if (l == -1)
267 return;
268
269 macstr++;
270 korina_dev0_data.mac[i] = (h << 4) + l;
271 }
272}
273
274
275/* NAND definitions */
276#define NAND_CHIP_DELAY 25
277
278static void __init rb532_nand_setup(void)
279{
280 switch (mips_machtype) {
281 case MACH_MIKROTIK_RB532A:
282 set_latch_u5(LO_FOFF | LO_CEX,
283 LO_ULED | LO_ALE | LO_CLE | LO_WPX);
284 break;
285 default:
286 set_latch_u5(LO_WPX | LO_FOFF | LO_CEX,
287 LO_ULED | LO_ALE | LO_CLE);
288 break;
289 }
290
291 /* Setup NAND specific settings */
292 rb532_nand_data.chip.nr_chips = 1;
293 rb532_nand_data.chip.nr_partitions = ARRAY_SIZE(rb532_partition_info);
294 rb532_nand_data.chip.partitions = rb532_partition_info;
295 rb532_nand_data.chip.chip_delay = NAND_CHIP_DELAY;
296}
297
298
299static int __init plat_setup_devices(void)
300{
301 /* Look for the CF card reader */
302 if (!readl(IDT434_REG_BASE + DEV1MASK))
303 rb532_devs[2] = NULL; /* disable cf_slot0 at index 2 */
304 else {
305 cf_slot0_res[0].start =
306 readl(IDT434_REG_BASE + DEV1BASE);
307 cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
308 }
309
310 /* Read the NAND resources from the device controller */
311 nand_slot0_res[0].start = readl(IDT434_REG_BASE + DEV2BASE);
312 nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
313
314 /* Read and map device controller 3 */
315 dev3.base = ioremap_nocache(readl(IDT434_REG_BASE + DEV3BASE), 1);
316
317 if (!dev3.base) {
318 printk(KERN_ERR "rb532: cannot remap device controller 3\n");
319 return -ENXIO;
320 }
321
322 /* Initialise the NAND device */
323 rb532_nand_setup();
324
325 /* set the uart clock to the current cpu frequency */
326 rb532_uart_res[0].uartclk = idt_cpu_freq;
327
328 dev_set_drvdata(&korina_dev0.dev, &korina_dev0_data);
329
330 return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs));
331}
332
333static int __init setup_kmac(char *s)
334{
335 printk(KERN_INFO "korina mac = %s\n", s);
336 parse_mac_addr(s);
337 return 0;
338}
339
340__setup("kmac=", setup_kmac);
341
342arch_initcall(plat_setup_devices);
1/*
2 * RouterBoard 500 Platform devices
3 *
4 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17#include <linux/kernel.h>
18#include <linux/export.h>
19#include <linux/init.h>
20#include <linux/ctype.h>
21#include <linux/string.h>
22#include <linux/platform_device.h>
23#include <linux/mtd/rawnand.h>
24#include <linux/mtd/mtd.h>
25#include <linux/mtd/partitions.h>
26#include <linux/gpio.h>
27#include <linux/gpio_keys.h>
28#include <linux/input.h>
29#include <linux/serial_8250.h>
30
31#include <asm/bootinfo.h>
32
33#include <asm/mach-rc32434/rc32434.h>
34#include <asm/mach-rc32434/dma.h>
35#include <asm/mach-rc32434/dma_v.h>
36#include <asm/mach-rc32434/eth.h>
37#include <asm/mach-rc32434/rb.h>
38#include <asm/mach-rc32434/integ.h>
39#include <asm/mach-rc32434/gpio.h>
40#include <asm/mach-rc32434/irq.h>
41
42#define ETH0_RX_DMA_ADDR (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET)
43#define ETH0_TX_DMA_ADDR (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET)
44
45extern unsigned int idt_cpu_freq;
46
47static struct mpmc_device dev3;
48
49void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
50{
51 unsigned long flags;
52
53 spin_lock_irqsave(&dev3.lock, flags);
54
55 dev3.state = (dev3.state | or_mask) & ~nand_mask;
56 writeb(dev3.state, dev3.base);
57
58 spin_unlock_irqrestore(&dev3.lock, flags);
59}
60EXPORT_SYMBOL(set_latch_u5);
61
62unsigned char get_latch_u5(void)
63{
64 return dev3.state;
65}
66EXPORT_SYMBOL(get_latch_u5);
67
68static struct resource korina_dev0_res[] = {
69 {
70 .name = "korina_regs",
71 .start = ETH0_BASE_ADDR,
72 .end = ETH0_BASE_ADDR + sizeof(struct eth_regs),
73 .flags = IORESOURCE_MEM,
74 }, {
75 .name = "korina_rx",
76 .start = ETH0_DMA_RX_IRQ,
77 .end = ETH0_DMA_RX_IRQ,
78 .flags = IORESOURCE_IRQ
79 }, {
80 .name = "korina_tx",
81 .start = ETH0_DMA_TX_IRQ,
82 .end = ETH0_DMA_TX_IRQ,
83 .flags = IORESOURCE_IRQ
84 }, {
85 .name = "korina_ovr",
86 .start = ETH0_RX_OVR_IRQ,
87 .end = ETH0_RX_OVR_IRQ,
88 .flags = IORESOURCE_IRQ
89 }, {
90 .name = "korina_und",
91 .start = ETH0_TX_UND_IRQ,
92 .end = ETH0_TX_UND_IRQ,
93 .flags = IORESOURCE_IRQ
94 }, {
95 .name = "korina_dma_rx",
96 .start = ETH0_RX_DMA_ADDR,
97 .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
98 .flags = IORESOURCE_MEM,
99 }, {
100 .name = "korina_dma_tx",
101 .start = ETH0_TX_DMA_ADDR,
102 .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
103 .flags = IORESOURCE_MEM,
104 }
105};
106
107static struct korina_device korina_dev0_data = {
108 .name = "korina0",
109 .mac = {0xde, 0xca, 0xff, 0xc0, 0xff, 0xee}
110};
111
112static struct platform_device korina_dev0 = {
113 .id = -1,
114 .name = "korina",
115 .resource = korina_dev0_res,
116 .num_resources = ARRAY_SIZE(korina_dev0_res),
117};
118
119static struct resource cf_slot0_res[] = {
120 {
121 .name = "cf_membase",
122 .flags = IORESOURCE_MEM
123 }, {
124 .name = "cf_irq",
125 .start = (8 + 4 * 32 + CF_GPIO_NUM), /* 149 */
126 .end = (8 + 4 * 32 + CF_GPIO_NUM),
127 .flags = IORESOURCE_IRQ
128 }
129};
130
131static struct cf_device cf_slot0_data = {
132 .gpio_pin = CF_GPIO_NUM
133};
134
135static struct platform_device cf_slot0 = {
136 .id = -1,
137 .name = "pata-rb532-cf",
138 .dev.platform_data = &cf_slot0_data,
139 .resource = cf_slot0_res,
140 .num_resources = ARRAY_SIZE(cf_slot0_res),
141};
142
143/* Resources and device for NAND */
144static int rb532_dev_ready(struct mtd_info *mtd)
145{
146 return gpio_get_value(GPIO_RDY);
147}
148
149static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
150{
151 struct nand_chip *chip = mtd_to_nand(mtd);
152 unsigned char orbits, nandbits;
153
154 if (ctrl & NAND_CTRL_CHANGE) {
155 orbits = (ctrl & NAND_CLE) << 1;
156 orbits |= (ctrl & NAND_ALE) >> 1;
157
158 nandbits = (~ctrl & NAND_CLE) << 1;
159 nandbits |= (~ctrl & NAND_ALE) >> 1;
160
161 set_latch_u5(orbits, nandbits);
162 }
163 if (cmd != NAND_CMD_NONE)
164 writeb(cmd, chip->IO_ADDR_W);
165}
166
167static struct resource nand_slot0_res[] = {
168 [0] = {
169 .name = "nand_membase",
170 .flags = IORESOURCE_MEM
171 }
172};
173
174static struct platform_nand_data rb532_nand_data = {
175 .ctrl.dev_ready = rb532_dev_ready,
176 .ctrl.cmd_ctrl = rb532_cmd_ctrl,
177};
178
179static struct platform_device nand_slot0 = {
180 .name = "gen_nand",
181 .id = -1,
182 .resource = nand_slot0_res,
183 .num_resources = ARRAY_SIZE(nand_slot0_res),
184 .dev.platform_data = &rb532_nand_data,
185};
186
187static struct mtd_partition rb532_partition_info[] = {
188 {
189 .name = "Routerboard NAND boot",
190 .offset = 0,
191 .size = 4 * 1024 * 1024,
192 }, {
193 .name = "rootfs",
194 .offset = MTDPART_OFS_NXTBLK,
195 .size = MTDPART_SIZ_FULL,
196 }
197};
198
199static struct platform_device rb532_led = {
200 .name = "rb532-led",
201 .id = -1,
202};
203
204static struct platform_device rb532_button = {
205 .name = "rb532-button",
206 .id = -1,
207};
208
209static struct resource rb532_wdt_res[] = {
210 {
211 .name = "rb532_wdt_res",
212 .start = INTEG0_BASE_ADDR,
213 .end = INTEG0_BASE_ADDR + sizeof(struct integ),
214 .flags = IORESOURCE_MEM,
215 }
216};
217
218static struct platform_device rb532_wdt = {
219 .name = "rc32434_wdt",
220 .id = -1,
221 .resource = rb532_wdt_res,
222 .num_resources = ARRAY_SIZE(rb532_wdt_res),
223};
224
225static struct plat_serial8250_port rb532_uart_res[] = {
226 {
227 .type = PORT_16550A,
228 .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
229 .irq = UART0_IRQ,
230 .regshift = 2,
231 .iotype = UPIO_MEM,
232 .flags = UPF_BOOT_AUTOCONF,
233 },
234 {
235 .flags = 0,
236 }
237};
238
239static struct platform_device rb532_uart = {
240 .name = "serial8250",
241 .id = PLAT8250_DEV_PLATFORM,
242 .dev.platform_data = &rb532_uart_res,
243};
244
245static struct platform_device *rb532_devs[] = {
246 &korina_dev0,
247 &nand_slot0,
248 &cf_slot0,
249 &rb532_led,
250 &rb532_button,
251 &rb532_uart,
252 &rb532_wdt
253};
254
255/* NAND definitions */
256#define NAND_CHIP_DELAY 25
257
258static void __init rb532_nand_setup(void)
259{
260 switch (mips_machtype) {
261 case MACH_MIKROTIK_RB532A:
262 set_latch_u5(LO_FOFF | LO_CEX,
263 LO_ULED | LO_ALE | LO_CLE | LO_WPX);
264 break;
265 default:
266 set_latch_u5(LO_WPX | LO_FOFF | LO_CEX,
267 LO_ULED | LO_ALE | LO_CLE);
268 break;
269 }
270
271 /* Setup NAND specific settings */
272 rb532_nand_data.chip.nr_chips = 1;
273 rb532_nand_data.chip.nr_partitions = ARRAY_SIZE(rb532_partition_info);
274 rb532_nand_data.chip.partitions = rb532_partition_info;
275 rb532_nand_data.chip.chip_delay = NAND_CHIP_DELAY;
276}
277
278
279static int __init plat_setup_devices(void)
280{
281 /* Look for the CF card reader */
282 if (!readl(IDT434_REG_BASE + DEV1MASK))
283 rb532_devs[2] = NULL; /* disable cf_slot0 at index 2 */
284 else {
285 cf_slot0_res[0].start =
286 readl(IDT434_REG_BASE + DEV1BASE);
287 cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
288 }
289
290 /* Read the NAND resources from the device controller */
291 nand_slot0_res[0].start = readl(IDT434_REG_BASE + DEV2BASE);
292 nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
293
294 /* Read and map device controller 3 */
295 dev3.base = ioremap_nocache(readl(IDT434_REG_BASE + DEV3BASE), 1);
296
297 if (!dev3.base) {
298 printk(KERN_ERR "rb532: cannot remap device controller 3\n");
299 return -ENXIO;
300 }
301
302 /* Initialise the NAND device */
303 rb532_nand_setup();
304
305 /* set the uart clock to the current cpu frequency */
306 rb532_uart_res[0].uartclk = idt_cpu_freq;
307
308 dev_set_drvdata(&korina_dev0.dev, &korina_dev0_data);
309
310 return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs));
311}
312
313#ifdef CONFIG_NET
314
315static int __init setup_kmac(char *s)
316{
317 printk(KERN_INFO "korina mac = %s\n", s);
318 if (!mac_pton(s, korina_dev0_data.mac)) {
319 printk(KERN_ERR "Invalid mac\n");
320 return -EINVAL;
321 }
322 return 0;
323}
324
325__setup("kmac=", setup_kmac);
326
327#endif /* CONFIG_NET */
328
329arch_initcall(plat_setup_devices);