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1/*
2 * OMAP4 PRM module functions
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc.
5 * Copyright (C) 2010 Nokia Corporation
6 * Benoît Cousson
7 * Paul Walmsley
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/delay.h>
16#include <linux/errno.h>
17#include <linux/err.h>
18#include <linux/io.h>
19
20#include <plat/cpu.h>
21#include <plat/irqs.h>
22#include <plat/prcm.h>
23
24#include "iomap.h"
25#include "common.h"
26#include "vp.h"
27#include "prm44xx.h"
28#include "prm-regbits-44xx.h"
29#include "prcm44xx.h"
30#include "prminst44xx.h"
31
32static const struct omap_prcm_irq omap4_prcm_irqs[] = {
33 OMAP_PRCM_IRQ("wkup", 0, 0),
34 OMAP_PRCM_IRQ("io", 9, 1),
35};
36
37static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
38 .ack = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
39 .mask = OMAP4_PRM_IRQENABLE_MPU_OFFSET,
40 .nr_regs = 2,
41 .irqs = omap4_prcm_irqs,
42 .nr_irqs = ARRAY_SIZE(omap4_prcm_irqs),
43 .irq = OMAP44XX_IRQ_PRCM,
44 .read_pending_irqs = &omap44xx_prm_read_pending_irqs,
45 .ocp_barrier = &omap44xx_prm_ocp_barrier,
46 .save_and_clear_irqen = &omap44xx_prm_save_and_clear_irqen,
47 .restore_irqen = &omap44xx_prm_restore_irqen,
48};
49
50/* PRM low-level functions */
51
52/* Read a register in a CM/PRM instance in the PRM module */
53u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
54{
55 return __raw_readl(OMAP44XX_PRM_REGADDR(inst, reg));
56}
57
58/* Write into a register in a CM/PRM instance in the PRM module */
59void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
60{
61 __raw_writel(val, OMAP44XX_PRM_REGADDR(inst, reg));
62}
63
64/* Read-modify-write a register in a PRM module. Caller must lock */
65u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
66{
67 u32 v;
68
69 v = omap4_prm_read_inst_reg(inst, reg);
70 v &= ~mask;
71 v |= bits;
72 omap4_prm_write_inst_reg(v, inst, reg);
73
74 return v;
75}
76
77/* PRM VP */
78
79/*
80 * struct omap4_vp - OMAP4 VP register access description.
81 * @irqstatus_mpu: offset to IRQSTATUS_MPU register for VP
82 * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
83 */
84struct omap4_vp {
85 u32 irqstatus_mpu;
86 u32 tranxdone_status;
87};
88
89static struct omap4_vp omap4_vp[] = {
90 [OMAP4_VP_VDD_MPU_ID] = {
91 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
92 .tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
93 },
94 [OMAP4_VP_VDD_IVA_ID] = {
95 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
96 .tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
97 },
98 [OMAP4_VP_VDD_CORE_ID] = {
99 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
100 .tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
101 },
102};
103
104u32 omap4_prm_vp_check_txdone(u8 vp_id)
105{
106 struct omap4_vp *vp = &omap4_vp[vp_id];
107 u32 irqstatus;
108
109 irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
110 OMAP4430_PRM_OCP_SOCKET_INST,
111 vp->irqstatus_mpu);
112 return irqstatus & vp->tranxdone_status;
113}
114
115void omap4_prm_vp_clear_txdone(u8 vp_id)
116{
117 struct omap4_vp *vp = &omap4_vp[vp_id];
118
119 omap4_prminst_write_inst_reg(vp->tranxdone_status,
120 OMAP4430_PRM_PARTITION,
121 OMAP4430_PRM_OCP_SOCKET_INST,
122 vp->irqstatus_mpu);
123};
124
125u32 omap4_prm_vcvp_read(u8 offset)
126{
127 return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
128 OMAP4430_PRM_DEVICE_INST, offset);
129}
130
131void omap4_prm_vcvp_write(u32 val, u8 offset)
132{
133 omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION,
134 OMAP4430_PRM_DEVICE_INST, offset);
135}
136
137u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
138{
139 return omap4_prminst_rmw_inst_reg_bits(mask, bits,
140 OMAP4430_PRM_PARTITION,
141 OMAP4430_PRM_DEVICE_INST,
142 offset);
143}
144
145static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs)
146{
147 u32 mask, st;
148
149 /* XXX read mask from RAM? */
150 mask = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
151 irqen_offs);
152 st = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, irqst_offs);
153
154 return mask & st;
155}
156
157/**
158 * omap44xx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
159 * @events: ptr to two consecutive u32s, preallocated by caller
160 *
161 * Read PRM_IRQSTATUS_MPU* bits, AND'ed with the currently-enabled PRM
162 * MPU IRQs, and store the result into the two u32s pointed to by @events.
163 * No return value.
164 */
165void omap44xx_prm_read_pending_irqs(unsigned long *events)
166{
167 events[0] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_OFFSET,
168 OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
169
170 events[1] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_2_OFFSET,
171 OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET);
172}
173
174/**
175 * omap44xx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
176 *
177 * Force any buffered writes to the PRM IP block to complete. Needed
178 * by the PRM IRQ handler, which reads and writes directly to the IP
179 * block, to avoid race conditions after acknowledging or clearing IRQ
180 * bits. No return value.
181 */
182void omap44xx_prm_ocp_barrier(void)
183{
184 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
185 OMAP4_REVISION_PRM_OFFSET);
186}
187
188/**
189 * omap44xx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU* regs
190 * @saved_mask: ptr to a u32 array to save IRQENABLE bits
191 *
192 * Save the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers to
193 * @saved_mask. @saved_mask must be allocated by the caller.
194 * Intended to be used in the PRM interrupt handler suspend callback.
195 * The OCP barrier is needed to ensure the write to disable PRM
196 * interrupts reaches the PRM before returning; otherwise, spurious
197 * interrupts might occur. No return value.
198 */
199void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
200{
201 saved_mask[0] =
202 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
203 OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
204 saved_mask[1] =
205 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
206 OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET);
207
208 omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST,
209 OMAP4_PRM_IRQENABLE_MPU_OFFSET);
210 omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST,
211 OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
212
213 /* OCP barrier */
214 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
215 OMAP4_REVISION_PRM_OFFSET);
216}
217
218/**
219 * omap44xx_prm_restore_irqen - set PRM_IRQENABLE_MPU* registers from args
220 * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
221 *
222 * Restore the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers from
223 * @saved_mask. Intended to be used in the PRM interrupt handler resume
224 * callback to restore values saved by omap44xx_prm_save_and_clear_irqen().
225 * No OCP barrier should be needed here; any pending PRM interrupts will fire
226 * once the writes reach the PRM. No return value.
227 */
228void omap44xx_prm_restore_irqen(u32 *saved_mask)
229{
230 omap4_prm_write_inst_reg(saved_mask[0], OMAP4430_PRM_OCP_SOCKET_INST,
231 OMAP4_PRM_IRQENABLE_MPU_OFFSET);
232 omap4_prm_write_inst_reg(saved_mask[1], OMAP4430_PRM_OCP_SOCKET_INST,
233 OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
234}
235
236static int __init omap4xxx_prcm_init(void)
237{
238 if (cpu_is_omap44xx())
239 return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
240 return 0;
241}
242subsys_initcall(omap4xxx_prcm_init);
1/*
2 * OMAP4 PRM module functions
3 *
4 * Copyright (C) 2011-2012 Texas Instruments, Inc.
5 * Copyright (C) 2010 Nokia Corporation
6 * Benoît Cousson
7 * Paul Walmsley
8 * Rajendra Nayak <rnayak@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/delay.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/io.h>
20#include <linux/of_irq.h>
21#include <linux/of.h>
22
23#include "soc.h"
24#include "iomap.h"
25#include "common.h"
26#include "vp.h"
27#include "prm44xx.h"
28#include "prcm43xx.h"
29#include "prm-regbits-44xx.h"
30#include "prcm44xx.h"
31#include "prminst44xx.h"
32#include "powerdomain.h"
33
34/* Static data */
35
36static void omap44xx_prm_read_pending_irqs(unsigned long *events);
37static void omap44xx_prm_ocp_barrier(void);
38static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
39static void omap44xx_prm_restore_irqen(u32 *saved_mask);
40static void omap44xx_prm_reconfigure_io_chain(void);
41
42static const struct omap_prcm_irq omap4_prcm_irqs[] = {
43 OMAP_PRCM_IRQ("io", 9, 1),
44};
45
46static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
47 .ack = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
48 .mask = OMAP4_PRM_IRQENABLE_MPU_OFFSET,
49 .pm_ctrl = OMAP4_PRM_IO_PMCTRL_OFFSET,
50 .nr_regs = 2,
51 .irqs = omap4_prcm_irqs,
52 .nr_irqs = ARRAY_SIZE(omap4_prcm_irqs),
53 .read_pending_irqs = &omap44xx_prm_read_pending_irqs,
54 .ocp_barrier = &omap44xx_prm_ocp_barrier,
55 .save_and_clear_irqen = &omap44xx_prm_save_and_clear_irqen,
56 .restore_irqen = &omap44xx_prm_restore_irqen,
57 .reconfigure_io_chain = &omap44xx_prm_reconfigure_io_chain,
58};
59
60/*
61 * omap44xx_prm_reset_src_map - map from bits in the PRM_RSTST
62 * hardware register (which are specific to OMAP44xx SoCs) to reset
63 * source ID bit shifts (which is an OMAP SoC-independent
64 * enumeration)
65 */
66static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = {
67 { OMAP4430_GLOBAL_WARM_SW_RST_SHIFT,
68 OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },
69 { OMAP4430_GLOBAL_COLD_RST_SHIFT,
70 OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },
71 { OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT,
72 OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },
73 { OMAP4430_MPU_WDT_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
74 { OMAP4430_SECURE_WDT_RST_SHIFT, OMAP_SECU_WD_RST_SRC_ID_SHIFT },
75 { OMAP4430_EXTERNAL_WARM_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT },
76 { OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT,
77 OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT },
78 { OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT,
79 OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT },
80 { OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT,
81 OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT },
82 { OMAP4430_ICEPICK_RST_SHIFT, OMAP_ICEPICK_RST_SRC_ID_SHIFT },
83 { OMAP4430_C2C_RST_SHIFT, OMAP_C2C_RST_SRC_ID_SHIFT },
84 { -1, -1 },
85};
86
87/* PRM low-level functions */
88
89/* Read a register in a CM/PRM instance in the PRM module */
90static u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
91{
92 return readl_relaxed(prm_base.va + inst + reg);
93}
94
95/* Write into a register in a CM/PRM instance in the PRM module */
96static void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
97{
98 writel_relaxed(val, prm_base.va + inst + reg);
99}
100
101/* Read-modify-write a register in a PRM module. Caller must lock */
102static u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
103{
104 u32 v;
105
106 v = omap4_prm_read_inst_reg(inst, reg);
107 v &= ~mask;
108 v |= bits;
109 omap4_prm_write_inst_reg(v, inst, reg);
110
111 return v;
112}
113
114/* PRM VP */
115
116/*
117 * struct omap4_vp - OMAP4 VP register access description.
118 * @irqstatus_mpu: offset to IRQSTATUS_MPU register for VP
119 * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
120 */
121struct omap4_vp {
122 u32 irqstatus_mpu;
123 u32 tranxdone_status;
124};
125
126static struct omap4_vp omap4_vp[] = {
127 [OMAP4_VP_VDD_MPU_ID] = {
128 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
129 .tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
130 },
131 [OMAP4_VP_VDD_IVA_ID] = {
132 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
133 .tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
134 },
135 [OMAP4_VP_VDD_CORE_ID] = {
136 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
137 .tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
138 },
139};
140
141static u32 omap4_prm_vp_check_txdone(u8 vp_id)
142{
143 struct omap4_vp *vp = &omap4_vp[vp_id];
144 u32 irqstatus;
145
146 irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
147 OMAP4430_PRM_OCP_SOCKET_INST,
148 vp->irqstatus_mpu);
149 return irqstatus & vp->tranxdone_status;
150}
151
152static void omap4_prm_vp_clear_txdone(u8 vp_id)
153{
154 struct omap4_vp *vp = &omap4_vp[vp_id];
155
156 omap4_prminst_write_inst_reg(vp->tranxdone_status,
157 OMAP4430_PRM_PARTITION,
158 OMAP4430_PRM_OCP_SOCKET_INST,
159 vp->irqstatus_mpu);
160};
161
162u32 omap4_prm_vcvp_read(u8 offset)
163{
164 s32 inst = omap4_prmst_get_prm_dev_inst();
165
166 if (inst == PRM_INSTANCE_UNKNOWN)
167 return 0;
168
169 return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
170 inst, offset);
171}
172
173void omap4_prm_vcvp_write(u32 val, u8 offset)
174{
175 s32 inst = omap4_prmst_get_prm_dev_inst();
176
177 if (inst == PRM_INSTANCE_UNKNOWN)
178 return;
179
180 omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION,
181 inst, offset);
182}
183
184u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
185{
186 s32 inst = omap4_prmst_get_prm_dev_inst();
187
188 if (inst == PRM_INSTANCE_UNKNOWN)
189 return 0;
190
191 return omap4_prminst_rmw_inst_reg_bits(mask, bits,
192 OMAP4430_PRM_PARTITION,
193 inst,
194 offset);
195}
196
197static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs)
198{
199 u32 mask, st;
200
201 /* XXX read mask from RAM? */
202 mask = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
203 irqen_offs);
204 st = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, irqst_offs);
205
206 return mask & st;
207}
208
209/**
210 * omap44xx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
211 * @events: ptr to two consecutive u32s, preallocated by caller
212 *
213 * Read PRM_IRQSTATUS_MPU* bits, AND'ed with the currently-enabled PRM
214 * MPU IRQs, and store the result into the two u32s pointed to by @events.
215 * No return value.
216 */
217static void omap44xx_prm_read_pending_irqs(unsigned long *events)
218{
219 int i;
220
221 for (i = 0; i < omap4_prcm_irq_setup.nr_regs; i++)
222 events[i] = _read_pending_irq_reg(omap4_prcm_irq_setup.mask +
223 i * 4, omap4_prcm_irq_setup.ack + i * 4);
224}
225
226/**
227 * omap44xx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
228 *
229 * Force any buffered writes to the PRM IP block to complete. Needed
230 * by the PRM IRQ handler, which reads and writes directly to the IP
231 * block, to avoid race conditions after acknowledging or clearing IRQ
232 * bits. No return value.
233 */
234static void omap44xx_prm_ocp_barrier(void)
235{
236 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
237 OMAP4_REVISION_PRM_OFFSET);
238}
239
240/**
241 * omap44xx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU* regs
242 * @saved_mask: ptr to a u32 array to save IRQENABLE bits
243 *
244 * Save the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers to
245 * @saved_mask. @saved_mask must be allocated by the caller.
246 * Intended to be used in the PRM interrupt handler suspend callback.
247 * The OCP barrier is needed to ensure the write to disable PRM
248 * interrupts reaches the PRM before returning; otherwise, spurious
249 * interrupts might occur. No return value.
250 */
251static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
252{
253 int i;
254 u16 reg;
255
256 for (i = 0; i < omap4_prcm_irq_setup.nr_regs; i++) {
257 reg = omap4_prcm_irq_setup.mask + i * 4;
258
259 saved_mask[i] =
260 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
261 reg);
262 omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST, reg);
263 }
264
265 /* OCP barrier */
266 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
267 OMAP4_REVISION_PRM_OFFSET);
268}
269
270/**
271 * omap44xx_prm_restore_irqen - set PRM_IRQENABLE_MPU* registers from args
272 * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
273 *
274 * Restore the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers from
275 * @saved_mask. Intended to be used in the PRM interrupt handler resume
276 * callback to restore values saved by omap44xx_prm_save_and_clear_irqen().
277 * No OCP barrier should be needed here; any pending PRM interrupts will fire
278 * once the writes reach the PRM. No return value.
279 */
280static void omap44xx_prm_restore_irqen(u32 *saved_mask)
281{
282 int i;
283
284 for (i = 0; i < omap4_prcm_irq_setup.nr_regs; i++)
285 omap4_prm_write_inst_reg(saved_mask[i],
286 OMAP4430_PRM_OCP_SOCKET_INST,
287 omap4_prcm_irq_setup.mask + i * 4);
288}
289
290/**
291 * omap44xx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
292 *
293 * Clear any previously-latched I/O wakeup events and ensure that the
294 * I/O wakeup gates are aligned with the current mux settings. Works
295 * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then
296 * deasserting WUCLKIN and waiting for WUCLKOUT to be deasserted.
297 * No return value. XXX Are the final two steps necessary?
298 */
299static void omap44xx_prm_reconfigure_io_chain(void)
300{
301 int i = 0;
302 s32 inst = omap4_prmst_get_prm_dev_inst();
303
304 if (inst == PRM_INSTANCE_UNKNOWN)
305 return;
306
307 /* Trigger WUCLKIN enable */
308 omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK,
309 OMAP4430_WUCLK_CTRL_MASK,
310 inst,
311 omap4_prcm_irq_setup.pm_ctrl);
312 omap_test_timeout(
313 (((omap4_prm_read_inst_reg(inst,
314 omap4_prcm_irq_setup.pm_ctrl) &
315 OMAP4430_WUCLK_STATUS_MASK) >>
316 OMAP4430_WUCLK_STATUS_SHIFT) == 1),
317 MAX_IOPAD_LATCH_TIME, i);
318 if (i == MAX_IOPAD_LATCH_TIME)
319 pr_warn("PRM: I/O chain clock line assertion timed out\n");
320
321 /* Trigger WUCLKIN disable */
322 omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 0x0,
323 inst,
324 omap4_prcm_irq_setup.pm_ctrl);
325 omap_test_timeout(
326 (((omap4_prm_read_inst_reg(inst,
327 omap4_prcm_irq_setup.pm_ctrl) &
328 OMAP4430_WUCLK_STATUS_MASK) >>
329 OMAP4430_WUCLK_STATUS_SHIFT) == 0),
330 MAX_IOPAD_LATCH_TIME, i);
331 if (i == MAX_IOPAD_LATCH_TIME)
332 pr_warn("PRM: I/O chain clock line deassertion timed out\n");
333
334 return;
335}
336
337/**
338 * omap44xx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
339 *
340 * Activates the I/O wakeup event latches and allows events logged by
341 * those latches to signal a wakeup event to the PRCM. For I/O wakeups
342 * to occur, WAKEUPENABLE bits must be set in the pad mux registers, and
343 * omap44xx_prm_reconfigure_io_chain() must be called. No return value.
344 */
345static void __init omap44xx_prm_enable_io_wakeup(void)
346{
347 s32 inst = omap4_prmst_get_prm_dev_inst();
348
349 if (inst == PRM_INSTANCE_UNKNOWN)
350 return;
351
352 omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
353 OMAP4430_GLOBAL_WUEN_MASK,
354 inst,
355 omap4_prcm_irq_setup.pm_ctrl);
356}
357
358/**
359 * omap44xx_prm_read_reset_sources - return the last SoC reset source
360 *
361 * Return a u32 representing the last reset sources of the SoC. The
362 * returned reset source bits are standardized across OMAP SoCs.
363 */
364static u32 omap44xx_prm_read_reset_sources(void)
365{
366 struct prm_reset_src_map *p;
367 u32 r = 0;
368 u32 v;
369 s32 inst = omap4_prmst_get_prm_dev_inst();
370
371 if (inst == PRM_INSTANCE_UNKNOWN)
372 return 0;
373
374
375 v = omap4_prm_read_inst_reg(inst,
376 OMAP4_RM_RSTST);
377
378 p = omap44xx_prm_reset_src_map;
379 while (p->reg_shift >= 0 && p->std_shift >= 0) {
380 if (v & (1 << p->reg_shift))
381 r |= 1 << p->std_shift;
382 p++;
383 }
384
385 return r;
386}
387
388/**
389 * omap44xx_prm_was_any_context_lost_old - was module hardware context lost?
390 * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
391 * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
392 * @idx: CONTEXT register offset
393 *
394 * Return 1 if any bits were set in the *_CONTEXT_* register
395 * identified by (@part, @inst, @idx), which means that some context
396 * was lost for that module; otherwise, return 0.
397 */
398static bool omap44xx_prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx)
399{
400 return (omap4_prminst_read_inst_reg(part, inst, idx)) ? 1 : 0;
401}
402
403/**
404 * omap44xx_prm_clear_context_lost_flags_old - clear context loss flags
405 * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
406 * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
407 * @idx: CONTEXT register offset
408 *
409 * Clear hardware context loss bits for the module identified by
410 * (@part, @inst, @idx). No return value. XXX Writes to reserved bits;
411 * is there a way to avoid this?
412 */
413static void omap44xx_prm_clear_context_loss_flags_old(u8 part, s16 inst,
414 u16 idx)
415{
416 omap4_prminst_write_inst_reg(0xffffffff, part, inst, idx);
417}
418
419/* Powerdomain low-level functions */
420
421static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
422{
423 omap4_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK,
424 (pwrst << OMAP_POWERSTATE_SHIFT),
425 pwrdm->prcm_partition,
426 pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
427 return 0;
428}
429
430static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
431{
432 u32 v;
433
434 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
435 OMAP4_PM_PWSTCTRL);
436 v &= OMAP_POWERSTATE_MASK;
437 v >>= OMAP_POWERSTATE_SHIFT;
438
439 return v;
440}
441
442static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm)
443{
444 u32 v;
445
446 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
447 OMAP4_PM_PWSTST);
448 v &= OMAP_POWERSTATEST_MASK;
449 v >>= OMAP_POWERSTATEST_SHIFT;
450
451 return v;
452}
453
454static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
455{
456 u32 v;
457
458 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
459 OMAP4_PM_PWSTST);
460 v &= OMAP4430_LASTPOWERSTATEENTERED_MASK;
461 v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT;
462
463 return v;
464}
465
466static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
467{
468 omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
469 (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
470 pwrdm->prcm_partition,
471 pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
472 return 0;
473}
474
475static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
476{
477 omap4_prminst_rmw_inst_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK,
478 OMAP4430_LASTPOWERSTATEENTERED_MASK,
479 pwrdm->prcm_partition,
480 pwrdm->prcm_offs, OMAP4_PM_PWSTST);
481 return 0;
482}
483
484static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
485{
486 u32 v;
487
488 v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK);
489 omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v,
490 pwrdm->prcm_partition, pwrdm->prcm_offs,
491 OMAP4_PM_PWSTCTRL);
492
493 return 0;
494}
495
496static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
497 u8 pwrst)
498{
499 u32 m;
500
501 m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
502
503 omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
504 pwrdm->prcm_partition, pwrdm->prcm_offs,
505 OMAP4_PM_PWSTCTRL);
506
507 return 0;
508}
509
510static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
511 u8 pwrst)
512{
513 u32 m;
514
515 m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
516
517 omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
518 pwrdm->prcm_partition, pwrdm->prcm_offs,
519 OMAP4_PM_PWSTCTRL);
520
521 return 0;
522}
523
524static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
525{
526 u32 v;
527
528 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
529 OMAP4_PM_PWSTST);
530 v &= OMAP4430_LOGICSTATEST_MASK;
531 v >>= OMAP4430_LOGICSTATEST_SHIFT;
532
533 return v;
534}
535
536static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
537{
538 u32 v;
539
540 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
541 OMAP4_PM_PWSTCTRL);
542 v &= OMAP4430_LOGICRETSTATE_MASK;
543 v >>= OMAP4430_LOGICRETSTATE_SHIFT;
544
545 return v;
546}
547
548/**
549 * omap4_pwrdm_read_prev_logic_pwrst - read the previous logic powerstate
550 * @pwrdm: struct powerdomain * to read the state for
551 *
552 * Reads the previous logic powerstate for a powerdomain. This
553 * function must determine the previous logic powerstate by first
554 * checking the previous powerstate for the domain. If that was OFF,
555 * then logic has been lost. If previous state was RETENTION, the
556 * function reads the setting for the next retention logic state to
557 * see the actual value. In every other case, the logic is
558 * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
559 * depending whether the logic was retained or not.
560 */
561static int omap4_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
562{
563 int state;
564
565 state = omap4_pwrdm_read_prev_pwrst(pwrdm);
566
567 if (state == PWRDM_POWER_OFF)
568 return PWRDM_POWER_OFF;
569
570 if (state != PWRDM_POWER_RET)
571 return PWRDM_POWER_RET;
572
573 return omap4_pwrdm_read_logic_retst(pwrdm);
574}
575
576static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
577{
578 u32 m, v;
579
580 m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
581
582 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
583 OMAP4_PM_PWSTST);
584 v &= m;
585 v >>= __ffs(m);
586
587 return v;
588}
589
590static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
591{
592 u32 m, v;
593
594 m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
595
596 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
597 OMAP4_PM_PWSTCTRL);
598 v &= m;
599 v >>= __ffs(m);
600
601 return v;
602}
603
604/**
605 * omap4_pwrdm_read_prev_mem_pwrst - reads the previous memory powerstate
606 * @pwrdm: struct powerdomain * to read mem powerstate for
607 * @bank: memory bank index
608 *
609 * Reads the previous memory powerstate for a powerdomain. This
610 * function must determine the previous memory powerstate by first
611 * checking the previous powerstate for the domain. If that was OFF,
612 * then logic has been lost. If previous state was RETENTION, the
613 * function reads the setting for the next memory retention state to
614 * see the actual value. In every other case, the logic is
615 * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
616 * depending whether logic was retained or not.
617 */
618static int omap4_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
619{
620 int state;
621
622 state = omap4_pwrdm_read_prev_pwrst(pwrdm);
623
624 if (state == PWRDM_POWER_OFF)
625 return PWRDM_POWER_OFF;
626
627 if (state != PWRDM_POWER_RET)
628 return PWRDM_POWER_RET;
629
630 return omap4_pwrdm_read_mem_retst(pwrdm, bank);
631}
632
633static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
634{
635 u32 c = 0;
636
637 /*
638 * REVISIT: pwrdm_wait_transition() may be better implemented
639 * via a callback and a periodic timer check -- how long do we expect
640 * powerdomain transitions to take?
641 */
642
643 /* XXX Is this udelay() value meaningful? */
644 while ((omap4_prminst_read_inst_reg(pwrdm->prcm_partition,
645 pwrdm->prcm_offs,
646 OMAP4_PM_PWSTST) &
647 OMAP_INTRANSITION_MASK) &&
648 (c++ < PWRDM_TRANSITION_BAILOUT))
649 udelay(1);
650
651 if (c > PWRDM_TRANSITION_BAILOUT) {
652 pr_err("powerdomain: %s: waited too long to complete transition\n",
653 pwrdm->name);
654 return -EAGAIN;
655 }
656
657 pr_debug("powerdomain: completed transition in %d loops\n", c);
658
659 return 0;
660}
661
662static int omap4_check_vcvp(void)
663{
664 if (prm_features & PRM_HAS_VOLTAGE)
665 return 1;
666
667 return 0;
668}
669
670struct pwrdm_ops omap4_pwrdm_operations = {
671 .pwrdm_set_next_pwrst = omap4_pwrdm_set_next_pwrst,
672 .pwrdm_read_next_pwrst = omap4_pwrdm_read_next_pwrst,
673 .pwrdm_read_pwrst = omap4_pwrdm_read_pwrst,
674 .pwrdm_read_prev_pwrst = omap4_pwrdm_read_prev_pwrst,
675 .pwrdm_set_lowpwrstchange = omap4_pwrdm_set_lowpwrstchange,
676 .pwrdm_clear_all_prev_pwrst = omap4_pwrdm_clear_all_prev_pwrst,
677 .pwrdm_set_logic_retst = omap4_pwrdm_set_logic_retst,
678 .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst,
679 .pwrdm_read_prev_logic_pwrst = omap4_pwrdm_read_prev_logic_pwrst,
680 .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst,
681 .pwrdm_read_mem_pwrst = omap4_pwrdm_read_mem_pwrst,
682 .pwrdm_read_mem_retst = omap4_pwrdm_read_mem_retst,
683 .pwrdm_read_prev_mem_pwrst = omap4_pwrdm_read_prev_mem_pwrst,
684 .pwrdm_set_mem_onst = omap4_pwrdm_set_mem_onst,
685 .pwrdm_set_mem_retst = omap4_pwrdm_set_mem_retst,
686 .pwrdm_wait_transition = omap4_pwrdm_wait_transition,
687 .pwrdm_has_voltdm = omap4_check_vcvp,
688};
689
690static int omap44xx_prm_late_init(void);
691
692/*
693 * XXX document
694 */
695static struct prm_ll_data omap44xx_prm_ll_data = {
696 .read_reset_sources = &omap44xx_prm_read_reset_sources,
697 .was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old,
698 .clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old,
699 .late_init = &omap44xx_prm_late_init,
700 .assert_hardreset = omap4_prminst_assert_hardreset,
701 .deassert_hardreset = omap4_prminst_deassert_hardreset,
702 .is_hardreset_asserted = omap4_prminst_is_hardreset_asserted,
703 .reset_system = omap4_prminst_global_warm_sw_reset,
704 .vp_check_txdone = omap4_prm_vp_check_txdone,
705 .vp_clear_txdone = omap4_prm_vp_clear_txdone,
706};
707
708static const struct omap_prcm_init_data *prm_init_data;
709
710int __init omap44xx_prm_init(const struct omap_prcm_init_data *data)
711{
712 omap_prm_base_init();
713
714 prm_init_data = data;
715
716 if (data->flags & PRM_HAS_IO_WAKEUP)
717 prm_features |= PRM_HAS_IO_WAKEUP;
718
719 if (data->flags & PRM_HAS_VOLTAGE)
720 prm_features |= PRM_HAS_VOLTAGE;
721
722 omap4_prminst_set_prm_dev_inst(data->device_inst_offset);
723
724 /* Add AM437X specific differences */
725 if (of_device_is_compatible(data->np, "ti,am4-prcm")) {
726 omap4_prcm_irq_setup.nr_irqs = 1;
727 omap4_prcm_irq_setup.nr_regs = 1;
728 omap4_prcm_irq_setup.pm_ctrl = AM43XX_PRM_IO_PMCTRL_OFFSET;
729 omap4_prcm_irq_setup.ack = AM43XX_PRM_IRQSTATUS_MPU_OFFSET;
730 omap4_prcm_irq_setup.mask = AM43XX_PRM_IRQENABLE_MPU_OFFSET;
731 }
732
733 return prm_register(&omap44xx_prm_ll_data);
734}
735
736static int omap44xx_prm_late_init(void)
737{
738 int irq_num;
739
740 if (!(prm_features & PRM_HAS_IO_WAKEUP))
741 return 0;
742
743 irq_num = of_irq_get(prm_init_data->np, 0);
744 if (irq_num == -EPROBE_DEFER)
745 return irq_num;
746
747 omap4_prcm_irq_setup.irq = irq_num;
748
749 omap44xx_prm_enable_io_wakeup();
750
751 return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
752}
753
754static void __exit omap44xx_prm_exit(void)
755{
756 prm_unregister(&omap44xx_prm_ll_data);
757}
758__exitcall(omap44xx_prm_exit);