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1/*
2 * OMAP2/3 Power/Reset Management (PRM) register definitions
3 *
4 * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
5 * Copyright (C) 2008-2010 Nokia Corporation
6 * Paul Walmsley
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * The PRM hardware modules on the OMAP2/3 are quite similar to each
13 * other. The PRM on OMAP4 has a new register layout, and is handled
14 * in a separate file.
15 */
16#ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H
17#define __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H
18
19#include "prcm-common.h"
20#include "prm.h"
21
22#define OMAP2420_PRM_REGADDR(module, reg) \
23 OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
24#define OMAP2430_PRM_REGADDR(module, reg) \
25 OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
26#define OMAP34XX_PRM_REGADDR(module, reg) \
27 OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
28
29
30/*
31 * OMAP2-specific global PRM registers
32 * Use __raw_{read,write}l() with these registers.
33 *
34 * With a few exceptions, these are the register names beginning with
35 * PRCM_* on 24xx. (The exceptions are the IRQSTATUS and IRQENABLE
36 * bits.)
37 *
38 */
39
40#define OMAP2_PRCM_REVISION_OFFSET 0x0000
41#define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
42#define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010
43#define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
44
45#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
46#define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
47#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
48#define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
49
50#define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050
51#define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
52#define OMAP2_PRCM_VOLTST_OFFSET 0x0054
53#define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
54#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060
55#define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
56#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070
57#define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
58#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078
59#define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
60#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080
61#define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
62#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
63#define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
64#define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090
65#define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
66#define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094
67#define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
68#define OMAP2_PRCM_POLCTRL_OFFSET 0x0098
69#define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
70
71#define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
72#define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
73
74#define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
75#define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
76
77#define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
78#define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
79#define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
80#define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
81#define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
82#define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
83#define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
84#define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
85#define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
86#define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
87
88/*
89 * OMAP3-specific global PRM registers
90 * Use __raw_{read,write}l() with these registers.
91 *
92 * With a few exceptions, these are the register names beginning with
93 * PRM_* on 34xx. (The exceptions are the IRQSTATUS and IRQENABLE
94 * bits.)
95 */
96
97#define OMAP3_PRM_REVISION_OFFSET 0x0004
98#define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
99#define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014
100#define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
101
102#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018
103#define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
104#define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c
105#define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
106
107
108#define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
109#define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
110#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024
111#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
112#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028
113#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
114#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c
115#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
116#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030
117#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
118#define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034
119#define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
120#define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038
121#define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
122#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c
123#define OMAP3430_PRM_VC_BYPASS_VAL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
124#define OMAP3_PRM_RSTCTRL_OFFSET 0x0050
125#define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
126#define OMAP3_PRM_RSTTIME_OFFSET 0x0054
127#define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
128#define OMAP3_PRM_RSTST_OFFSET 0x0058
129#define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
130#define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060
131#define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
132#define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064
133#define OMAP3430_PRM_SRAM_PCHARGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
134#define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070
135#define OMAP3430_PRM_CLKSRC_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
136#define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090
137#define OMAP3430_PRM_VOLTSETUP1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
138#define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094
139#define OMAP3430_PRM_VOLTOFFSET OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
140#define OMAP3_PRM_CLKSETUP_OFFSET 0x0098
141#define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
142#define OMAP3_PRM_POLCTRL_OFFSET 0x009c
143#define OMAP3430_PRM_POLCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
144#define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0
145#define OMAP3430_PRM_VOLTSETUP2 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
146#define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0
147#define OMAP3430_PRM_VP1_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
148#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4
149#define OMAP3430_PRM_VP1_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
150#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8
151#define OMAP3430_PRM_VP1_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
152#define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc
153#define OMAP3430_PRM_VP1_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
154#define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0
155#define OMAP3430_PRM_VP1_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
156#define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4
157#define OMAP3430_PRM_VP1_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
158#define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0
159#define OMAP3430_PRM_VP2_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
160#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4
161#define OMAP3430_PRM_VP2_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
162#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8
163#define OMAP3430_PRM_VP2_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
164#define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc
165#define OMAP3430_PRM_VP2_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
166#define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0
167#define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
168#define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4
169#define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
170
171#define OMAP3_PRM_CLKSEL_OFFSET 0x0040
172#define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
173#define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070
174#define OMAP3430_PRM_CLKOUT_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
175
176/*
177 * Module specific PRM register offsets from PRM_BASE + domain offset
178 *
179 * Use prm_{read,write}_mod_reg() with these registers.
180 *
181 * With a few exceptions, these are the register names beginning with
182 * {PM,RM}_* on both OMAP2/3 SoC families.. (The exceptions are the
183 * IRQSTATUS and IRQENABLE bits.)
184 */
185
186/* Register offsets appearing on both OMAP2 and OMAP3 */
187
188#define OMAP2_RM_RSTCTRL 0x0050
189#define OMAP2_RM_RSTTIME 0x0054
190#define OMAP2_RM_RSTST 0x0058
191#define OMAP2_PM_PWSTCTRL 0x00e0
192#define OMAP2_PM_PWSTST 0x00e4
193
194#define PM_WKEN 0x00a0
195#define PM_WKEN1 PM_WKEN
196#define PM_WKST 0x00b0
197#define PM_WKST1 PM_WKST
198#define PM_WKDEP 0x00c8
199#define PM_EVGENCTRL 0x00d4
200#define PM_EVGENONTIM 0x00d8
201#define PM_EVGENOFFTIM 0x00dc
202
203/* OMAP2xxx specific register offsets */
204#define OMAP24XX_PM_WKEN2 0x00a4
205#define OMAP24XX_PM_WKST2 0x00b4
206
207#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */
208#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */
209#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8
210#define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc
211
212/* OMAP3 specific register offsets */
213#define OMAP3430ES2_PM_WKEN3 0x00f0
214#define OMAP3430ES2_PM_WKST3 0x00b8
215
216#define OMAP3430_PM_MPUGRPSEL 0x00a4
217#define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL
218#define OMAP3430ES2_PM_MPUGRPSEL3 0x00f8
219
220#define OMAP3430_PM_IVAGRPSEL 0x00a8
221#define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL
222#define OMAP3430ES2_PM_IVAGRPSEL3 0x00f4
223
224#define OMAP3430_PM_PREPWSTST 0x00e8
225
226#define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8
227#define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc
228
229
230#ifndef __ASSEMBLER__
231/*
232 * Stub omap2xxx/omap3xxx functions so that common files
233 * continue to build when custom builds are used
234 */
235#if defined(CONFIG_ARCH_OMAP4) && !(defined(CONFIG_ARCH_OMAP2) || \
236 defined(CONFIG_ARCH_OMAP3))
237static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
238{
239 WARN(1, "prm: omap2xxx/omap3xxx specific function and "
240 "not suppose to be used on omap4\n");
241 return 0;
242}
243static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
244{
245 WARN(1, "prm: omap2xxx/omap3xxx specific function and "
246 "not suppose to be used on omap4\n");
247}
248static inline u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits,
249 s16 module, s16 idx)
250{
251 WARN(1, "prm: omap2xxx/omap3xxx specific function and "
252 "not suppose to be used on omap4\n");
253 return 0;
254}
255static inline u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
256{
257 WARN(1, "prm: omap2xxx/omap3xxx specific function and "
258 "not suppose to be used on omap4\n");
259 return 0;
260}
261static inline u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
262{
263 WARN(1, "prm: omap2xxx/omap3xxx specific function and "
264 "not suppose to be used on omap4\n");
265 return 0;
266}
267static inline u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
268{
269 WARN(1, "prm: omap2xxx/omap3xxx specific function and "
270 "not suppose to be used on omap4\n");
271 return 0;
272}
273static inline int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
274{
275 WARN(1, "prm: omap2xxx/omap3xxx specific function and "
276 "not suppose to be used on omap4\n");
277 return 0;
278}
279static inline int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
280{
281 WARN(1, "prm: omap2xxx/omap3xxx specific function and "
282 "not suppose to be used on omap4\n");
283 return 0;
284}
285static inline int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift,
286 u8 st_shift)
287{
288 WARN(1, "prm: omap2xxx/omap3xxx specific function and "
289 "not suppose to be used on omap4\n");
290 return 0;
291}
292#else
293/* Power/reset management domain register get/set */
294extern u32 omap2_prm_read_mod_reg(s16 module, u16 idx);
295extern void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx);
296extern u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
297extern u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx);
298extern u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx);
299extern u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask);
300
301/* These omap2_ PRM functions apply to both OMAP2 and 3 */
302extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
303extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
304extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift);
305
306/* OMAP3-specific VP functions */
307u32 omap3_prm_vp_check_txdone(u8 vp_id);
308void omap3_prm_vp_clear_txdone(u8 vp_id);
309
310/*
311 * OMAP3 access functions for voltage controller (VC) and
312 * voltage proccessor (VP) in the PRM.
313 */
314extern u32 omap3_prm_vcvp_read(u8 offset);
315extern void omap3_prm_vcvp_write(u32 val, u8 offset);
316extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
317
318/* PRM interrupt-related functions */
319extern void omap3xxx_prm_read_pending_irqs(unsigned long *events);
320extern void omap3xxx_prm_ocp_barrier(void);
321extern void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask);
322extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
323
324#endif /* CONFIG_ARCH_OMAP4 */
325
326#endif
327
328/*
329 * Bits common to specific registers
330 *
331 * The 3430 register and bit names are generally used,
332 * since they tend to make more sense
333 */
334
335/* PM_EVGENONTIM_MPU */
336/* Named PM_EVEGENONTIM_MPU on the 24XX */
337#define OMAP_ONTIMEVAL_SHIFT 0
338#define OMAP_ONTIMEVAL_MASK (0xffffffff << 0)
339
340/* PM_EVGENOFFTIM_MPU */
341/* Named PM_EVEGENOFFTIM_MPU on the 24XX */
342#define OMAP_OFFTIMEVAL_SHIFT 0
343#define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0)
344
345/* PRM_CLKSETUP and PRCM_VOLTSETUP */
346/* Named PRCM_CLKSSETUP on the 24XX */
347#define OMAP_SETUP_TIME_SHIFT 0
348#define OMAP_SETUP_TIME_MASK (0xffff << 0)
349
350/* PRM_CLKSRC_CTRL */
351/* Named PRCM_CLKSRC_CTRL on the 24XX */
352#define OMAP_SYSCLKDIV_SHIFT 6
353#define OMAP_SYSCLKDIV_MASK (0x3 << 6)
354#define OMAP_AUTOEXTCLKMODE_SHIFT 3
355#define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3)
356#define OMAP_SYSCLKSEL_SHIFT 0
357#define OMAP_SYSCLKSEL_MASK (0x3 << 0)
358
359/* PM_EVGENCTRL_MPU */
360#define OMAP_OFFLOADMODE_SHIFT 3
361#define OMAP_OFFLOADMODE_MASK (0x3 << 3)
362#define OMAP_ONLOADMODE_SHIFT 1
363#define OMAP_ONLOADMODE_MASK (0x3 << 1)
364#define OMAP_ENABLE_MASK (1 << 0)
365
366/* PRM_RSTTIME */
367/* Named RM_RSTTIME_WKUP on the 24xx */
368#define OMAP_RSTTIME2_SHIFT 8
369#define OMAP_RSTTIME2_MASK (0x1f << 8)
370#define OMAP_RSTTIME1_SHIFT 0
371#define OMAP_RSTTIME1_MASK (0xff << 0)
372
373/* PRM_RSTCTRL */
374/* Named RM_RSTCTRL_WKUP on the 24xx */
375/* 2420 calls RST_DPLL3 'RST_DPLL' */
376#define OMAP_RST_DPLL3_MASK (1 << 2)
377#define OMAP_RST_GS_MASK (1 << 1)
378
379
380/*
381 * Bits common to module-shared registers
382 *
383 * Not all registers of a particular type support all of these bits -
384 * check TRM if you are unsure
385 */
386
387/*
388 * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
389 * called 'COREWKUP_RST'
390 *
391 * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
392 * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
393 */
394#define OMAP_COREDOMAINWKUP_RST_MASK (1 << 3)
395
396/*
397 * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
398 *
399 * 2430: RM_RSTST_MDM
400 *
401 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
402 */
403#define OMAP_DOMAINWKUP_RST_MASK (1 << 2)
404
405/*
406 * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
407 * On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
408 *
409 * 2430: RM_RSTST_MDM
410 *
411 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
412 */
413#define OMAP_GLOBALWARM_RST_MASK (1 << 1)
414#define OMAP_GLOBALCOLD_RST_MASK (1 << 0)
415
416/*
417 * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
418 * 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
419 *
420 * 2430: PM_WKDEP_MDM
421 *
422 * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
423 * PM_WKDEP_PER
424 */
425#define OMAP_EN_WKUP_SHIFT 4
426#define OMAP_EN_WKUP_MASK (1 << 4)
427
428/*
429 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
430 * PM_PWSTCTRL_DSP
431 *
432 * 2430: PM_PWSTCTRL_MDM
433 *
434 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
435 * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
436 * PM_PWSTCTRL_NEON
437 */
438#define OMAP_LOGICRETSTATE_MASK (1 << 2)
439
440
441/*
442 * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
443 * submodule to exit hardreset
444 */
445#define MAX_MODULE_HARDRESET_WAIT 10000
446
447
448#endif
1/*
2 * OMAP2xxx/3xxx-common Power/Reset Management (PRM) register definitions
3 *
4 * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
5 * Copyright (C) 2008-2010 Nokia Corporation
6 * Paul Walmsley
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * The PRM hardware modules on the OMAP2/3 are quite similar to each
13 * other. The PRM on OMAP4 has a new register layout, and is handled
14 * in a separate file.
15 */
16#ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H
17#define __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H
18
19#include "prcm-common.h"
20#include "prm.h"
21
22/*
23 * Module specific PRM register offsets from PRM_BASE + domain offset
24 *
25 * Use prm_{read,write}_mod_reg() with these registers.
26 *
27 * With a few exceptions, these are the register names beginning with
28 * {PM,RM}_* on both OMAP2/3 SoC families.. (The exceptions are the
29 * IRQSTATUS and IRQENABLE bits.)
30 */
31
32/* Register offsets appearing on both OMAP2 and OMAP3 */
33
34#define OMAP2_RM_RSTCTRL 0x0050
35#define OMAP2_RM_RSTTIME 0x0054
36#define OMAP2_RM_RSTST 0x0058
37#define OMAP2_PM_PWSTCTRL 0x00e0
38#define OMAP2_PM_PWSTST 0x00e4
39
40#define PM_WKEN 0x00a0
41#define PM_WKEN1 PM_WKEN
42#define PM_WKST 0x00b0
43#define PM_WKST1 PM_WKST
44#define PM_WKDEP 0x00c8
45#define PM_EVGENCTRL 0x00d4
46#define PM_EVGENONTIM 0x00d8
47#define PM_EVGENOFFTIM 0x00dc
48
49
50#ifndef __ASSEMBLER__
51
52#include <linux/io.h>
53#include "powerdomain.h"
54
55/* Power/reset management domain register get/set */
56static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
57{
58 return readl_relaxed(prm_base.va + module + idx);
59}
60
61static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
62{
63 writel_relaxed(val, prm_base.va + module + idx);
64}
65
66/* Read-modify-write a register in a PRM module. Caller must lock */
67static inline u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module,
68 s16 idx)
69{
70 u32 v;
71
72 v = omap2_prm_read_mod_reg(module, idx);
73 v &= ~mask;
74 v |= bits;
75 omap2_prm_write_mod_reg(v, module, idx);
76
77 return v;
78}
79
80/* Read a PRM register, AND it, and shift the result down to bit 0 */
81static inline u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
82{
83 u32 v;
84
85 v = omap2_prm_read_mod_reg(domain, idx);
86 v &= mask;
87 v >>= __ffs(mask);
88
89 return v;
90}
91
92static inline u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
93{
94 return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx);
95}
96
97static inline u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
98{
99 return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
100}
101
102/* These omap2_ PRM functions apply to both OMAP2 and 3 */
103int omap2_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset);
104int omap2_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod,
105 u16 offset);
106int omap2_prm_deassert_hardreset(u8 rst_shift, u8 st_shift, u8 part,
107 s16 prm_mod, u16 reset_offset,
108 u16 st_offset);
109
110extern int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
111extern int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
112extern int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm);
113extern int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
114 u8 pwrst);
115extern int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
116 u8 pwrst);
117extern int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
118extern int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
119extern int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
120extern int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm);
121
122extern int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
123 struct clockdomain *clkdm2);
124extern int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
125 struct clockdomain *clkdm2);
126extern int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
127 struct clockdomain *clkdm2);
128extern int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm);
129
130#endif /* __ASSEMBLER */
131
132/*
133 * Bits common to specific registers
134 *
135 * The 3430 register and bit names are generally used,
136 * since they tend to make more sense
137 */
138
139/* PM_EVGENONTIM_MPU */
140/* Named PM_EVEGENONTIM_MPU on the 24XX */
141#define OMAP_ONTIMEVAL_SHIFT 0
142#define OMAP_ONTIMEVAL_MASK (0xffffffff << 0)
143
144/* PM_EVGENOFFTIM_MPU */
145/* Named PM_EVEGENOFFTIM_MPU on the 24XX */
146#define OMAP_OFFTIMEVAL_SHIFT 0
147#define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0)
148
149/* PRM_CLKSETUP and PRCM_VOLTSETUP */
150/* Named PRCM_CLKSSETUP on the 24XX */
151#define OMAP_SETUP_TIME_SHIFT 0
152#define OMAP_SETUP_TIME_MASK (0xffff << 0)
153
154/* PRM_CLKSRC_CTRL */
155/* Named PRCM_CLKSRC_CTRL on the 24XX */
156#define OMAP_SYSCLKDIV_SHIFT 6
157#define OMAP_SYSCLKDIV_MASK (0x3 << 6)
158#define OMAP_SYSCLKDIV_WIDTH 2
159#define OMAP_AUTOEXTCLKMODE_SHIFT 3
160#define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3)
161#define OMAP_SYSCLKSEL_SHIFT 0
162#define OMAP_SYSCLKSEL_MASK (0x3 << 0)
163
164/* PM_EVGENCTRL_MPU */
165#define OMAP_OFFLOADMODE_SHIFT 3
166#define OMAP_OFFLOADMODE_MASK (0x3 << 3)
167#define OMAP_ONLOADMODE_SHIFT 1
168#define OMAP_ONLOADMODE_MASK (0x3 << 1)
169#define OMAP_ENABLE_MASK (1 << 0)
170
171/* PRM_RSTTIME */
172/* Named RM_RSTTIME_WKUP on the 24xx */
173#define OMAP_RSTTIME2_SHIFT 8
174#define OMAP_RSTTIME2_MASK (0x1f << 8)
175#define OMAP_RSTTIME1_SHIFT 0
176#define OMAP_RSTTIME1_MASK (0xff << 0)
177
178/* PRM_RSTCTRL */
179/* Named RM_RSTCTRL_WKUP on the 24xx */
180/* 2420 calls RST_DPLL3 'RST_DPLL' */
181#define OMAP_RST_DPLL3_MASK (1 << 2)
182#define OMAP_RST_GS_MASK (1 << 1)
183
184
185/*
186 * Bits common to module-shared registers
187 *
188 * Not all registers of a particular type support all of these bits -
189 * check TRM if you are unsure
190 */
191
192/*
193 * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
194 * called 'COREWKUP_RST'
195 *
196 * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
197 * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
198 */
199#define OMAP_COREDOMAINWKUP_RST_MASK (1 << 3)
200
201/*
202 * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
203 *
204 * 2430: RM_RSTST_MDM
205 *
206 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
207 */
208#define OMAP_DOMAINWKUP_RST_MASK (1 << 2)
209
210/*
211 * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
212 * On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
213 *
214 * 2430: RM_RSTST_MDM
215 *
216 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
217 */
218#define OMAP_GLOBALWARM_RST_SHIFT 1
219#define OMAP_GLOBALWARM_RST_MASK (1 << 1)
220#define OMAP_GLOBALCOLD_RST_SHIFT 0
221#define OMAP_GLOBALCOLD_RST_MASK (1 << 0)
222
223/*
224 * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
225 * 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
226 *
227 * 2430: PM_WKDEP_MDM
228 *
229 * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
230 * PM_WKDEP_PER
231 */
232#define OMAP_EN_WKUP_SHIFT 4
233#define OMAP_EN_WKUP_MASK (1 << 4)
234
235/*
236 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
237 * PM_PWSTCTRL_DSP
238 *
239 * 2430: PM_PWSTCTRL_MDM
240 *
241 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
242 * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
243 * PM_PWSTCTRL_NEON
244 */
245#define OMAP_LOGICRETSTATE_MASK (1 << 2)
246
247
248#endif