1/*
  2 * linux/arch/arm/mach-omap2/prcm.c
  3 *
  4 * OMAP 24xx Power Reset and Clock Management (PRCM) functions
  5 *
  6 * Copyright (C) 2005 Nokia Corporation
  7 *
  8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
  9 *
 10 * Copyright (C) 2007 Texas Instruments, Inc.
 11 * Rajendra Nayak <rnayak@ti.com>
 12 *
 13 * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
 14 * Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com>
 15 *
 16 * This program is free software; you can redistribute it and/or modify
 17 * it under the terms of the GNU General Public License version 2 as
 18 * published by the Free Software Foundation.
 19 */
 20
 21#include <linux/kernel.h>
 22#include <linux/init.h>
 23#include <linux/clk.h>
 24#include <linux/io.h>
 25#include <linux/delay.h>
 26#include <linux/export.h>
 27
 28#include "common.h"
 29#include <plat/prcm.h>
 30#include <plat/irqs.h>
 31
 32#include "clock.h"
 33#include "clock2xxx.h"
 34#include "cm2xxx_3xxx.h"
 35#include "prm2xxx_3xxx.h"
 36#include "prm44xx.h"
 37#include "prminst44xx.h"
 38#include "prm-regbits-24xx.h"
 39#include "prm-regbits-44xx.h"
 40#include "control.h"
 41
 42void __iomem *prm_base;
 43void __iomem *cm_base;
 44void __iomem *cm2_base;
 45void __iomem *prcm_mpu_base;
 46
 47#define MAX_MODULE_ENABLE_WAIT		100000
 48
 49u32 omap_prcm_get_reset_sources(void)
 50{
 51	/* XXX This presumably needs modification for 34XX */
 52	if (cpu_is_omap24xx() || cpu_is_omap34xx())
 53		return omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
 54	if (cpu_is_omap44xx())
 55		return omap2_prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
 56
 57	return 0;
 58}
 59EXPORT_SYMBOL(omap_prcm_get_reset_sources);
 60
 61/* Resets clock rates and reboots the system. Only called from system.h */
 62void omap_prcm_restart(char mode, const char *cmd)
 63{
 64	s16 prcm_offs = 0;
 65
 66	if (cpu_is_omap24xx()) {
 67		omap2xxx_clk_prepare_for_reboot();
 68
 69		prcm_offs = WKUP_MOD;
 70	} else if (cpu_is_omap34xx()) {
 71		prcm_offs = OMAP3430_GR_MOD;
 72		omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
 73	} else if (cpu_is_omap44xx()) {
 74		omap4_prminst_global_warm_sw_reset(); /* never returns */
 75	} else {
 76		WARN_ON(1);
 77	}
 78
 79	/*
 80	 * As per Errata i520, in some cases, user will not be able to
 81	 * access DDR memory after warm-reset.
 82	 * This situation occurs while the warm-reset happens during a read
 83	 * access to DDR memory. In that particular condition, DDR memory
 84	 * does not respond to a corrupted read command due to the warm
 85	 * reset occurrence but SDRC is waiting for read completion.
 86	 * SDRC is not sensitive to the warm reset, but the interconnect is
 87	 * reset on the fly, thus causing a misalignment between SDRC logic,
 88	 * interconnect logic and DDR memory state.
 89	 * WORKAROUND:
 90	 * Steps to perform before a Warm reset is trigged:
 91	 * 1. enable self-refresh on idle request
 92	 * 2. put SDRC in idle
 93	 * 3. wait until SDRC goes to idle
 94	 * 4. generate SW reset (Global SW reset)
 95	 *
 96	 * Steps to be performed after warm reset occurs (in bootloader):
 97	 * if HW warm reset is the source, apply below steps before any
 98	 * accesses to SDRAM:
 99	 * 1. Reset SMS and SDRC and wait till reset is complete
100	 * 2. Re-initialize SMS, SDRC and memory
101	 *
102	 * NOTE: Above work around is required only if arch reset is implemented
103	 * using Global SW reset(GLOBAL_SW_RST). DPLL3 reset does not need
104	 * the WA since it resets SDRC as well as part of cold reset.
105	 */
106
107	/* XXX should be moved to some OMAP2/3 specific code */
108	omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
109				   OMAP2_RM_RSTCTRL);
110	omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */
111}
112
113/**
114 * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
115 * @reg: physical address of module IDLEST register
116 * @mask: value to mask against to determine if the module is active
117 * @idlest: idle state indicator (0 or 1) for the clock
118 * @name: name of the clock (for printk)
119 *
120 * Returns 1 if the module indicated readiness in time, or 0 if it
121 * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
122 *
123 * XXX This function is deprecated.  It should be removed once the
124 * hwmod conversion is complete.
125 */
126int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
127				const char *name)
128{
129	int i = 0;
130	int ena = 0;
131
132	if (idlest)
133		ena = 0;
134	else
135		ena = mask;
136
137	/* Wait for lock */
138	omap_test_timeout(((__raw_readl(reg) & mask) == ena),
139			  MAX_MODULE_ENABLE_WAIT, i);
140
141	if (i < MAX_MODULE_ENABLE_WAIT)
142		pr_debug("cm: Module associated with clock %s ready after %d "
143			 "loops\n", name, i);
144	else
145		pr_err("cm: Module associated with clock %s didn't enable in "
146		       "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
147
148	return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
149};
150
151void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
152{
153	if (omap2_globals->prm)
154		prm_base = omap2_globals->prm;
155	if (omap2_globals->cm)
156		cm_base = omap2_globals->cm;
157	if (omap2_globals->cm2)
158		cm2_base = omap2_globals->cm2;
159	if (omap2_globals->prcm_mpu)
160		prcm_mpu_base = omap2_globals->prcm_mpu;
161
162	if (cpu_is_omap44xx()) {
163		omap_prm_base_init();
164		omap_cm_base_init();
165	}
166}