1/*
  2 * OMAP4XXX L3 Interconnect  error handling driver header
  3 *
  4 * Copyright (C) 2011 Texas Corporation
  5 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
  6 *	sricharan <r.sricharan@ti.com>
  7 *
  8 * This program is free software; you can redistribute it and/or modify
  9 * it under the terms of the GNU General Public License as published by
 10 * the Free Software Foundation; either version 2 of the License, or
 11 * (at your option) any later version.
 12 *
 13 * This program is distributed in the hope that it will be useful,
 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16 * GNU General Public License for more details.
 17 *
 18 * You should have received a copy of the GNU General Public License
 19 * along with this program; if not, write to the Free Software
 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
 21 * USA
 22 */
 23#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
 24#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
 25
 26#define L3_MODULES			3
 27#define CLEAR_STDERR_LOG		(1 << 31)
 28#define CUSTOM_ERROR			0x2
 29#define STANDARD_ERROR			0x0
 30#define INBAND_ERROR			0x0
 31#define L3_APPLICATION_ERROR		0x0
 32#define L3_DEBUG_ERROR			0x1
 33
 34/* L3 TARG register offsets */
 35#define L3_TARG_STDERRLOG_MAIN		0x48
 36#define L3_TARG_STDERRLOG_SLVOFSLSB	0x5c
 37#define L3_TARG_STDERRLOG_MSTADDR	0x68
 38#define L3_FLAGMUX_REGERR0		0xc
 39
 40#define NUM_OF_L3_MASTERS	(sizeof(l3_masters)/sizeof(l3_masters[0]))
 41
 42static u32 l3_flagmux[L3_MODULES] = {
 43	0x500,
 44	0x1000,
 45	0X0200
 46};
 47
 48/* L3 Target standard Error register offsets */
 49static u32 l3_targ_inst_clk1[] = {
 50	0x100, /* DMM1 */
 51	0x200, /* DMM2 */
 52	0x300, /* ABE */
 53	0x400, /* L4CFG */
 54	0x600  /* CLK2 PWR DISC */
 55};
 56
 57static u32 l3_targ_inst_clk2[] = {
 58	0x500, /* CORTEX M3 */
 59	0x300, /* DSS */
 60	0x100, /* GPMC */
 61	0x400, /* ISS */
 62	0x700, /* IVAHD */
 63	0xD00, /* missing in TRM  corresponds to AES1*/
 64	0x900, /* L4 PER0*/
 65	0x200, /* OCMRAM */
 66	0x100, /* missing in TRM corresponds to GPMC sERROR*/
 67	0x600, /* SGX */
 68	0x800, /* SL2 */
 69	0x1600, /* C2C */
 70	0x1100,	/* missing in TRM corresponds PWR DISC CLK1*/
 71	0xF00, /* missing in TRM corrsponds to SHA1*/
 72	0xE00, /* missing in TRM corresponds to AES2*/
 73	0xC00, /* L4 PER3 */
 74	0xA00, /* L4 PER1*/
 75	0xB00 /* L4 PER2*/
 76};
 77
 78static u32 l3_targ_inst_clk3[] = {
 79	0x0100	/* EMUSS */
 80};
 81
 82static struct l3_masters_data {
 83	u32 id;
 84	char name[10];
 85} l3_masters[] = {
 86	{ 0x0 , "MPU"},
 87	{ 0x10, "CS_ADP"},
 88	{ 0x14, "xxx"},
 89	{ 0x20, "DSP"},
 90	{ 0x30, "IVAHD"},
 91	{ 0x40, "ISS"},
 92	{ 0x44, "DucatiM3"},
 93	{ 0x48, "FaceDetect"},
 94	{ 0x50, "SDMA_Rd"},
 95	{ 0x54, "SDMA_Wr"},
 96	{ 0x58, "xxx"},
 97	{ 0x5C, "xxx"},
 98	{ 0x60, "SGX"},
 99	{ 0x70, "DSS"},
100	{ 0x80, "C2C"},
101	{ 0x88, "xxx"},
102	{ 0x8C, "xxx"},
103	{ 0x90, "HSI"},
104	{ 0xA0, "MMC1"},
105	{ 0xA4, "MMC2"},
106	{ 0xA8, "MMC6"},
107	{ 0xB0, "UNIPRO1"},
108	{ 0xC0, "USBHOSTHS"},
109	{ 0xC4, "USBOTGHS"},
110	{ 0xC8, "USBHOSTFS"}
111};
112
113static char *l3_targ_inst_name[L3_MODULES][18] = {
114	{
115		"DMM1",
116		"DMM2",
117		"ABE",
118		"L4CFG",
119		"CLK2 PWR DISC",
120	},
121	{
122		"CORTEX M3" ,
123		"DSS ",
124		"GPMC ",
125		"ISS ",
126		"IVAHD ",
127		"AES1",
128		"L4 PER0",
129		"OCMRAM ",
130		"GPMC sERROR",
131		"SGX ",
132		"SL2 ",
133		"C2C ",
134		"PWR DISC CLK1",
135		"SHA1",
136		"AES2",
137		"L4 PER3",
138		"L4 PER1",
139		"L4 PER2",
140	},
141	{
142		"EMUSS",
143	},
144};
145
146static u32 *l3_targ[L3_MODULES] = {
147	l3_targ_inst_clk1,
148	l3_targ_inst_clk2,
149	l3_targ_inst_clk3,
150};
151
152struct omap4_l3 {
153	struct device *dev;
154	struct clk *ick;
155
156	/* memory base */
157	void __iomem *l3_base[L3_MODULES];
158
159	int debug_irq;
160	int app_irq;
161};
162#endif