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1/*
2 * DRA7xx CM2 instance offset macros
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Generated by code originally written by:
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
22#ifndef __ARCH_ARM_MACH_OMAP2_CM2_7XX_H
23#define __ARCH_ARM_MACH_OMAP2_CM2_7XX_H
24
25/* CM2 base address */
26#define DRA7XX_CM_CORE_BASE 0x4a008000
27
28#define DRA7XX_CM_CORE_REGADDR(inst, reg) \
29 OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_BASE + (inst) + (reg))
30
31/* CM_CORE instances */
32#define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000
33#define DRA7XX_CM_CORE_CKGEN_INST 0x0104
34#define DRA7XX_CM_CORE_COREAON_INST 0x0600
35#define DRA7XX_CM_CORE_CORE_INST 0x0700
36#define DRA7XX_CM_CORE_IVA_INST 0x0f00
37#define DRA7XX_CM_CORE_CAM_INST 0x1000
38#define DRA7XX_CM_CORE_DSS_INST 0x1100
39#define DRA7XX_CM_CORE_GPU_INST 0x1200
40#define DRA7XX_CM_CORE_L3INIT_INST 0x1300
41#define DRA7XX_CM_CORE_CUSTEFUSE_INST 0x1600
42#define DRA7XX_CM_CORE_L4PER_INST 0x1700
43#define DRA7XX_CM_CORE_RESTORE_INST 0x1e18
44
45/* CM_CORE clockdomain register offsets (from instance start) */
46#define DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000
47#define DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS 0x0000
48#define DRA7XX_CM_CORE_CORE_IPU2_CDOFFS 0x0200
49#define DRA7XX_CM_CORE_CORE_DMA_CDOFFS 0x0300
50#define DRA7XX_CM_CORE_CORE_EMIF_CDOFFS 0x0400
51#define DRA7XX_CM_CORE_CORE_ATL_CDOFFS 0x0520
52#define DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS 0x0600
53#define DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS 0x0700
54#define DRA7XX_CM_CORE_IVA_IVA_CDOFFS 0x0000
55#define DRA7XX_CM_CORE_CAM_CAM_CDOFFS 0x0000
56#define DRA7XX_CM_CORE_DSS_DSS_CDOFFS 0x0000
57#define DRA7XX_CM_CORE_GPU_GPU_CDOFFS 0x0000
58#define DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS 0x0000
59#define DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS 0x00a0
60#define DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS 0x00c0
61#define DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS 0x0000
62#define DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS 0x0000
63#define DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS 0x0180
64#define DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS 0x01fc
65#define DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS 0x0210
66
67/* CM_CORE */
68
69/* CM_CORE.OCP_SOCKET_CM_CORE register offsets */
70#define DRA7XX_REVISION_CM_CORE_OFFSET 0x0000
71#define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET 0x0040
72#define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_OCP_SOCKET_INST, 0x0040)
73#define DRA7XX_CM_CORE_DEBUG_CFG_OFFSET 0x00f0
74
75/* CM_CORE.CKGEN_CM_CORE register offsets */
76#define DRA7XX_CM_CLKSEL_USB_60MHZ_OFFSET 0x0000
77#define DRA7XX_CM_CLKSEL_USB_60MHZ DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0000)
78#define DRA7XX_CM_CLKMODE_DPLL_PER_OFFSET 0x003c
79#define DRA7XX_CM_CLKMODE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x003c)
80#define DRA7XX_CM_IDLEST_DPLL_PER_OFFSET 0x0040
81#define DRA7XX_CM_IDLEST_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0040)
82#define DRA7XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0044
83#define DRA7XX_CM_AUTOIDLE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0044)
84#define DRA7XX_CM_CLKSEL_DPLL_PER_OFFSET 0x0048
85#define DRA7XX_CM_CLKSEL_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0048)
86#define DRA7XX_CM_DIV_M2_DPLL_PER_OFFSET 0x004c
87#define DRA7XX_CM_DIV_M2_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x004c)
88#define DRA7XX_CM_DIV_M3_DPLL_PER_OFFSET 0x0050
89#define DRA7XX_CM_DIV_M3_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0050)
90#define DRA7XX_CM_DIV_H11_DPLL_PER_OFFSET 0x0054
91#define DRA7XX_CM_DIV_H11_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0054)
92#define DRA7XX_CM_DIV_H12_DPLL_PER_OFFSET 0x0058
93#define DRA7XX_CM_DIV_H12_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0058)
94#define DRA7XX_CM_DIV_H13_DPLL_PER_OFFSET 0x005c
95#define DRA7XX_CM_DIV_H13_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x005c)
96#define DRA7XX_CM_DIV_H14_DPLL_PER_OFFSET 0x0060
97#define DRA7XX_CM_DIV_H14_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0060)
98#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0064
99#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x0068
100#define DRA7XX_CM_CLKMODE_DPLL_USB_OFFSET 0x007c
101#define DRA7XX_CM_CLKMODE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x007c)
102#define DRA7XX_CM_IDLEST_DPLL_USB_OFFSET 0x0080
103#define DRA7XX_CM_IDLEST_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0080)
104#define DRA7XX_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0084
105#define DRA7XX_CM_AUTOIDLE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0084)
106#define DRA7XX_CM_CLKSEL_DPLL_USB_OFFSET 0x0088
107#define DRA7XX_CM_CLKSEL_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0088)
108#define DRA7XX_CM_DIV_M2_DPLL_USB_OFFSET 0x008c
109#define DRA7XX_CM_DIV_M2_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x008c)
110#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a4
111#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00a8
112#define DRA7XX_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b0
113#define DRA7XX_CM_CLKDCOLDO_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00b0)
114#define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF_OFFSET 0x00fc
115#define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00fc)
116#define DRA7XX_CM_IDLEST_DPLL_PCIE_REF_OFFSET 0x0100
117#define DRA7XX_CM_IDLEST_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0100)
118#define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF_OFFSET 0x0104
119#define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0104)
120#define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF_OFFSET 0x0108
121#define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0108)
122#define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF_OFFSET 0x010c
123#define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x010c)
124#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PCIE_REF_OFFSET 0x0110
125#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PCIE_REF_OFFSET 0x0114
126#define DRA7XX_CM_CLKMODE_APLL_PCIE_OFFSET 0x0118
127#define DRA7XX_CM_CLKMODE_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0118)
128#define DRA7XX_CM_IDLEST_APLL_PCIE_OFFSET 0x011c
129#define DRA7XX_CM_IDLEST_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x011c)
130#define DRA7XX_CM_DIV_M2_APLL_PCIE_OFFSET 0x0120
131#define DRA7XX_CM_DIV_M2_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0120)
132#define DRA7XX_CM_CLKVCOLDO_APLL_PCIE_OFFSET 0x0124
133#define DRA7XX_CM_CLKVCOLDO_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0124)
134
135/* CM_CORE.COREAON_CM_CORE register offsets */
136#define DRA7XX_CM_COREAON_CLKSTCTRL_OFFSET 0x0000
137#define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET 0x0028
138#define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0028)
139#define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET 0x0038
140#define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0038)
141#define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL_OFFSET 0x0040
142#define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0040)
143#define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0050
144#define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0050)
145#define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL_OFFSET 0x0058
146#define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0058)
147#define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL_OFFSET 0x0068
148#define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0068)
149#define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL_OFFSET 0x0078
150#define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0078)
151#define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL_OFFSET 0x0088
152#define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0088)
153#define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL_OFFSET 0x0098
154#define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0098)
155#define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL_OFFSET 0x00a0
156#define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00a0)
157#define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL_OFFSET 0x00b0
158#define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00b0)
159#define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL_OFFSET 0x00c0
160#define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00c0)
161#define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL_OFFSET 0x00d0
162#define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00d0)
163
164/* CM_CORE.CORE_CM_CORE register offsets */
165#define DRA7XX_CM_L3MAIN1_CLKSTCTRL_OFFSET 0x0000
166#define DRA7XX_CM_L3MAIN1_DYNAMICDEP_OFFSET 0x0008
167#define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET 0x0020
168#define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0020)
169#define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET 0x0028
170#define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0028)
171#define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL_OFFSET 0x0030
172#define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0030)
173#define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_OFFSET 0x0050
174#define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0050)
175#define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_OFFSET 0x0058
176#define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0058)
177#define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_OFFSET 0x0060
178#define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0060)
179#define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL_OFFSET 0x0068
180#define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0068)
181#define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET 0x0070
182#define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0070)
183#define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET 0x0078
184#define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0078)
185#define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET 0x0080
186#define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0080)
187#define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET 0x0088
188#define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0088)
189#define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET 0x0090
190#define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0090)
191#define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL_OFFSET 0x0098
192#define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0098)
193#define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL_OFFSET 0x00a0
194#define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a0)
195#define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL_OFFSET 0x00a8
196#define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a8)
197#define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL_OFFSET 0x00b0
198#define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b0)
199#define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL_OFFSET 0x00b8
200#define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b8)
201#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL_OFFSET 0x00c0
202#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c0)
203#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL_OFFSET 0x00c8
204#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c8)
205#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL_OFFSET 0x00d0
206#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d0)
207#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL_OFFSET 0x00d8
208#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d8)
209#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL_OFFSET 0x00f0
210#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f0)
211#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL_OFFSET 0x00f8
212#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f8)
213#define DRA7XX_CM_IPU2_CLKSTCTRL_OFFSET 0x0200
214#define DRA7XX_CM_IPU2_STATICDEP_OFFSET 0x0204
215#define DRA7XX_CM_IPU2_DYNAMICDEP_OFFSET 0x0208
216#define DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET 0x0220
217#define DRA7XX_CM_IPU2_IPU2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0220)
218#define DRA7XX_CM_DMA_CLKSTCTRL_OFFSET 0x0300
219#define DRA7XX_CM_DMA_STATICDEP_OFFSET 0x0304
220#define DRA7XX_CM_DMA_DYNAMICDEP_OFFSET 0x0308
221#define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET 0x0320
222#define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0320)
223#define DRA7XX_CM_EMIF_CLKSTCTRL_OFFSET 0x0400
224#define DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET 0x0420
225#define DRA7XX_CM_EMIF_DMM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0420)
226#define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET 0x0428
227#define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0428)
228#define DRA7XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET 0x0430
229#define DRA7XX_CM_EMIF_EMIF1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0430)
230#define DRA7XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET 0x0438
231#define DRA7XX_CM_EMIF_EMIF2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0438)
232#define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET 0x0440
233#define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0440)
234#define DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET 0x0500
235#define DRA7XX_CM_ATL_ATL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0500)
236#define DRA7XX_CM_ATL_CLKSTCTRL_OFFSET 0x0520
237#define DRA7XX_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600
238#define DRA7XX_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608
239#define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620
240#define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0620)
241#define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET 0x0628
242#define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0628)
243#define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET 0x0630
244#define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0630)
245#define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638
246#define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0638)
247#define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET 0x0640
248#define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0640)
249#define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET 0x0648
250#define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0648)
251#define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET 0x0650
252#define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0650)
253#define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET 0x0658
254#define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0658)
255#define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET 0x0660
256#define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0660)
257#define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET 0x0668
258#define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0668)
259#define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET 0x0670
260#define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0670)
261#define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET 0x0678
262#define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0678)
263#define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET 0x0680
264#define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0680)
265#define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET 0x0688
266#define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0688)
267#define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET 0x0690
268#define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0690)
269#define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET 0x0698
270#define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0698)
271#define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET 0x06a0
272#define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a0)
273#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL_OFFSET 0x06a8
274#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a8)
275#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL_OFFSET 0x06b0
276#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b0)
277#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL_OFFSET 0x06b8
278#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b8)
279#define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL_OFFSET 0x06c0
280#define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06c0)
281#define DRA7XX_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700
282#define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET 0x0720
283#define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0720)
284#define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728
285#define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0728)
286#define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET 0x0740
287#define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0740)
288#define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET 0x0748
289#define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0748)
290#define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET 0x0750
291#define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0750)
292
293/* CM_CORE.IVA_CM_CORE register offsets */
294#define DRA7XX_CM_IVA_CLKSTCTRL_OFFSET 0x0000
295#define DRA7XX_CM_IVA_STATICDEP_OFFSET 0x0004
296#define DRA7XX_CM_IVA_DYNAMICDEP_OFFSET 0x0008
297#define DRA7XX_CM_IVA_IVA_CLKCTRL_OFFSET 0x0020
298#define DRA7XX_CM_IVA_IVA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0020)
299#define DRA7XX_CM_IVA_SL2_CLKCTRL_OFFSET 0x0028
300#define DRA7XX_CM_IVA_SL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0028)
301
302/* CM_CORE.CAM_CM_CORE register offsets */
303#define DRA7XX_CM_CAM_CLKSTCTRL_OFFSET 0x0000
304#define DRA7XX_CM_CAM_STATICDEP_OFFSET 0x0004
305#define DRA7XX_CM_CAM_VIP1_CLKCTRL_OFFSET 0x0020
306#define DRA7XX_CM_CAM_VIP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0020)
307#define DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET 0x0028
308#define DRA7XX_CM_CAM_VIP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0028)
309#define DRA7XX_CM_CAM_VIP3_CLKCTRL_OFFSET 0x0030
310#define DRA7XX_CM_CAM_VIP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0030)
311#define DRA7XX_CM_CAM_LVDSRX_CLKCTRL_OFFSET 0x0038
312#define DRA7XX_CM_CAM_LVDSRX_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0038)
313#define DRA7XX_CM_CAM_CSI1_CLKCTRL_OFFSET 0x0040
314#define DRA7XX_CM_CAM_CSI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0040)
315#define DRA7XX_CM_CAM_CSI2_CLKCTRL_OFFSET 0x0048
316#define DRA7XX_CM_CAM_CSI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0048)
317
318/* CM_CORE.DSS_CM_CORE register offsets */
319#define DRA7XX_CM_DSS_CLKSTCTRL_OFFSET 0x0000
320#define DRA7XX_CM_DSS_STATICDEP_OFFSET 0x0004
321#define DRA7XX_CM_DSS_DYNAMICDEP_OFFSET 0x0008
322#define DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020
323#define DRA7XX_CM_DSS_DSS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0020)
324#define DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET 0x0030
325#define DRA7XX_CM_DSS_BB2D_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0030)
326#define DRA7XX_CM_DSS_SDVENC_CLKCTRL_OFFSET 0x003c
327#define DRA7XX_CM_DSS_SDVENC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x003c)
328
329/* CM_CORE.GPU_CM_CORE register offsets */
330#define DRA7XX_CM_GPU_CLKSTCTRL_OFFSET 0x0000
331#define DRA7XX_CM_GPU_STATICDEP_OFFSET 0x0004
332#define DRA7XX_CM_GPU_DYNAMICDEP_OFFSET 0x0008
333#define DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET 0x0020
334#define DRA7XX_CM_GPU_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_GPU_INST, 0x0020)
335
336/* CM_CORE.L3INIT_CM_CORE register offsets */
337#define DRA7XX_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000
338#define DRA7XX_CM_L3INIT_STATICDEP_OFFSET 0x0004
339#define DRA7XX_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008
340#define DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028
341#define DRA7XX_CM_L3INIT_MMC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0028)
342#define DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030
343#define DRA7XX_CM_L3INIT_MMC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0030)
344#define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET 0x0040
345#define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0040)
346#define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET 0x0048
347#define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0048)
348#define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET 0x0050
349#define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0050)
350#define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL_OFFSET 0x0058
351#define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0058)
352#define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET 0x0078
353#define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0078)
354#define DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088
355#define DRA7XX_CM_L3INIT_SATA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088)
356#define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET 0x00a0
357#define DRA7XX_CM_PCIE_STATICDEP_OFFSET 0x00a4
358#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET 0x00b0
359#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b0)
360#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET 0x00b8
361#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b8)
362#define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET 0x00c0
363#define DRA7XX_CM_GMAC_STATICDEP_OFFSET 0x00c4
364#define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8
365#define DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET 0x00d0
366#define DRA7XX_CM_GMAC_GMAC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00d0)
367#define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET 0x00e0
368#define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e0)
369#define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET 0x00e8
370#define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e8)
371#define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET 0x00f0
372#define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00f0)
373
374/* CM_CORE.CUSTEFUSE_CM_CORE register offsets */
375#define DRA7XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET 0x0000
376#define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET 0x0020
377#define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CUSTEFUSE_INST, 0x0020)
378
379/* CM_CORE.L4PER_CM_CORE register offsets */
380#define DRA7XX_CM_L4PER_CLKSTCTRL_OFFSET 0x0000
381#define DRA7XX_CM_L4PER_DYNAMICDEP_OFFSET 0x0008
382#define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET 0x000c
383#define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x000c)
384#define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET 0x0014
385#define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0014)
386#define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET 0x0018
387#define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0018)
388#define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET 0x0020
389#define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0020)
390#define DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET 0x0028
391#define DRA7XX_CM_L4PER_TIMER10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0028)
392#define DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET 0x0030
393#define DRA7XX_CM_L4PER_TIMER11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0030)
394#define DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET 0x0038
395#define DRA7XX_CM_L4PER_TIMER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0038)
396#define DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET 0x0040
397#define DRA7XX_CM_L4PER_TIMER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0040)
398#define DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET 0x0048
399#define DRA7XX_CM_L4PER_TIMER4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0048)
400#define DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET 0x0050
401#define DRA7XX_CM_L4PER_TIMER9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0050)
402#define DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058
403#define DRA7XX_CM_L4PER_ELM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0058)
404#define DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060
405#define DRA7XX_CM_L4PER_GPIO2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0060)
406#define DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068
407#define DRA7XX_CM_L4PER_GPIO3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0068)
408#define DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070
409#define DRA7XX_CM_L4PER_GPIO4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0070)
410#define DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078
411#define DRA7XX_CM_L4PER_GPIO5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0078)
412#define DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080
413#define DRA7XX_CM_L4PER_GPIO6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0080)
414#define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088
415#define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0088)
416#define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET 0x0090
417#define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0090)
418#define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET 0x0098
419#define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0098)
420#define DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0
421#define DRA7XX_CM_L4PER_I2C1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a0)
422#define DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8
423#define DRA7XX_CM_L4PER_I2C2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a8)
424#define DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0
425#define DRA7XX_CM_L4PER_I2C3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b0)
426#define DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8
427#define DRA7XX_CM_L4PER_I2C4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b8)
428#define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET 0x00c0
429#define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c0)
430#define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET 0x00c4
431#define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c4)
432#define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET 0x00c8
433#define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c8)
434#define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET 0x00d0
435#define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d0)
436#define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET 0x00d8
437#define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d8)
438#define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0
439#define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f0)
440#define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8
441#define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f8)
442#define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100
443#define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0100)
444#define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108
445#define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0108)
446#define DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET 0x0110
447#define DRA7XX_CM_L4PER_GPIO7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0110)
448#define DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET 0x0118
449#define DRA7XX_CM_L4PER_GPIO8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0118)
450#define DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET 0x0120
451#define DRA7XX_CM_L4PER_MMC3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0120)
452#define DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET 0x0128
453#define DRA7XX_CM_L4PER_MMC4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0128)
454#define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET 0x0130
455#define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0130)
456#define DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET 0x0138
457#define DRA7XX_CM_L4PER2_QSPI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0138)
458#define DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140
459#define DRA7XX_CM_L4PER_UART1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0140)
460#define DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148
461#define DRA7XX_CM_L4PER_UART2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0148)
462#define DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150
463#define DRA7XX_CM_L4PER_UART3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0150)
464#define DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158
465#define DRA7XX_CM_L4PER_UART4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0158)
466#define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET 0x0160
467#define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0160)
468#define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET 0x0168
469#define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0168)
470#define DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET 0x0170
471#define DRA7XX_CM_L4PER_UART5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0170)
472#define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET 0x0178
473#define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0178)
474#define DRA7XX_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180
475#define DRA7XX_CM_L4SEC_STATICDEP_OFFSET 0x0184
476#define DRA7XX_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188
477#define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET 0x0190
478#define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0190)
479#define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET 0x0198
480#define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0198)
481#define DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0
482#define DRA7XX_CM_L4SEC_AES1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a0)
483#define DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8
484#define DRA7XX_CM_L4SEC_AES2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a8)
485#define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0
486#define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b0)
487#define DRA7XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET 0x01b8
488#define DRA7XX_CM_L4SEC_FPKA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b8)
489#define DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0
490#define DRA7XX_CM_L4SEC_RNG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c0)
491#define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8
492#define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c8)
493#define DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET 0x01d0
494#define DRA7XX_CM_L4PER2_UART7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d0)
495#define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET 0x01d8
496#define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d8)
497#define DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET 0x01e0
498#define DRA7XX_CM_L4PER2_UART8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e0)
499#define DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET 0x01e8
500#define DRA7XX_CM_L4PER2_UART9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e8)
501#define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET 0x01f0
502#define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f0)
503#define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL_OFFSET 0x01f8
504#define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f8)
505#define DRA7XX_CM_L4PER2_CLKSTCTRL_OFFSET 0x01fc
506#define DRA7XX_CM_L4PER2_DYNAMICDEP_OFFSET 0x0200
507#define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET 0x0204
508#define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0204)
509#define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET 0x0208
510#define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0208)
511#define DRA7XX_CM_L4PER2_STATICDEP_OFFSET 0x020c
512#define DRA7XX_CM_L4PER3_CLKSTCTRL_OFFSET 0x0210
513#define DRA7XX_CM_L4PER3_DYNAMICDEP_OFFSET 0x0214
514
515#endif