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1#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
2#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
3
4/*
5 * OMAP24XX Clock Management register bits
6 *
7 * Copyright (C) 2007 Texas Instruments, Inc.
8 * Copyright (C) 2007 Nokia Corporation
9 *
10 * Written by Paul Walmsley
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17/* Bits shared between registers */
18
19/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
20#define OMAP24XX_EN_CAM_SHIFT 31
21#define OMAP24XX_EN_CAM_MASK (1 << 31)
22#define OMAP24XX_EN_WDT4_SHIFT 29
23#define OMAP24XX_EN_WDT4_MASK (1 << 29)
24#define OMAP2420_EN_WDT3_SHIFT 28
25#define OMAP2420_EN_WDT3_MASK (1 << 28)
26#define OMAP24XX_EN_MSPRO_SHIFT 27
27#define OMAP24XX_EN_MSPRO_MASK (1 << 27)
28#define OMAP24XX_EN_FAC_SHIFT 25
29#define OMAP24XX_EN_FAC_MASK (1 << 25)
30#define OMAP2420_EN_EAC_SHIFT 24
31#define OMAP2420_EN_EAC_MASK (1 << 24)
32#define OMAP24XX_EN_HDQ_SHIFT 23
33#define OMAP24XX_EN_HDQ_MASK (1 << 23)
34#define OMAP2420_EN_I2C2_SHIFT 20
35#define OMAP2420_EN_I2C2_MASK (1 << 20)
36#define OMAP2420_EN_I2C1_SHIFT 19
37#define OMAP2420_EN_I2C1_MASK (1 << 19)
38
39/* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */
40#define OMAP2430_EN_MCBSP5_SHIFT 5
41#define OMAP2430_EN_MCBSP5_MASK (1 << 5)
42#define OMAP2430_EN_MCBSP4_SHIFT 4
43#define OMAP2430_EN_MCBSP4_MASK (1 << 4)
44#define OMAP2430_EN_MCBSP3_SHIFT 3
45#define OMAP2430_EN_MCBSP3_MASK (1 << 3)
46#define OMAP24XX_EN_SSI_SHIFT 1
47#define OMAP24XX_EN_SSI_MASK (1 << 1)
48
49/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
50#define OMAP24XX_EN_MPU_WDT_SHIFT 3
51#define OMAP24XX_EN_MPU_WDT_MASK (1 << 3)
52
53/* Bits specific to each register */
54
55/* CM_IDLEST_MPU */
56/* 2430 only */
57#define OMAP2430_ST_MPU_MASK (1 << 0)
58
59/* CM_CLKSEL_MPU */
60#define OMAP24XX_CLKSEL_MPU_SHIFT 0
61#define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0)
62
63/* CM_CLKSTCTRL_MPU */
64#define OMAP24XX_AUTOSTATE_MPU_SHIFT 0
65#define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0)
66
67/* CM_FCLKEN1_CORE specific bits*/
68#define OMAP24XX_EN_TV_SHIFT 2
69#define OMAP24XX_EN_TV_MASK (1 << 2)
70#define OMAP24XX_EN_DSS2_SHIFT 1
71#define OMAP24XX_EN_DSS2_MASK (1 << 1)
72#define OMAP24XX_EN_DSS1_SHIFT 0
73#define OMAP24XX_EN_DSS1_MASK (1 << 0)
74
75/* CM_FCLKEN2_CORE specific bits */
76#define OMAP2430_EN_I2CHS2_SHIFT 20
77#define OMAP2430_EN_I2CHS2_MASK (1 << 20)
78#define OMAP2430_EN_I2CHS1_SHIFT 19
79#define OMAP2430_EN_I2CHS1_MASK (1 << 19)
80#define OMAP2430_EN_MMCHSDB2_SHIFT 17
81#define OMAP2430_EN_MMCHSDB2_MASK (1 << 17)
82#define OMAP2430_EN_MMCHSDB1_SHIFT 16
83#define OMAP2430_EN_MMCHSDB1_MASK (1 << 16)
84
85/* CM_ICLKEN1_CORE specific bits */
86#define OMAP24XX_EN_MAILBOXES_SHIFT 30
87#define OMAP24XX_EN_MAILBOXES_MASK (1 << 30)
88#define OMAP24XX_EN_DSS_SHIFT 0
89#define OMAP24XX_EN_DSS_MASK (1 << 0)
90
91/* CM_ICLKEN2_CORE specific bits */
92
93/* CM_ICLKEN3_CORE */
94/* 2430 only */
95#define OMAP2430_EN_SDRC_SHIFT 2
96#define OMAP2430_EN_SDRC_MASK (1 << 2)
97
98/* CM_ICLKEN4_CORE */
99#define OMAP24XX_EN_PKA_SHIFT 4
100#define OMAP24XX_EN_PKA_MASK (1 << 4)
101#define OMAP24XX_EN_AES_SHIFT 3
102#define OMAP24XX_EN_AES_MASK (1 << 3)
103#define OMAP24XX_EN_RNG_SHIFT 2
104#define OMAP24XX_EN_RNG_MASK (1 << 2)
105#define OMAP24XX_EN_SHA_SHIFT 1
106#define OMAP24XX_EN_SHA_MASK (1 << 1)
107#define OMAP24XX_EN_DES_SHIFT 0
108#define OMAP24XX_EN_DES_MASK (1 << 0)
109
110/* CM_IDLEST1_CORE specific bits */
111#define OMAP24XX_ST_MAILBOXES_SHIFT 30
112#define OMAP24XX_ST_MAILBOXES_MASK (1 << 30)
113#define OMAP24XX_ST_WDT4_SHIFT 29
114#define OMAP24XX_ST_WDT4_MASK (1 << 29)
115#define OMAP2420_ST_WDT3_SHIFT 28
116#define OMAP2420_ST_WDT3_MASK (1 << 28)
117#define OMAP24XX_ST_MSPRO_SHIFT 27
118#define OMAP24XX_ST_MSPRO_MASK (1 << 27)
119#define OMAP24XX_ST_FAC_SHIFT 25
120#define OMAP24XX_ST_FAC_MASK (1 << 25)
121#define OMAP2420_ST_EAC_SHIFT 24
122#define OMAP2420_ST_EAC_MASK (1 << 24)
123#define OMAP24XX_ST_HDQ_SHIFT 23
124#define OMAP24XX_ST_HDQ_MASK (1 << 23)
125#define OMAP2420_ST_I2C2_SHIFT 20
126#define OMAP2420_ST_I2C2_MASK (1 << 20)
127#define OMAP2430_ST_I2CHS1_SHIFT 19
128#define OMAP2430_ST_I2CHS1_MASK (1 << 19)
129#define OMAP2420_ST_I2C1_SHIFT 19
130#define OMAP2420_ST_I2C1_MASK (1 << 19)
131#define OMAP2430_ST_I2CHS2_SHIFT 20
132#define OMAP2430_ST_I2CHS2_MASK (1 << 20)
133#define OMAP24XX_ST_MCBSP2_SHIFT 16
134#define OMAP24XX_ST_MCBSP2_MASK (1 << 16)
135#define OMAP24XX_ST_MCBSP1_SHIFT 15
136#define OMAP24XX_ST_MCBSP1_MASK (1 << 15)
137#define OMAP24XX_ST_DSS_SHIFT 0
138#define OMAP24XX_ST_DSS_MASK (1 << 0)
139
140/* CM_IDLEST2_CORE */
141#define OMAP2430_ST_MCBSP5_SHIFT 5
142#define OMAP2430_ST_MCBSP5_MASK (1 << 5)
143#define OMAP2430_ST_MCBSP4_SHIFT 4
144#define OMAP2430_ST_MCBSP4_MASK (1 << 4)
145#define OMAP2430_ST_MCBSP3_SHIFT 3
146#define OMAP2430_ST_MCBSP3_MASK (1 << 3)
147#define OMAP24XX_ST_SSI_SHIFT 1
148#define OMAP24XX_ST_SSI_MASK (1 << 1)
149
150/* CM_IDLEST3_CORE */
151/* 2430 only */
152#define OMAP2430_ST_SDRC_MASK (1 << 2)
153
154/* CM_IDLEST4_CORE */
155#define OMAP24XX_ST_PKA_SHIFT 4
156#define OMAP24XX_ST_PKA_MASK (1 << 4)
157#define OMAP24XX_ST_AES_SHIFT 3
158#define OMAP24XX_ST_AES_MASK (1 << 3)
159#define OMAP24XX_ST_RNG_SHIFT 2
160#define OMAP24XX_ST_RNG_MASK (1 << 2)
161#define OMAP24XX_ST_SHA_SHIFT 1
162#define OMAP24XX_ST_SHA_MASK (1 << 1)
163#define OMAP24XX_ST_DES_SHIFT 0
164#define OMAP24XX_ST_DES_MASK (1 << 0)
165
166/* CM_AUTOIDLE1_CORE */
167#define OMAP24XX_AUTO_CAM_MASK (1 << 31)
168#define OMAP24XX_AUTO_MAILBOXES_MASK (1 << 30)
169#define OMAP24XX_AUTO_WDT4_MASK (1 << 29)
170#define OMAP2420_AUTO_WDT3_MASK (1 << 28)
171#define OMAP24XX_AUTO_MSPRO_MASK (1 << 27)
172#define OMAP2420_AUTO_MMC_MASK (1 << 26)
173#define OMAP24XX_AUTO_FAC_MASK (1 << 25)
174#define OMAP2420_AUTO_EAC_MASK (1 << 24)
175#define OMAP24XX_AUTO_HDQ_MASK (1 << 23)
176#define OMAP24XX_AUTO_UART2_MASK (1 << 22)
177#define OMAP24XX_AUTO_UART1_MASK (1 << 21)
178#define OMAP24XX_AUTO_I2C2_MASK (1 << 20)
179#define OMAP24XX_AUTO_I2C1_MASK (1 << 19)
180#define OMAP24XX_AUTO_MCSPI2_MASK (1 << 18)
181#define OMAP24XX_AUTO_MCSPI1_MASK (1 << 17)
182#define OMAP24XX_AUTO_MCBSP2_MASK (1 << 16)
183#define OMAP24XX_AUTO_MCBSP1_MASK (1 << 15)
184#define OMAP24XX_AUTO_GPT12_MASK (1 << 14)
185#define OMAP24XX_AUTO_GPT11_MASK (1 << 13)
186#define OMAP24XX_AUTO_GPT10_MASK (1 << 12)
187#define OMAP24XX_AUTO_GPT9_MASK (1 << 11)
188#define OMAP24XX_AUTO_GPT8_MASK (1 << 10)
189#define OMAP24XX_AUTO_GPT7_MASK (1 << 9)
190#define OMAP24XX_AUTO_GPT6_MASK (1 << 8)
191#define OMAP24XX_AUTO_GPT5_MASK (1 << 7)
192#define OMAP24XX_AUTO_GPT4_MASK (1 << 6)
193#define OMAP24XX_AUTO_GPT3_MASK (1 << 5)
194#define OMAP24XX_AUTO_GPT2_MASK (1 << 4)
195#define OMAP2420_AUTO_VLYNQ_MASK (1 << 3)
196#define OMAP24XX_AUTO_DSS_MASK (1 << 0)
197
198/* CM_AUTOIDLE2_CORE */
199#define OMAP2430_AUTO_MDM_INTC_MASK (1 << 11)
200#define OMAP2430_AUTO_GPIO5_MASK (1 << 10)
201#define OMAP2430_AUTO_MCSPI3_MASK (1 << 9)
202#define OMAP2430_AUTO_MMCHS2_MASK (1 << 8)
203#define OMAP2430_AUTO_MMCHS1_MASK (1 << 7)
204#define OMAP2430_AUTO_USBHS_MASK (1 << 6)
205#define OMAP2430_AUTO_MCBSP5_MASK (1 << 5)
206#define OMAP2430_AUTO_MCBSP4_MASK (1 << 4)
207#define OMAP2430_AUTO_MCBSP3_MASK (1 << 3)
208#define OMAP24XX_AUTO_UART3_MASK (1 << 2)
209#define OMAP24XX_AUTO_SSI_MASK (1 << 1)
210#define OMAP24XX_AUTO_USB_MASK (1 << 0)
211
212/* CM_AUTOIDLE3_CORE */
213#define OMAP24XX_AUTO_SDRC_SHIFT 2
214#define OMAP24XX_AUTO_SDRC_MASK (1 << 2)
215#define OMAP24XX_AUTO_GPMC_SHIFT 1
216#define OMAP24XX_AUTO_GPMC_MASK (1 << 1)
217#define OMAP24XX_AUTO_SDMA_SHIFT 0
218#define OMAP24XX_AUTO_SDMA_MASK (1 << 0)
219
220/* CM_AUTOIDLE4_CORE */
221#define OMAP24XX_AUTO_PKA_MASK (1 << 4)
222#define OMAP24XX_AUTO_AES_MASK (1 << 3)
223#define OMAP24XX_AUTO_RNG_MASK (1 << 2)
224#define OMAP24XX_AUTO_SHA_MASK (1 << 1)
225#define OMAP24XX_AUTO_DES_MASK (1 << 0)
226
227/* CM_CLKSEL1_CORE */
228#define OMAP24XX_CLKSEL_USB_SHIFT 25
229#define OMAP24XX_CLKSEL_USB_MASK (0x7 << 25)
230#define OMAP24XX_CLKSEL_SSI_SHIFT 20
231#define OMAP24XX_CLKSEL_SSI_MASK (0x1f << 20)
232#define OMAP2420_CLKSEL_VLYNQ_SHIFT 15
233#define OMAP2420_CLKSEL_VLYNQ_MASK (0x1f << 15)
234#define OMAP24XX_CLKSEL_DSS2_SHIFT 13
235#define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13)
236#define OMAP24XX_CLKSEL_DSS1_SHIFT 8
237#define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8)
238#define OMAP24XX_CLKSEL_L4_SHIFT 5
239#define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5)
240#define OMAP24XX_CLKSEL_L3_SHIFT 0
241#define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0)
242
243/* CM_CLKSEL2_CORE */
244#define OMAP24XX_CLKSEL_GPT12_SHIFT 22
245#define OMAP24XX_CLKSEL_GPT12_MASK (0x3 << 22)
246#define OMAP24XX_CLKSEL_GPT11_SHIFT 20
247#define OMAP24XX_CLKSEL_GPT11_MASK (0x3 << 20)
248#define OMAP24XX_CLKSEL_GPT10_SHIFT 18
249#define OMAP24XX_CLKSEL_GPT10_MASK (0x3 << 18)
250#define OMAP24XX_CLKSEL_GPT9_SHIFT 16
251#define OMAP24XX_CLKSEL_GPT9_MASK (0x3 << 16)
252#define OMAP24XX_CLKSEL_GPT8_SHIFT 14
253#define OMAP24XX_CLKSEL_GPT8_MASK (0x3 << 14)
254#define OMAP24XX_CLKSEL_GPT7_SHIFT 12
255#define OMAP24XX_CLKSEL_GPT7_MASK (0x3 << 12)
256#define OMAP24XX_CLKSEL_GPT6_SHIFT 10
257#define OMAP24XX_CLKSEL_GPT6_MASK (0x3 << 10)
258#define OMAP24XX_CLKSEL_GPT5_SHIFT 8
259#define OMAP24XX_CLKSEL_GPT5_MASK (0x3 << 8)
260#define OMAP24XX_CLKSEL_GPT4_SHIFT 6
261#define OMAP24XX_CLKSEL_GPT4_MASK (0x3 << 6)
262#define OMAP24XX_CLKSEL_GPT3_SHIFT 4
263#define OMAP24XX_CLKSEL_GPT3_MASK (0x3 << 4)
264#define OMAP24XX_CLKSEL_GPT2_SHIFT 2
265#define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2)
266
267/* CM_CLKSTCTRL_CORE */
268#define OMAP24XX_AUTOSTATE_DSS_SHIFT 2
269#define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2)
270#define OMAP24XX_AUTOSTATE_L4_SHIFT 1
271#define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1)
272#define OMAP24XX_AUTOSTATE_L3_SHIFT 0
273#define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0)
274
275/* CM_FCLKEN_GFX */
276#define OMAP24XX_EN_3D_SHIFT 2
277#define OMAP24XX_EN_3D_MASK (1 << 2)
278#define OMAP24XX_EN_2D_SHIFT 1
279#define OMAP24XX_EN_2D_MASK (1 << 1)
280
281/* CM_ICLKEN_GFX specific bits */
282
283/* CM_IDLEST_GFX specific bits */
284
285/* CM_CLKSEL_GFX specific bits */
286
287/* CM_CLKSTCTRL_GFX */
288#define OMAP24XX_AUTOSTATE_GFX_SHIFT 0
289#define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0)
290
291/* CM_FCLKEN_WKUP specific bits */
292
293/* CM_ICLKEN_WKUP specific bits */
294#define OMAP2430_EN_ICR_SHIFT 6
295#define OMAP2430_EN_ICR_MASK (1 << 6)
296#define OMAP24XX_EN_OMAPCTRL_SHIFT 5
297#define OMAP24XX_EN_OMAPCTRL_MASK (1 << 5)
298#define OMAP24XX_EN_WDT1_SHIFT 4
299#define OMAP24XX_EN_WDT1_MASK (1 << 4)
300#define OMAP24XX_EN_32KSYNC_SHIFT 1
301#define OMAP24XX_EN_32KSYNC_MASK (1 << 1)
302
303/* CM_IDLEST_WKUP specific bits */
304#define OMAP2430_ST_ICR_SHIFT 6
305#define OMAP2430_ST_ICR_MASK (1 << 6)
306#define OMAP24XX_ST_OMAPCTRL_SHIFT 5
307#define OMAP24XX_ST_OMAPCTRL_MASK (1 << 5)
308#define OMAP24XX_ST_WDT1_SHIFT 4
309#define OMAP24XX_ST_WDT1_MASK (1 << 4)
310#define OMAP24XX_ST_MPU_WDT_SHIFT 3
311#define OMAP24XX_ST_MPU_WDT_MASK (1 << 3)
312#define OMAP24XX_ST_32KSYNC_SHIFT 1
313#define OMAP24XX_ST_32KSYNC_MASK (1 << 1)
314
315/* CM_AUTOIDLE_WKUP */
316#define OMAP24XX_AUTO_OMAPCTRL_MASK (1 << 5)
317#define OMAP24XX_AUTO_WDT1_MASK (1 << 4)
318#define OMAP24XX_AUTO_MPU_WDT_MASK (1 << 3)
319#define OMAP24XX_AUTO_GPIOS_MASK (1 << 2)
320#define OMAP24XX_AUTO_32KSYNC_MASK (1 << 1)
321#define OMAP24XX_AUTO_GPT1_MASK (1 << 0)
322
323/* CM_CLKSEL_WKUP */
324#define OMAP24XX_CLKSEL_GPT1_SHIFT 0
325#define OMAP24XX_CLKSEL_GPT1_MASK (0x3 << 0)
326
327/* CM_CLKEN_PLL */
328#define OMAP24XX_EN_54M_PLL_SHIFT 6
329#define OMAP24XX_EN_54M_PLL_MASK (0x3 << 6)
330#define OMAP24XX_EN_96M_PLL_SHIFT 2
331#define OMAP24XX_EN_96M_PLL_MASK (0x3 << 2)
332#define OMAP24XX_EN_DPLL_SHIFT 0
333#define OMAP24XX_EN_DPLL_MASK (0x3 << 0)
334
335/* CM_IDLEST_CKGEN */
336#define OMAP24XX_ST_54M_APLL_MASK (1 << 9)
337#define OMAP24XX_ST_96M_APLL_MASK (1 << 8)
338#define OMAP24XX_ST_54M_CLK_MASK (1 << 6)
339#define OMAP24XX_ST_12M_CLK_MASK (1 << 5)
340#define OMAP24XX_ST_48M_CLK_MASK (1 << 4)
341#define OMAP24XX_ST_96M_CLK_MASK (1 << 2)
342#define OMAP24XX_ST_CORE_CLK_SHIFT 0
343#define OMAP24XX_ST_CORE_CLK_MASK (0x3 << 0)
344
345/* CM_AUTOIDLE_PLL */
346#define OMAP24XX_AUTO_54M_SHIFT 6
347#define OMAP24XX_AUTO_54M_MASK (0x3 << 6)
348#define OMAP24XX_AUTO_96M_SHIFT 2
349#define OMAP24XX_AUTO_96M_MASK (0x3 << 2)
350#define OMAP24XX_AUTO_DPLL_SHIFT 0
351#define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0)
352
353/* CM_CLKSEL1_PLL */
354#define OMAP2430_MAXDPLLFASTLOCK_SHIFT 28
355#define OMAP2430_MAXDPLLFASTLOCK_MASK (0x7 << 28)
356#define OMAP24XX_APLLS_CLKIN_SHIFT 23
357#define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23)
358#define OMAP24XX_DPLL_MULT_SHIFT 12
359#define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12)
360#define OMAP24XX_DPLL_DIV_SHIFT 8
361#define OMAP24XX_DPLL_DIV_MASK (0xf << 8)
362#define OMAP24XX_54M_SOURCE_SHIFT 5
363#define OMAP24XX_54M_SOURCE_MASK (1 << 5)
364#define OMAP2430_96M_SOURCE_SHIFT 4
365#define OMAP2430_96M_SOURCE_MASK (1 << 4)
366#define OMAP24XX_48M_SOURCE_SHIFT 3
367#define OMAP24XX_48M_SOURCE_MASK (1 << 3)
368#define OMAP2430_ALTCLK_SOURCE_SHIFT 0
369#define OMAP2430_ALTCLK_SOURCE_MASK (0x7 << 0)
370
371/* CM_CLKSEL2_PLL */
372#define OMAP24XX_CORE_CLK_SRC_SHIFT 0
373#define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0)
374
375/* CM_FCLKEN_DSP */
376#define OMAP2420_EN_IVA_COP_SHIFT 10
377#define OMAP2420_EN_IVA_COP_MASK (1 << 10)
378#define OMAP2420_EN_IVA_MPU_SHIFT 8
379#define OMAP2420_EN_IVA_MPU_MASK (1 << 8)
380#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0
381#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_MASK (1 << 0)
382
383/* CM_ICLKEN_DSP */
384#define OMAP2420_EN_DSP_IPI_SHIFT 1
385#define OMAP2420_EN_DSP_IPI_MASK (1 << 1)
386
387/* CM_IDLEST_DSP */
388#define OMAP2420_ST_IVA_MASK (1 << 8)
389#define OMAP2420_ST_IPI_MASK (1 << 1)
390#define OMAP24XX_ST_DSP_MASK (1 << 0)
391
392/* CM_AUTOIDLE_DSP */
393#define OMAP2420_AUTO_DSP_IPI_MASK (1 << 1)
394
395/* CM_CLKSEL_DSP */
396#define OMAP2420_SYNC_IVA_MASK (1 << 13)
397#define OMAP2420_CLKSEL_IVA_SHIFT 8
398#define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8)
399#define OMAP24XX_SYNC_DSP_MASK (1 << 7)
400#define OMAP24XX_CLKSEL_DSP_IF_SHIFT 5
401#define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5)
402#define OMAP24XX_CLKSEL_DSP_SHIFT 0
403#define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0)
404
405/* CM_CLKSTCTRL_DSP */
406#define OMAP2420_AUTOSTATE_IVA_SHIFT 8
407#define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8)
408#define OMAP24XX_AUTOSTATE_DSP_SHIFT 0
409#define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0)
410
411/* CM_FCLKEN_MDM */
412/* 2430 only */
413#define OMAP2430_EN_OSC_SHIFT 1
414#define OMAP2430_EN_OSC_MASK (1 << 1)
415
416/* CM_ICLKEN_MDM */
417/* 2430 only */
418#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0
419#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_MASK (1 << 0)
420
421/* CM_IDLEST_MDM specific bits */
422/* 2430 only */
423
424/* CM_AUTOIDLE_MDM */
425/* 2430 only */
426#define OMAP2430_AUTO_OSC_MASK (1 << 1)
427#define OMAP2430_AUTO_MDM_MASK (1 << 0)
428
429/* CM_CLKSEL_MDM */
430/* 2430 only */
431#define OMAP2430_SYNC_MDM_MASK (1 << 4)
432#define OMAP2430_CLKSEL_MDM_SHIFT 0
433#define OMAP2430_CLKSEL_MDM_MASK (0xf << 0)
434
435/* CM_CLKSTCTRL_MDM */
436/* 2430 only */
437#define OMAP2430_AUTOSTATE_MDM_SHIFT 0
438#define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0)
439
440/* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */
441#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0
442#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1
443
444
445#endif
1#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
2#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
3
4/*
5 * OMAP24XX Clock Management register bits
6 *
7 * Copyright (C) 2007 Texas Instruments, Inc.
8 * Copyright (C) 2007 Nokia Corporation
9 *
10 * Written by Paul Walmsley
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0)
18#define OMAP24XX_EN_DSS1_MASK (1 << 0)
19#define OMAP24XX_ST_MAILBOXES_SHIFT 30
20#define OMAP24XX_ST_HDQ_SHIFT 23
21#define OMAP2420_ST_I2C2_SHIFT 20
22#define OMAP2430_ST_I2CHS1_SHIFT 19
23#define OMAP2420_ST_I2C1_SHIFT 19
24#define OMAP2430_ST_I2CHS2_SHIFT 20
25#define OMAP24XX_ST_MCBSP2_SHIFT 16
26#define OMAP24XX_ST_MCBSP1_SHIFT 15
27#define OMAP2430_ST_MCBSP5_SHIFT 5
28#define OMAP2430_ST_MCBSP4_SHIFT 4
29#define OMAP2430_ST_MCBSP3_SHIFT 3
30#define OMAP24XX_ST_AES_SHIFT 3
31#define OMAP24XX_ST_RNG_SHIFT 2
32#define OMAP24XX_ST_SHA_SHIFT 1
33#define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13)
34#define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2)
35#define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1)
36#define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0)
37#define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0)
38#define OMAP24XX_ST_MPU_WDT_SHIFT 3
39#define OMAP24XX_ST_32KSYNC_SHIFT 1
40#define OMAP24XX_EN_54M_PLL_SHIFT 6
41#define OMAP24XX_EN_96M_PLL_SHIFT 2
42#define OMAP24XX_ST_54M_APLL_SHIFT 9
43#define OMAP24XX_ST_96M_APLL_SHIFT 8
44#define OMAP24XX_AUTO_54M_MASK (0x3 << 6)
45#define OMAP24XX_AUTO_96M_MASK (0x3 << 2)
46#define OMAP24XX_AUTO_DPLL_SHIFT 0
47#define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0)
48#define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0)
49#define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8)
50#define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0)
51#define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0)
52#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0
53#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1
54#endif