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1/*
2 * OMAP3xxx clockdomains
3 *
4 * Copyright (C) 2008-2011 Texas Instruments, Inc.
5 * Copyright (C) 2008-2010 Nokia Corporation
6 *
7 * Paul Walmsley, Jouni Högander
8 *
9 * This file contains clockdomains and clockdomain wakeup/sleep
10 * dependencies for the OMAP3xxx chips. Some notes:
11 *
12 * A useful validation rule for struct clockdomain: Any clockdomain
13 * referenced by a wkdep_srcs or sleepdep_srcs array must have a
14 * dep_bit assigned. So wkdep_srcs/sleepdep_srcs are really just
15 * software-controllable dependencies. Non-software-controllable
16 * dependencies do exist, but they are not encoded below (yet).
17 *
18 * The overly-specific dep_bit names are due to a bit name collision
19 * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
20 * value are the same for all powerdomains: 2
21 *
22 * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
23 * sanity check?
24 * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
25 */
26
27/*
28 * To-Do List
29 * -> Port the Sleep/Wakeup dependencies for the domains
30 * from the Power domain framework
31 */
32
33#include <linux/kernel.h>
34#include <linux/io.h>
35
36#include "clockdomain.h"
37#include "prm2xxx_3xxx.h"
38#include "cm2xxx_3xxx.h"
39#include "cm-regbits-34xx.h"
40#include "prm-regbits-34xx.h"
41
42/*
43 * Clockdomain dependencies for wkdeps/sleepdeps
44 *
45 * XXX Hardware dependencies (e.g., dependencies that cannot be
46 * changed in software) are not included here yet, but should be.
47 */
48
49/* OMAP3-specific possible dependencies */
50
51/*
52 * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
53 * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
54 */
55static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = {
56 { .clkdm_name = "iva2_clkdm" },
57 { .clkdm_name = "mpu_clkdm" },
58 { .clkdm_name = "wkup_clkdm" },
59 { NULL },
60};
61
62/* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
63static struct clkdm_dep per_wkdeps[] = {
64 { .clkdm_name = "core_l3_clkdm" },
65 { .clkdm_name = "core_l4_clkdm" },
66 { .clkdm_name = "iva2_clkdm" },
67 { .clkdm_name = "mpu_clkdm" },
68 { .clkdm_name = "wkup_clkdm" },
69 { NULL },
70};
71
72/* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
73static struct clkdm_dep usbhost_wkdeps[] = {
74 { .clkdm_name = "core_l3_clkdm" },
75 { .clkdm_name = "core_l4_clkdm" },
76 { .clkdm_name = "iva2_clkdm" },
77 { .clkdm_name = "mpu_clkdm" },
78 { .clkdm_name = "wkup_clkdm" },
79 { NULL },
80};
81
82/* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
83static struct clkdm_dep mpu_3xxx_wkdeps[] = {
84 { .clkdm_name = "core_l3_clkdm" },
85 { .clkdm_name = "core_l4_clkdm" },
86 { .clkdm_name = "iva2_clkdm" },
87 { .clkdm_name = "dss_clkdm" },
88 { .clkdm_name = "per_clkdm" },
89 { NULL },
90};
91
92/* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
93static struct clkdm_dep iva2_wkdeps[] = {
94 { .clkdm_name = "core_l3_clkdm" },
95 { .clkdm_name = "core_l4_clkdm" },
96 { .clkdm_name = "mpu_clkdm" },
97 { .clkdm_name = "wkup_clkdm" },
98 { .clkdm_name = "dss_clkdm" },
99 { .clkdm_name = "per_clkdm" },
100 { NULL },
101};
102
103/* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */
104static struct clkdm_dep cam_wkdeps[] = {
105 { .clkdm_name = "iva2_clkdm" },
106 { .clkdm_name = "mpu_clkdm" },
107 { .clkdm_name = "wkup_clkdm" },
108 { NULL },
109};
110
111/* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */
112static struct clkdm_dep dss_wkdeps[] = {
113 { .clkdm_name = "iva2_clkdm" },
114 { .clkdm_name = "mpu_clkdm" },
115 { .clkdm_name = "wkup_clkdm" },
116 { NULL },
117};
118
119/* 3430: PM_WKDEP_NEON: MPU */
120static struct clkdm_dep neon_wkdeps[] = {
121 { .clkdm_name = "mpu_clkdm" },
122 { NULL },
123};
124
125/* Sleep dependency source arrays for OMAP3-specific clkdms */
126
127/* 3430: CM_SLEEPDEP_DSS: MPU, IVA */
128static struct clkdm_dep dss_sleepdeps[] = {
129 { .clkdm_name = "mpu_clkdm" },
130 { .clkdm_name = "iva2_clkdm" },
131 { NULL },
132};
133
134/* 3430: CM_SLEEPDEP_PER: MPU, IVA */
135static struct clkdm_dep per_sleepdeps[] = {
136 { .clkdm_name = "mpu_clkdm" },
137 { .clkdm_name = "iva2_clkdm" },
138 { NULL },
139};
140
141/* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
142static struct clkdm_dep usbhost_sleepdeps[] = {
143 { .clkdm_name = "mpu_clkdm" },
144 { .clkdm_name = "iva2_clkdm" },
145 { NULL },
146};
147
148/* 3430: CM_SLEEPDEP_CAM: MPU */
149static struct clkdm_dep cam_sleepdeps[] = {
150 { .clkdm_name = "mpu_clkdm" },
151 { NULL },
152};
153
154/*
155 * 3430ES1: CM_SLEEPDEP_GFX: MPU
156 * 3430ES2: CM_SLEEPDEP_SGX: MPU
157 * These can share data since they will never be present simultaneously
158 * on the same device.
159 */
160static struct clkdm_dep gfx_sgx_sleepdeps[] = {
161 { .clkdm_name = "mpu_clkdm" },
162 { NULL },
163};
164
165/*
166 * OMAP3 clockdomains
167 */
168
169static struct clockdomain mpu_3xxx_clkdm = {
170 .name = "mpu_clkdm",
171 .pwrdm = { .name = "mpu_pwrdm" },
172 .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
173 .dep_bit = OMAP3430_EN_MPU_SHIFT,
174 .wkdep_srcs = mpu_3xxx_wkdeps,
175 .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
176};
177
178static struct clockdomain neon_clkdm = {
179 .name = "neon_clkdm",
180 .pwrdm = { .name = "neon_pwrdm" },
181 .flags = CLKDM_CAN_HWSUP_SWSUP,
182 .wkdep_srcs = neon_wkdeps,
183 .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
184};
185
186static struct clockdomain iva2_clkdm = {
187 .name = "iva2_clkdm",
188 .pwrdm = { .name = "iva2_pwrdm" },
189 .flags = CLKDM_CAN_HWSUP_SWSUP,
190 .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
191 .wkdep_srcs = iva2_wkdeps,
192 .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
193};
194
195static struct clockdomain gfx_3430es1_clkdm = {
196 .name = "gfx_clkdm",
197 .pwrdm = { .name = "gfx_pwrdm" },
198 .flags = CLKDM_CAN_HWSUP_SWSUP,
199 .wkdep_srcs = gfx_sgx_3xxx_wkdeps,
200 .sleepdep_srcs = gfx_sgx_sleepdeps,
201 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
202};
203
204static struct clockdomain sgx_clkdm = {
205 .name = "sgx_clkdm",
206 .pwrdm = { .name = "sgx_pwrdm" },
207 .flags = CLKDM_CAN_HWSUP_SWSUP,
208 .wkdep_srcs = gfx_sgx_3xxx_wkdeps,
209 .sleepdep_srcs = gfx_sgx_sleepdeps,
210 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
211};
212
213/*
214 * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
215 * then that information was removed from the 34xx ES2+ TRM. It is
216 * unclear whether the core is still there, but the clockdomain logic
217 * is there, and must be programmed to an appropriate state if the
218 * CORE clockdomain is to become inactive.
219 */
220static struct clockdomain d2d_clkdm = {
221 .name = "d2d_clkdm",
222 .pwrdm = { .name = "core_pwrdm" },
223 .flags = CLKDM_CAN_HWSUP_SWSUP,
224 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
225};
226
227/*
228 * XXX add usecounting for clkdm dependencies, otherwise the presence
229 * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
230 * could cause trouble
231 */
232static struct clockdomain core_l3_3xxx_clkdm = {
233 .name = "core_l3_clkdm",
234 .pwrdm = { .name = "core_pwrdm" },
235 .flags = CLKDM_CAN_HWSUP,
236 .dep_bit = OMAP3430_EN_CORE_SHIFT,
237 .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
238};
239
240/*
241 * XXX add usecounting for clkdm dependencies, otherwise the presence
242 * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
243 * could cause trouble
244 */
245static struct clockdomain core_l4_3xxx_clkdm = {
246 .name = "core_l4_clkdm",
247 .pwrdm = { .name = "core_pwrdm" },
248 .flags = CLKDM_CAN_HWSUP,
249 .dep_bit = OMAP3430_EN_CORE_SHIFT,
250 .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
251};
252
253/* Another case of bit name collisions between several registers: EN_DSS */
254static struct clockdomain dss_3xxx_clkdm = {
255 .name = "dss_clkdm",
256 .pwrdm = { .name = "dss_pwrdm" },
257 .flags = CLKDM_CAN_HWSUP_SWSUP,
258 .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
259 .wkdep_srcs = dss_wkdeps,
260 .sleepdep_srcs = dss_sleepdeps,
261 .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
262};
263
264static struct clockdomain cam_clkdm = {
265 .name = "cam_clkdm",
266 .pwrdm = { .name = "cam_pwrdm" },
267 .flags = CLKDM_CAN_HWSUP_SWSUP,
268 .wkdep_srcs = cam_wkdeps,
269 .sleepdep_srcs = cam_sleepdeps,
270 .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
271};
272
273static struct clockdomain usbhost_clkdm = {
274 .name = "usbhost_clkdm",
275 .pwrdm = { .name = "usbhost_pwrdm" },
276 .flags = CLKDM_CAN_HWSUP_SWSUP,
277 .wkdep_srcs = usbhost_wkdeps,
278 .sleepdep_srcs = usbhost_sleepdeps,
279 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
280};
281
282static struct clockdomain per_clkdm = {
283 .name = "per_clkdm",
284 .pwrdm = { .name = "per_pwrdm" },
285 .flags = CLKDM_CAN_HWSUP_SWSUP,
286 .dep_bit = OMAP3430_EN_PER_SHIFT,
287 .wkdep_srcs = per_wkdeps,
288 .sleepdep_srcs = per_sleepdeps,
289 .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
290};
291
292/*
293 * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
294 * switched of even if sdti is in use
295 */
296static struct clockdomain emu_clkdm = {
297 .name = "emu_clkdm",
298 .pwrdm = { .name = "emu_pwrdm" },
299 .flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP,
300 .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
301};
302
303static struct clockdomain dpll1_clkdm = {
304 .name = "dpll1_clkdm",
305 .pwrdm = { .name = "dpll1_pwrdm" },
306};
307
308static struct clockdomain dpll2_clkdm = {
309 .name = "dpll2_clkdm",
310 .pwrdm = { .name = "dpll2_pwrdm" },
311};
312
313static struct clockdomain dpll3_clkdm = {
314 .name = "dpll3_clkdm",
315 .pwrdm = { .name = "dpll3_pwrdm" },
316};
317
318static struct clockdomain dpll4_clkdm = {
319 .name = "dpll4_clkdm",
320 .pwrdm = { .name = "dpll4_pwrdm" },
321};
322
323static struct clockdomain dpll5_clkdm = {
324 .name = "dpll5_clkdm",
325 .pwrdm = { .name = "dpll5_pwrdm" },
326};
327
328/*
329 * Clockdomain hwsup dependencies
330 */
331
332static struct clkdm_autodep clkdm_autodeps[] = {
333 {
334 .clkdm = { .name = "mpu_clkdm" },
335 },
336 {
337 .clkdm = { .name = "iva2_clkdm" },
338 },
339 {
340 .clkdm = { .name = NULL },
341 }
342};
343
344/*
345 *
346 */
347
348static struct clockdomain *clockdomains_omap3430_common[] __initdata = {
349 &wkup_common_clkdm,
350 &cm_common_clkdm,
351 &prm_common_clkdm,
352 &mpu_3xxx_clkdm,
353 &neon_clkdm,
354 &iva2_clkdm,
355 &d2d_clkdm,
356 &core_l3_3xxx_clkdm,
357 &core_l4_3xxx_clkdm,
358 &dss_3xxx_clkdm,
359 &cam_clkdm,
360 &per_clkdm,
361 &emu_clkdm,
362 &dpll1_clkdm,
363 &dpll2_clkdm,
364 &dpll3_clkdm,
365 &dpll4_clkdm,
366 NULL
367};
368
369static struct clockdomain *clockdomains_omap3430es1[] __initdata = {
370 &gfx_3430es1_clkdm,
371 NULL,
372};
373
374static struct clockdomain *clockdomains_omap3430es2plus[] __initdata = {
375 &sgx_clkdm,
376 &dpll5_clkdm,
377 &usbhost_clkdm,
378 NULL,
379};
380
381void __init omap3xxx_clockdomains_init(void)
382{
383 struct clockdomain **sc;
384
385 if (!cpu_is_omap34xx())
386 return;
387
388 clkdm_register_platform_funcs(&omap3_clkdm_operations);
389 clkdm_register_clkdms(clockdomains_omap3430_common);
390
391 sc = (omap_rev() == OMAP3430_REV_ES1_0) ? clockdomains_omap3430es1 :
392 clockdomains_omap3430es2plus;
393
394 clkdm_register_clkdms(sc);
395
396 clkdm_register_autodeps(clkdm_autodeps);
397 clkdm_complete_init();
398}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * OMAP3xxx clockdomains
4 *
5 * Copyright (C) 2008-2011 Texas Instruments, Inc.
6 * Copyright (C) 2008-2010 Nokia Corporation
7 *
8 * Paul Walmsley, Jouni Högander
9 *
10 * This file contains clockdomains and clockdomain wakeup/sleep
11 * dependencies for the OMAP3xxx chips. Some notes:
12 *
13 * A useful validation rule for struct clockdomain: Any clockdomain
14 * referenced by a wkdep_srcs or sleepdep_srcs array must have a
15 * dep_bit assigned. So wkdep_srcs/sleepdep_srcs are really just
16 * software-controllable dependencies. Non-software-controllable
17 * dependencies do exist, but they are not encoded below (yet).
18 *
19 * The overly-specific dep_bit names are due to a bit name collision
20 * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
21 * value are the same for all powerdomains: 2
22 *
23 * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
24 * sanity check?
25 * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
26 */
27
28/*
29 * To-Do List
30 * -> Port the Sleep/Wakeup dependencies for the domains
31 * from the Power domain framework
32 */
33
34#include <linux/kernel.h>
35#include <linux/io.h>
36
37#include "soc.h"
38#include "clockdomain.h"
39#include "prm2xxx_3xxx.h"
40#include "cm2xxx_3xxx.h"
41#include "cm-regbits-34xx.h"
42#include "prm-regbits-34xx.h"
43
44/*
45 * Clockdomain dependencies for wkdeps/sleepdeps
46 *
47 * XXX Hardware dependencies (e.g., dependencies that cannot be
48 * changed in software) are not included here yet, but should be.
49 */
50
51/* OMAP3-specific possible dependencies */
52
53/*
54 * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
55 * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
56 */
57static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = {
58 { .clkdm_name = "iva2_clkdm" },
59 { .clkdm_name = "mpu_clkdm" },
60 { .clkdm_name = "wkup_clkdm" },
61 { NULL },
62};
63
64static struct clkdm_dep gfx_sgx_am35x_wkdeps[] = {
65 { .clkdm_name = "mpu_clkdm" },
66 { .clkdm_name = "wkup_clkdm" },
67 { NULL },
68};
69
70/* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
71static struct clkdm_dep per_wkdeps[] = {
72 { .clkdm_name = "core_l3_clkdm" },
73 { .clkdm_name = "core_l4_clkdm" },
74 { .clkdm_name = "iva2_clkdm" },
75 { .clkdm_name = "mpu_clkdm" },
76 { .clkdm_name = "wkup_clkdm" },
77 { NULL },
78};
79
80static struct clkdm_dep per_am35x_wkdeps[] = {
81 { .clkdm_name = "core_l3_clkdm" },
82 { .clkdm_name = "core_l4_clkdm" },
83 { .clkdm_name = "mpu_clkdm" },
84 { .clkdm_name = "wkup_clkdm" },
85 { NULL },
86};
87
88/* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
89static struct clkdm_dep usbhost_wkdeps[] = {
90 { .clkdm_name = "core_l3_clkdm" },
91 { .clkdm_name = "core_l4_clkdm" },
92 { .clkdm_name = "iva2_clkdm" },
93 { .clkdm_name = "mpu_clkdm" },
94 { .clkdm_name = "wkup_clkdm" },
95 { NULL },
96};
97
98static struct clkdm_dep usbhost_am35x_wkdeps[] = {
99 { .clkdm_name = "core_l3_clkdm" },
100 { .clkdm_name = "core_l4_clkdm" },
101 { .clkdm_name = "mpu_clkdm" },
102 { .clkdm_name = "wkup_clkdm" },
103 { NULL },
104};
105
106/* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
107static struct clkdm_dep mpu_3xxx_wkdeps[] = {
108 { .clkdm_name = "core_l3_clkdm" },
109 { .clkdm_name = "core_l4_clkdm" },
110 { .clkdm_name = "iva2_clkdm" },
111 { .clkdm_name = "dss_clkdm" },
112 { .clkdm_name = "per_clkdm" },
113 { NULL },
114};
115
116static struct clkdm_dep mpu_am35x_wkdeps[] = {
117 { .clkdm_name = "core_l3_clkdm" },
118 { .clkdm_name = "core_l4_clkdm" },
119 { .clkdm_name = "dss_clkdm" },
120 { .clkdm_name = "per_clkdm" },
121 { NULL },
122};
123
124/* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
125static struct clkdm_dep iva2_wkdeps[] = {
126 { .clkdm_name = "core_l3_clkdm" },
127 { .clkdm_name = "core_l4_clkdm" },
128 { .clkdm_name = "mpu_clkdm" },
129 { .clkdm_name = "wkup_clkdm" },
130 { .clkdm_name = "dss_clkdm" },
131 { .clkdm_name = "per_clkdm" },
132 { NULL },
133};
134
135/* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */
136static struct clkdm_dep cam_wkdeps[] = {
137 { .clkdm_name = "iva2_clkdm" },
138 { .clkdm_name = "mpu_clkdm" },
139 { .clkdm_name = "wkup_clkdm" },
140 { NULL },
141};
142
143/* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */
144static struct clkdm_dep dss_wkdeps[] = {
145 { .clkdm_name = "iva2_clkdm" },
146 { .clkdm_name = "mpu_clkdm" },
147 { .clkdm_name = "wkup_clkdm" },
148 { NULL },
149};
150
151static struct clkdm_dep dss_am35x_wkdeps[] = {
152 { .clkdm_name = "mpu_clkdm" },
153 { .clkdm_name = "wkup_clkdm" },
154 { NULL },
155};
156
157/* 3430: PM_WKDEP_NEON: MPU */
158static struct clkdm_dep neon_wkdeps[] = {
159 { .clkdm_name = "mpu_clkdm" },
160 { NULL },
161};
162
163/* Sleep dependency source arrays for OMAP3-specific clkdms */
164
165/* 3430: CM_SLEEPDEP_DSS: MPU, IVA */
166static struct clkdm_dep dss_sleepdeps[] = {
167 { .clkdm_name = "mpu_clkdm" },
168 { .clkdm_name = "iva2_clkdm" },
169 { NULL },
170};
171
172static struct clkdm_dep dss_am35x_sleepdeps[] = {
173 { .clkdm_name = "mpu_clkdm" },
174 { NULL },
175};
176
177/* 3430: CM_SLEEPDEP_PER: MPU, IVA */
178static struct clkdm_dep per_sleepdeps[] = {
179 { .clkdm_name = "mpu_clkdm" },
180 { .clkdm_name = "iva2_clkdm" },
181 { NULL },
182};
183
184static struct clkdm_dep per_am35x_sleepdeps[] = {
185 { .clkdm_name = "mpu_clkdm" },
186 { NULL },
187};
188
189/* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
190static struct clkdm_dep usbhost_sleepdeps[] = {
191 { .clkdm_name = "mpu_clkdm" },
192 { .clkdm_name = "iva2_clkdm" },
193 { NULL },
194};
195
196static struct clkdm_dep usbhost_am35x_sleepdeps[] = {
197 { .clkdm_name = "mpu_clkdm" },
198 { NULL },
199};
200
201/* 3430: CM_SLEEPDEP_CAM: MPU */
202static struct clkdm_dep cam_sleepdeps[] = {
203 { .clkdm_name = "mpu_clkdm" },
204 { NULL },
205};
206
207/*
208 * 3430ES1: CM_SLEEPDEP_GFX: MPU
209 * 3430ES2: CM_SLEEPDEP_SGX: MPU
210 * These can share data since they will never be present simultaneously
211 * on the same device.
212 */
213static struct clkdm_dep gfx_sgx_sleepdeps[] = {
214 { .clkdm_name = "mpu_clkdm" },
215 { NULL },
216};
217
218/*
219 * OMAP3 clockdomains
220 */
221
222static struct clockdomain mpu_3xxx_clkdm = {
223 .name = "mpu_clkdm",
224 .pwrdm = { .name = "mpu_pwrdm" },
225 .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
226 .dep_bit = OMAP3430_EN_MPU_SHIFT,
227 .wkdep_srcs = mpu_3xxx_wkdeps,
228 .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
229};
230
231static struct clockdomain mpu_am35x_clkdm = {
232 .name = "mpu_clkdm",
233 .pwrdm = { .name = "mpu_pwrdm" },
234 .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
235 .dep_bit = OMAP3430_EN_MPU_SHIFT,
236 .wkdep_srcs = mpu_am35x_wkdeps,
237 .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
238};
239
240static struct clockdomain neon_clkdm = {
241 .name = "neon_clkdm",
242 .pwrdm = { .name = "neon_pwrdm" },
243 .flags = CLKDM_CAN_HWSUP_SWSUP,
244 .wkdep_srcs = neon_wkdeps,
245 .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
246};
247
248static struct clockdomain iva2_clkdm = {
249 .name = "iva2_clkdm",
250 .pwrdm = { .name = "iva2_pwrdm" },
251 .flags = CLKDM_CAN_SWSUP,
252 .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
253 .wkdep_srcs = iva2_wkdeps,
254 .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
255};
256
257static struct clockdomain gfx_3430es1_clkdm = {
258 .name = "gfx_clkdm",
259 .pwrdm = { .name = "gfx_pwrdm" },
260 .flags = CLKDM_CAN_HWSUP_SWSUP,
261 .wkdep_srcs = gfx_sgx_3xxx_wkdeps,
262 .sleepdep_srcs = gfx_sgx_sleepdeps,
263 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
264};
265
266static struct clockdomain sgx_clkdm = {
267 .name = "sgx_clkdm",
268 .pwrdm = { .name = "sgx_pwrdm" },
269 .flags = CLKDM_CAN_HWSUP_SWSUP,
270 .wkdep_srcs = gfx_sgx_3xxx_wkdeps,
271 .sleepdep_srcs = gfx_sgx_sleepdeps,
272 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
273};
274
275static struct clockdomain sgx_am35x_clkdm = {
276 .name = "sgx_clkdm",
277 .pwrdm = { .name = "sgx_pwrdm" },
278 .flags = CLKDM_CAN_HWSUP_SWSUP,
279 .wkdep_srcs = gfx_sgx_am35x_wkdeps,
280 .sleepdep_srcs = gfx_sgx_sleepdeps,
281 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
282};
283
284/*
285 * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
286 * then that information was removed from the 34xx ES2+ TRM. It is
287 * unclear whether the core is still there, but the clockdomain logic
288 * is there, and must be programmed to an appropriate state if the
289 * CORE clockdomain is to become inactive.
290 */
291static struct clockdomain d2d_clkdm = {
292 .name = "d2d_clkdm",
293 .pwrdm = { .name = "core_pwrdm" },
294 .flags = CLKDM_CAN_HWSUP_SWSUP,
295 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
296};
297
298/*
299 * XXX add usecounting for clkdm dependencies, otherwise the presence
300 * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
301 * could cause trouble
302 */
303static struct clockdomain core_l3_3xxx_clkdm = {
304 .name = "core_l3_clkdm",
305 .pwrdm = { .name = "core_pwrdm" },
306 .flags = CLKDM_CAN_HWSUP,
307 .dep_bit = OMAP3430_EN_CORE_SHIFT,
308 .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
309};
310
311/*
312 * XXX add usecounting for clkdm dependencies, otherwise the presence
313 * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
314 * could cause trouble
315 */
316static struct clockdomain core_l4_3xxx_clkdm = {
317 .name = "core_l4_clkdm",
318 .pwrdm = { .name = "core_pwrdm" },
319 .flags = CLKDM_CAN_HWSUP,
320 .dep_bit = OMAP3430_EN_CORE_SHIFT,
321 .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
322};
323
324/* Another case of bit name collisions between several registers: EN_DSS */
325static struct clockdomain dss_3xxx_clkdm = {
326 .name = "dss_clkdm",
327 .pwrdm = { .name = "dss_pwrdm" },
328 .flags = CLKDM_CAN_HWSUP_SWSUP,
329 .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
330 .wkdep_srcs = dss_wkdeps,
331 .sleepdep_srcs = dss_sleepdeps,
332 .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
333};
334
335static struct clockdomain dss_am35x_clkdm = {
336 .name = "dss_clkdm",
337 .pwrdm = { .name = "dss_pwrdm" },
338 .flags = CLKDM_CAN_HWSUP_SWSUP,
339 .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
340 .wkdep_srcs = dss_am35x_wkdeps,
341 .sleepdep_srcs = dss_am35x_sleepdeps,
342 .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
343};
344
345static struct clockdomain cam_clkdm = {
346 .name = "cam_clkdm",
347 .pwrdm = { .name = "cam_pwrdm" },
348 .flags = CLKDM_CAN_HWSUP_SWSUP,
349 .wkdep_srcs = cam_wkdeps,
350 .sleepdep_srcs = cam_sleepdeps,
351 .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
352};
353
354static struct clockdomain usbhost_clkdm = {
355 .name = "usbhost_clkdm",
356 .pwrdm = { .name = "usbhost_pwrdm" },
357 .flags = CLKDM_CAN_HWSUP_SWSUP,
358 .wkdep_srcs = usbhost_wkdeps,
359 .sleepdep_srcs = usbhost_sleepdeps,
360 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
361};
362
363static struct clockdomain usbhost_am35x_clkdm = {
364 .name = "usbhost_clkdm",
365 .pwrdm = { .name = "core_pwrdm" },
366 .flags = CLKDM_CAN_HWSUP_SWSUP,
367 .wkdep_srcs = usbhost_am35x_wkdeps,
368 .sleepdep_srcs = usbhost_am35x_sleepdeps,
369 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
370};
371
372static struct clockdomain per_clkdm = {
373 .name = "per_clkdm",
374 .pwrdm = { .name = "per_pwrdm" },
375 .flags = CLKDM_CAN_HWSUP_SWSUP,
376 .dep_bit = OMAP3430_EN_PER_SHIFT,
377 .wkdep_srcs = per_wkdeps,
378 .sleepdep_srcs = per_sleepdeps,
379 .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
380};
381
382static struct clockdomain per_am35x_clkdm = {
383 .name = "per_clkdm",
384 .pwrdm = { .name = "per_pwrdm" },
385 .flags = CLKDM_CAN_HWSUP_SWSUP,
386 .dep_bit = OMAP3430_EN_PER_SHIFT,
387 .wkdep_srcs = per_am35x_wkdeps,
388 .sleepdep_srcs = per_am35x_sleepdeps,
389 .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
390};
391
392static struct clockdomain emu_clkdm = {
393 .name = "emu_clkdm",
394 .pwrdm = { .name = "emu_pwrdm" },
395 .flags = (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_SWSUP |
396 CLKDM_MISSING_IDLE_REPORTING),
397 .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
398};
399
400static struct clockdomain dpll1_clkdm = {
401 .name = "dpll1_clkdm",
402 .pwrdm = { .name = "dpll1_pwrdm" },
403};
404
405static struct clockdomain dpll2_clkdm = {
406 .name = "dpll2_clkdm",
407 .pwrdm = { .name = "dpll2_pwrdm" },
408};
409
410static struct clockdomain dpll3_clkdm = {
411 .name = "dpll3_clkdm",
412 .pwrdm = { .name = "dpll3_pwrdm" },
413};
414
415static struct clockdomain dpll4_clkdm = {
416 .name = "dpll4_clkdm",
417 .pwrdm = { .name = "dpll4_pwrdm" },
418};
419
420static struct clockdomain dpll5_clkdm = {
421 .name = "dpll5_clkdm",
422 .pwrdm = { .name = "dpll5_pwrdm" },
423};
424
425/*
426 * Clockdomain hwsup dependencies
427 */
428
429static struct clkdm_autodep clkdm_autodeps[] = {
430 {
431 .clkdm = { .name = "mpu_clkdm" },
432 },
433 {
434 .clkdm = { .name = "iva2_clkdm" },
435 },
436 {
437 .clkdm = { .name = NULL },
438 }
439};
440
441static struct clkdm_autodep clkdm_am35x_autodeps[] = {
442 {
443 .clkdm = { .name = "mpu_clkdm" },
444 },
445 {
446 .clkdm = { .name = NULL },
447 }
448};
449
450/*
451 *
452 */
453
454static struct clockdomain *clockdomains_common[] __initdata = {
455 &wkup_common_clkdm,
456 &neon_clkdm,
457 &core_l3_3xxx_clkdm,
458 &core_l4_3xxx_clkdm,
459 &emu_clkdm,
460 &dpll1_clkdm,
461 &dpll3_clkdm,
462 &dpll4_clkdm,
463 NULL
464};
465
466static struct clockdomain *clockdomains_omap3430[] __initdata = {
467 &mpu_3xxx_clkdm,
468 &iva2_clkdm,
469 &d2d_clkdm,
470 &dss_3xxx_clkdm,
471 &cam_clkdm,
472 &per_clkdm,
473 &dpll2_clkdm,
474 NULL
475};
476
477static struct clockdomain *clockdomains_omap3430es1[] __initdata = {
478 &gfx_3430es1_clkdm,
479 NULL,
480};
481
482static struct clockdomain *clockdomains_omap3430es2plus[] __initdata = {
483 &sgx_clkdm,
484 &dpll5_clkdm,
485 &usbhost_clkdm,
486 NULL,
487};
488
489static struct clockdomain *clockdomains_am35x[] __initdata = {
490 &mpu_am35x_clkdm,
491 &sgx_am35x_clkdm,
492 &dss_am35x_clkdm,
493 &per_am35x_clkdm,
494 &usbhost_am35x_clkdm,
495 &dpll5_clkdm,
496 NULL
497};
498
499void __init omap3xxx_clockdomains_init(void)
500{
501 struct clockdomain **sc;
502 unsigned int rev;
503
504 if (!cpu_is_omap34xx())
505 return;
506
507 clkdm_register_platform_funcs(&omap3_clkdm_operations);
508 clkdm_register_clkdms(clockdomains_common);
509
510 rev = omap_rev();
511
512 if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
513 clkdm_register_clkdms(clockdomains_am35x);
514 clkdm_register_autodeps(clkdm_am35x_autodeps);
515 } else {
516 clkdm_register_clkdms(clockdomains_omap3430);
517
518 sc = (rev == OMAP3430_REV_ES1_0) ?
519 clockdomains_omap3430es1 : clockdomains_omap3430es2plus;
520
521 clkdm_register_clkdms(sc);
522 clkdm_register_autodeps(clkdm_autodeps);
523 }
524
525 clkdm_complete_init();
526}