1/*
   2 * OMAP3 clock data
   3 *
   4 * Copyright (C) 2007-2010, 2012 Texas Instruments, Inc.
   5 * Copyright (C) 2007-2011 Nokia Corporation
   6 *
   7 * Written by Paul Walmsley
   8 * With many device clock fixes by Kevin Hilman and Jouni Högander
   9 * DPLL bypass clock support added by Roman Tereshonkov
  10 *
  11 */
  12
  13/*
  14 * Virtual clocks are introduced as convenient tools.
  15 * They are sources for other clocks and not supposed
  16 * to be requested from drivers directly.
  17 */
  18
  19#include <linux/kernel.h>
  20#include <linux/clk.h>
  21#include <linux/list.h>
  22#include <linux/io.h>
  23
  24#include <plat/hardware.h>
  25#include <plat/clkdev_omap.h>
  26
  27#include "iomap.h"
  28#include "clock.h"
  29#include "clock3xxx.h"
  30#include "clock34xx.h"
  31#include "clock36xx.h"
  32#include "clock3517.h"
  33#include "cm2xxx_3xxx.h"
  34#include "cm-regbits-34xx.h"
  35#include "prm2xxx_3xxx.h"
  36#include "prm-regbits-34xx.h"
  37#include "control.h"
  38
  39/*
  40 * clocks
  41 */
  42
  43#define OMAP_CM_REGADDR		OMAP34XX_CM_REGADDR
  44
  45/* Maximum DPLL multiplier, divider values for OMAP3 */
  46#define OMAP3_MAX_DPLL_MULT		2047
  47#define OMAP3630_MAX_JTYPE_DPLL_MULT	4095
  48#define OMAP3_MAX_DPLL_DIV		128
  49
  50/*
  51 * DPLL1 supplies clock to the MPU.
  52 * DPLL2 supplies clock to the IVA2.
  53 * DPLL3 supplies CORE domain clocks.
  54 * DPLL4 supplies peripheral clocks.
  55 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  56 */
  57
  58/* Forward declarations for DPLL bypass clocks */
  59static struct clk dpll1_fck;
  60static struct clk dpll2_fck;
  61
  62/* PRM CLOCKS */
  63
  64/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  65static struct clk omap_32k_fck = {
  66	.name		= "omap_32k_fck",
  67	.ops		= &clkops_null,
  68	.rate		= 32768,
  69};
  70
  71static struct clk secure_32k_fck = {
  72	.name		= "secure_32k_fck",
  73	.ops		= &clkops_null,
  74	.rate		= 32768,
  75};
  76
  77/* Virtual source clocks for osc_sys_ck */
  78static struct clk virt_12m_ck = {
  79	.name		= "virt_12m_ck",
  80	.ops		= &clkops_null,
  81	.rate		= 12000000,
  82};
  83
  84static struct clk virt_13m_ck = {
  85	.name		= "virt_13m_ck",
  86	.ops		= &clkops_null,
  87	.rate		= 13000000,
  88};
  89
  90static struct clk virt_16_8m_ck = {
  91	.name		= "virt_16_8m_ck",
  92	.ops		= &clkops_null,
  93	.rate		= 16800000,
  94};
  95
  96static struct clk virt_19_2m_ck = {
  97	.name		= "virt_19_2m_ck",
  98	.ops		= &clkops_null,
  99	.rate		= 19200000,
 100};
 101
 102static struct clk virt_26m_ck = {
 103	.name		= "virt_26m_ck",
 104	.ops		= &clkops_null,
 105	.rate		= 26000000,
 106};
 107
 108static struct clk virt_38_4m_ck = {
 109	.name		= "virt_38_4m_ck",
 110	.ops		= &clkops_null,
 111	.rate		= 38400000,
 112};
 113
 114static const struct clksel_rate osc_sys_12m_rates[] = {
 115	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 116	{ .div = 0 }
 117};
 118
 119static const struct clksel_rate osc_sys_13m_rates[] = {
 120	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 121	{ .div = 0 }
 122};
 123
 124static const struct clksel_rate osc_sys_16_8m_rates[] = {
 125	{ .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
 126	{ .div = 0 }
 127};
 128
 129static const struct clksel_rate osc_sys_19_2m_rates[] = {
 130	{ .div = 1, .val = 2, .flags = RATE_IN_3XXX },
 131	{ .div = 0 }
 132};
 133
 134static const struct clksel_rate osc_sys_26m_rates[] = {
 135	{ .div = 1, .val = 3, .flags = RATE_IN_3XXX },
 136	{ .div = 0 }
 137};
 138
 139static const struct clksel_rate osc_sys_38_4m_rates[] = {
 140	{ .div = 1, .val = 4, .flags = RATE_IN_3XXX },
 141	{ .div = 0 }
 142};
 143
 144static const struct clksel osc_sys_clksel[] = {
 145	{ .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 146	{ .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 147	{ .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 148	{ .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 149	{ .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 150	{ .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 151	{ .parent = NULL },
 152};
 153
 154/* Oscillator clock */
 155/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 156static struct clk osc_sys_ck = {
 157	.name		= "osc_sys_ck",
 158	.ops		= &clkops_null,
 159	.init		= &omap2_init_clksel_parent,
 160	.clksel_reg	= OMAP3430_PRM_CLKSEL,
 161	.clksel_mask	= OMAP3430_SYS_CLKIN_SEL_MASK,
 162	.clksel		= osc_sys_clksel,
 163	/* REVISIT: deal with autoextclkmode? */
 164	.recalc		= &omap2_clksel_recalc,
 165};
 166
 167static const struct clksel_rate div2_rates[] = {
 168	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 169	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 170	{ .div = 0 }
 171};
 172
 173static const struct clksel sys_clksel[] = {
 174	{ .parent = &osc_sys_ck, .rates = div2_rates },
 175	{ .parent = NULL }
 176};
 177
 178/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 179/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 180static struct clk sys_ck = {
 181	.name		= "sys_ck",
 182	.ops		= &clkops_null,
 183	.parent		= &osc_sys_ck,
 184	.init		= &omap2_init_clksel_parent,
 185	.clksel_reg	= OMAP3430_PRM_CLKSRC_CTRL,
 186	.clksel_mask	= OMAP_SYSCLKDIV_MASK,
 187	.clksel		= sys_clksel,
 188	.recalc		= &omap2_clksel_recalc,
 189};
 190
 191static struct clk sys_altclk = {
 192	.name		= "sys_altclk",
 193	.ops		= &clkops_null,
 194};
 195
 196/* Optional external clock input for some McBSPs */
 197static struct clk mcbsp_clks = {
 198	.name		= "mcbsp_clks",
 199	.ops		= &clkops_null,
 200};
 201
 202/* PRM EXTERNAL CLOCK OUTPUT */
 203
 204static struct clk sys_clkout1 = {
 205	.name		= "sys_clkout1",
 206	.ops		= &clkops_omap2_dflt,
 207	.parent		= &osc_sys_ck,
 208	.enable_reg	= OMAP3430_PRM_CLKOUT_CTRL,
 209	.enable_bit	= OMAP3430_CLKOUT_EN_SHIFT,
 210	.recalc		= &followparent_recalc,
 211};
 212
 213/* DPLLS */
 214
 215/* CM CLOCKS */
 216
 217static const struct clksel_rate div16_dpll_rates[] = {
 218	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 219	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 220	{ .div = 3, .val = 3, .flags = RATE_IN_3XXX },
 221	{ .div = 4, .val = 4, .flags = RATE_IN_3XXX },
 222	{ .div = 5, .val = 5, .flags = RATE_IN_3XXX },
 223	{ .div = 6, .val = 6, .flags = RATE_IN_3XXX },
 224	{ .div = 7, .val = 7, .flags = RATE_IN_3XXX },
 225	{ .div = 8, .val = 8, .flags = RATE_IN_3XXX },
 226	{ .div = 9, .val = 9, .flags = RATE_IN_3XXX },
 227	{ .div = 10, .val = 10, .flags = RATE_IN_3XXX },
 228	{ .div = 11, .val = 11, .flags = RATE_IN_3XXX },
 229	{ .div = 12, .val = 12, .flags = RATE_IN_3XXX },
 230	{ .div = 13, .val = 13, .flags = RATE_IN_3XXX },
 231	{ .div = 14, .val = 14, .flags = RATE_IN_3XXX },
 232	{ .div = 15, .val = 15, .flags = RATE_IN_3XXX },
 233	{ .div = 16, .val = 16, .flags = RATE_IN_3XXX },
 234	{ .div = 0 }
 235};
 236
 237static const struct clksel_rate dpll4_rates[] = {
 238	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 239	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 240	{ .div = 3, .val = 3, .flags = RATE_IN_3XXX },
 241	{ .div = 4, .val = 4, .flags = RATE_IN_3XXX },
 242	{ .div = 5, .val = 5, .flags = RATE_IN_3XXX },
 243	{ .div = 6, .val = 6, .flags = RATE_IN_3XXX },
 244	{ .div = 7, .val = 7, .flags = RATE_IN_3XXX },
 245	{ .div = 8, .val = 8, .flags = RATE_IN_3XXX },
 246	{ .div = 9, .val = 9, .flags = RATE_IN_3XXX },
 247	{ .div = 10, .val = 10, .flags = RATE_IN_3XXX },
 248	{ .div = 11, .val = 11, .flags = RATE_IN_3XXX },
 249	{ .div = 12, .val = 12, .flags = RATE_IN_3XXX },
 250	{ .div = 13, .val = 13, .flags = RATE_IN_3XXX },
 251	{ .div = 14, .val = 14, .flags = RATE_IN_3XXX },
 252	{ .div = 15, .val = 15, .flags = RATE_IN_3XXX },
 253	{ .div = 16, .val = 16, .flags = RATE_IN_3XXX },
 254	{ .div = 17, .val = 17, .flags = RATE_IN_36XX },
 255	{ .div = 18, .val = 18, .flags = RATE_IN_36XX },
 256	{ .div = 19, .val = 19, .flags = RATE_IN_36XX },
 257	{ .div = 20, .val = 20, .flags = RATE_IN_36XX },
 258	{ .div = 21, .val = 21, .flags = RATE_IN_36XX },
 259	{ .div = 22, .val = 22, .flags = RATE_IN_36XX },
 260	{ .div = 23, .val = 23, .flags = RATE_IN_36XX },
 261	{ .div = 24, .val = 24, .flags = RATE_IN_36XX },
 262	{ .div = 25, .val = 25, .flags = RATE_IN_36XX },
 263	{ .div = 26, .val = 26, .flags = RATE_IN_36XX },
 264	{ .div = 27, .val = 27, .flags = RATE_IN_36XX },
 265	{ .div = 28, .val = 28, .flags = RATE_IN_36XX },
 266	{ .div = 29, .val = 29, .flags = RATE_IN_36XX },
 267	{ .div = 30, .val = 30, .flags = RATE_IN_36XX },
 268	{ .div = 31, .val = 31, .flags = RATE_IN_36XX },
 269	{ .div = 32, .val = 32, .flags = RATE_IN_36XX },
 270	{ .div = 0 }
 271};
 272
 273/* DPLL1 */
 274/* MPU clock source */
 275/* Type: DPLL */
 276static struct dpll_data dpll1_dd = {
 277	.mult_div1_reg	= OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 278	.mult_mask	= OMAP3430_MPU_DPLL_MULT_MASK,
 279	.div1_mask	= OMAP3430_MPU_DPLL_DIV_MASK,
 280	.clk_bypass	= &dpll1_fck,
 281	.clk_ref	= &sys_ck,
 282	.freqsel_mask	= OMAP3430_MPU_DPLL_FREQSEL_MASK,
 283	.control_reg	= OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 284	.enable_mask	= OMAP3430_EN_MPU_DPLL_MASK,
 285	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 286	.auto_recal_bit	= OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 287	.recal_en_bit	= OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 288	.recal_st_bit	= OMAP3430_MPU_DPLL_ST_SHIFT,
 289	.autoidle_reg	= OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 290	.autoidle_mask	= OMAP3430_AUTO_MPU_DPLL_MASK,
 291	.idlest_reg	= OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 292	.idlest_mask	= OMAP3430_ST_MPU_CLK_MASK,
 293	.max_multiplier = OMAP3_MAX_DPLL_MULT,
 294	.min_divider	= 1,
 295	.max_divider	= OMAP3_MAX_DPLL_DIV,
 296};
 297
 298static struct clk dpll1_ck = {
 299	.name		= "dpll1_ck",
 300	.ops		= &clkops_omap3_noncore_dpll_ops,
 301	.parent		= &sys_ck,
 302	.dpll_data	= &dpll1_dd,
 303	.round_rate	= &omap2_dpll_round_rate,
 304	.set_rate	= &omap3_noncore_dpll_set_rate,
 305	.clkdm_name	= "dpll1_clkdm",
 306	.recalc		= &omap3_dpll_recalc,
 307};
 308
 309/*
 310 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 311 * DPLL isn't bypassed.
 312 */
 313static struct clk dpll1_x2_ck = {
 314	.name		= "dpll1_x2_ck",
 315	.ops		= &clkops_null,
 316	.parent		= &dpll1_ck,
 317	.clkdm_name	= "dpll1_clkdm",
 318	.recalc		= &omap3_clkoutx2_recalc,
 319};
 320
 321/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 322static const struct clksel div16_dpll1_x2m2_clksel[] = {
 323	{ .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 324	{ .parent = NULL }
 325};
 326
 327/*
 328 * Does not exist in the TRM - needed to separate the M2 divider from
 329 * bypass selection in mpu_ck
 330 */
 331static struct clk dpll1_x2m2_ck = {
 332	.name		= "dpll1_x2m2_ck",
 333	.ops		= &clkops_null,
 334	.parent		= &dpll1_x2_ck,
 335	.init		= &omap2_init_clksel_parent,
 336	.clksel_reg	= OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 337	.clksel_mask	= OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 338	.clksel		= div16_dpll1_x2m2_clksel,
 339	.clkdm_name	= "dpll1_clkdm",
 340	.recalc		= &omap2_clksel_recalc,
 341};
 342
 343/* DPLL2 */
 344/* IVA2 clock source */
 345/* Type: DPLL */
 346
 347static struct dpll_data dpll2_dd = {
 348	.mult_div1_reg	= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 349	.mult_mask	= OMAP3430_IVA2_DPLL_MULT_MASK,
 350	.div1_mask	= OMAP3430_IVA2_DPLL_DIV_MASK,
 351	.clk_bypass	= &dpll2_fck,
 352	.clk_ref	= &sys_ck,
 353	.freqsel_mask	= OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 354	.control_reg	= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 355	.enable_mask	= OMAP3430_EN_IVA2_DPLL_MASK,
 356	.modes		= (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 357				(1 << DPLL_LOW_POWER_BYPASS),
 358	.auto_recal_bit	= OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 359	.recal_en_bit	= OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 360	.recal_st_bit	= OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 361	.autoidle_reg	= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 362	.autoidle_mask	= OMAP3430_AUTO_IVA2_DPLL_MASK,
 363	.idlest_reg	= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 364	.idlest_mask	= OMAP3430_ST_IVA2_CLK_MASK,
 365	.max_multiplier = OMAP3_MAX_DPLL_MULT,
 366	.min_divider	= 1,
 367	.max_divider	= OMAP3_MAX_DPLL_DIV,
 368};
 369
 370static struct clk dpll2_ck = {
 371	.name		= "dpll2_ck",
 372	.ops		= &clkops_omap3_noncore_dpll_ops,
 373	.parent		= &sys_ck,
 374	.dpll_data	= &dpll2_dd,
 375	.round_rate	= &omap2_dpll_round_rate,
 376	.set_rate	= &omap3_noncore_dpll_set_rate,
 377	.clkdm_name	= "dpll2_clkdm",
 378	.recalc		= &omap3_dpll_recalc,
 379};
 380
 381static const struct clksel div16_dpll2_m2x2_clksel[] = {
 382	{ .parent = &dpll2_ck, .rates = div16_dpll_rates },
 383	{ .parent = NULL }
 384};
 385
 386/*
 387 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 388 * or CLKOUTX2. CLKOUT seems most plausible.
 389 */
 390static struct clk dpll2_m2_ck = {
 391	.name		= "dpll2_m2_ck",
 392	.ops		= &clkops_null,
 393	.parent		= &dpll2_ck,
 394	.init		= &omap2_init_clksel_parent,
 395	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
 396					  OMAP3430_CM_CLKSEL2_PLL),
 397	.clksel_mask	= OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 398	.clksel		= div16_dpll2_m2x2_clksel,
 399	.clkdm_name	= "dpll2_clkdm",
 400	.recalc		= &omap2_clksel_recalc,
 401};
 402
 403/*
 404 * DPLL3
 405 * Source clock for all interfaces and for some device fclks
 406 * REVISIT: Also supports fast relock bypass - not included below
 407 */
 408static struct dpll_data dpll3_dd = {
 409	.mult_div1_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 410	.mult_mask	= OMAP3430_CORE_DPLL_MULT_MASK,
 411	.div1_mask	= OMAP3430_CORE_DPLL_DIV_MASK,
 412	.clk_bypass	= &sys_ck,
 413	.clk_ref	= &sys_ck,
 414	.freqsel_mask	= OMAP3430_CORE_DPLL_FREQSEL_MASK,
 415	.control_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 416	.enable_mask	= OMAP3430_EN_CORE_DPLL_MASK,
 417	.auto_recal_bit	= OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 418	.recal_en_bit	= OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 419	.recal_st_bit	= OMAP3430_CORE_DPLL_ST_SHIFT,
 420	.autoidle_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 421	.autoidle_mask	= OMAP3430_AUTO_CORE_DPLL_MASK,
 422	.idlest_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 423	.idlest_mask	= OMAP3430_ST_CORE_CLK_MASK,
 424	.max_multiplier = OMAP3_MAX_DPLL_MULT,
 425	.min_divider	= 1,
 426	.max_divider	= OMAP3_MAX_DPLL_DIV,
 427};
 428
 429static struct clk dpll3_ck = {
 430	.name		= "dpll3_ck",
 431	.ops		= &clkops_omap3_core_dpll_ops,
 432	.parent		= &sys_ck,
 433	.dpll_data	= &dpll3_dd,
 434	.round_rate	= &omap2_dpll_round_rate,
 435	.clkdm_name	= "dpll3_clkdm",
 436	.recalc		= &omap3_dpll_recalc,
 437};
 438
 439/*
 440 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 441 * DPLL isn't bypassed
 442 */
 443static struct clk dpll3_x2_ck = {
 444	.name		= "dpll3_x2_ck",
 445	.ops		= &clkops_null,
 446	.parent		= &dpll3_ck,
 447	.clkdm_name	= "dpll3_clkdm",
 448	.recalc		= &omap3_clkoutx2_recalc,
 449};
 450
 451static const struct clksel_rate div31_dpll3_rates[] = {
 452	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 453	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 454	{ .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS_36XX },
 455	{ .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS_36XX },
 456	{ .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
 457	{ .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS_36XX },
 458	{ .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS_36XX },
 459	{ .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS_36XX },
 460	{ .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS_36XX },
 461	{ .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS_36XX },
 462	{ .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS_36XX },
 463	{ .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS_36XX },
 464	{ .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS_36XX },
 465	{ .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS_36XX },
 466	{ .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS_36XX },
 467	{ .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS_36XX },
 468	{ .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS_36XX },
 469	{ .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS_36XX },
 470	{ .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS_36XX },
 471	{ .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS_36XX },
 472	{ .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS_36XX },
 473	{ .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS_36XX },
 474	{ .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS_36XX },
 475	{ .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS_36XX },
 476	{ .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS_36XX },
 477	{ .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS_36XX },
 478	{ .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS_36XX },
 479	{ .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS_36XX },
 480	{ .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS_36XX },
 481	{ .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS_36XX },
 482	{ .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS_36XX },
 483	{ .div = 0 },
 484};
 485
 486static const struct clksel div31_dpll3m2_clksel[] = {
 487	{ .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 488	{ .parent = NULL }
 489};
 490
 491/* DPLL3 output M2 - primary control point for CORE speed */
 492static struct clk dpll3_m2_ck = {
 493	.name		= "dpll3_m2_ck",
 494	.ops		= &clkops_null,
 495	.parent		= &dpll3_ck,
 496	.init		= &omap2_init_clksel_parent,
 497	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 498	.clksel_mask	= OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 499	.clksel		= div31_dpll3m2_clksel,
 500	.clkdm_name	= "dpll3_clkdm",
 501	.round_rate	= &omap2_clksel_round_rate,
 502	.set_rate	= &omap3_core_dpll_m2_set_rate,
 503	.recalc		= &omap2_clksel_recalc,
 504};
 505
 506static struct clk core_ck = {
 507	.name		= "core_ck",
 508	.ops		= &clkops_null,
 509	.parent		= &dpll3_m2_ck,
 510	.recalc		= &followparent_recalc,
 511};
 512
 513static struct clk dpll3_m2x2_ck = {
 514	.name		= "dpll3_m2x2_ck",
 515	.ops		= &clkops_null,
 516	.parent		= &dpll3_m2_ck,
 517	.clkdm_name	= "dpll3_clkdm",
 518	.recalc		= &omap3_clkoutx2_recalc,
 519};
 520
 521/* The PWRDN bit is apparently only available on 3430ES2 and above */
 522static const struct clksel div16_dpll3_clksel[] = {
 523	{ .parent = &dpll3_ck, .rates = div16_dpll_rates },
 524	{ .parent = NULL }
 525};
 526
 527/* This virtual clock is the source for dpll3_m3x2_ck */
 528static struct clk dpll3_m3_ck = {
 529	.name		= "dpll3_m3_ck",
 530	.ops		= &clkops_null,
 531	.parent		= &dpll3_ck,
 532	.init		= &omap2_init_clksel_parent,
 533	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 534	.clksel_mask	= OMAP3430_DIV_DPLL3_MASK,
 535	.clksel		= div16_dpll3_clksel,
 536	.clkdm_name	= "dpll3_clkdm",
 537	.recalc		= &omap2_clksel_recalc,
 538};
 539
 540/* The PWRDN bit is apparently only available on 3430ES2 and above */
 541static struct clk dpll3_m3x2_ck = {
 542	.name		= "dpll3_m3x2_ck",
 543	.ops		= &clkops_omap2_dflt_wait,
 544	.parent		= &dpll3_m3_ck,
 545	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 546	.enable_bit	= OMAP3430_PWRDN_EMU_CORE_SHIFT,
 547	.flags		= INVERT_ENABLE,
 548	.clkdm_name	= "dpll3_clkdm",
 549	.recalc		= &omap3_clkoutx2_recalc,
 550};
 551
 552static struct clk emu_core_alwon_ck = {
 553	.name		= "emu_core_alwon_ck",
 554	.ops		= &clkops_null,
 555	.parent		= &dpll3_m3x2_ck,
 556	.clkdm_name	= "dpll3_clkdm",
 557	.recalc		= &followparent_recalc,
 558};
 559
 560/* DPLL4 */
 561/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 562/* Type: DPLL */
 563static struct dpll_data dpll4_dd;
 564
 565static struct dpll_data dpll4_dd_34xx __initdata = {
 566	.mult_div1_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 567	.mult_mask	= OMAP3430_PERIPH_DPLL_MULT_MASK,
 568	.div1_mask	= OMAP3430_PERIPH_DPLL_DIV_MASK,
 569	.clk_bypass	= &sys_ck,
 570	.clk_ref	= &sys_ck,
 571	.freqsel_mask	= OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 572	.control_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 573	.enable_mask	= OMAP3430_EN_PERIPH_DPLL_MASK,
 574	.modes		= (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 575	.auto_recal_bit	= OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 576	.recal_en_bit	= OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 577	.recal_st_bit	= OMAP3430_PERIPH_DPLL_ST_SHIFT,
 578	.autoidle_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 579	.autoidle_mask	= OMAP3430_AUTO_PERIPH_DPLL_MASK,
 580	.idlest_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 581	.idlest_mask	= OMAP3430_ST_PERIPH_CLK_MASK,
 582	.max_multiplier = OMAP3_MAX_DPLL_MULT,
 583	.min_divider	= 1,
 584	.max_divider	= OMAP3_MAX_DPLL_DIV,
 585};
 586
 587static struct dpll_data dpll4_dd_3630 __initdata = {
 588	.mult_div1_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 589	.mult_mask	= OMAP3630_PERIPH_DPLL_MULT_MASK,
 590	.div1_mask	= OMAP3430_PERIPH_DPLL_DIV_MASK,
 591	.clk_bypass	= &sys_ck,
 592	.clk_ref	= &sys_ck,
 593	.control_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 594	.enable_mask	= OMAP3430_EN_PERIPH_DPLL_MASK,
 595	.modes		= (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 596	.auto_recal_bit	= OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 597	.recal_en_bit	= OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 598	.recal_st_bit	= OMAP3430_PERIPH_DPLL_ST_SHIFT,
 599	.autoidle_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 600	.autoidle_mask	= OMAP3430_AUTO_PERIPH_DPLL_MASK,
 601	.idlest_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 602	.idlest_mask	= OMAP3430_ST_PERIPH_CLK_MASK,
 603	.dco_mask	= OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
 604	.sddiv_mask	= OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
 605	.max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
 606	.min_divider	= 1,
 607	.max_divider	= OMAP3_MAX_DPLL_DIV,
 608	.flags		= DPLL_J_TYPE
 609};
 610
 611static struct clk dpll4_ck = {
 612	.name		= "dpll4_ck",
 613	.ops		= &clkops_omap3_noncore_dpll_ops,
 614	.parent		= &sys_ck,
 615	.dpll_data	= &dpll4_dd,
 616	.round_rate	= &omap2_dpll_round_rate,
 617	.set_rate	= &omap3_dpll4_set_rate,
 618	.clkdm_name	= "dpll4_clkdm",
 619	.recalc		= &omap3_dpll_recalc,
 620};
 621
 622/*
 623 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 624 * DPLL isn't bypassed --
 625 * XXX does this serve any downstream clocks?
 626 */
 627static struct clk dpll4_x2_ck = {
 628	.name		= "dpll4_x2_ck",
 629	.ops		= &clkops_null,
 630	.parent		= &dpll4_ck,
 631	.clkdm_name	= "dpll4_clkdm",
 632	.recalc		= &omap3_clkoutx2_recalc,
 633};
 634
 635static const struct clksel dpll4_clksel[] = {
 636	{ .parent = &dpll4_ck, .rates = dpll4_rates },
 637	{ .parent = NULL }
 638};
 639
 640/* This virtual clock is the source for dpll4_m2x2_ck */
 641static struct clk dpll4_m2_ck = {
 642	.name		= "dpll4_m2_ck",
 643	.ops		= &clkops_null,
 644	.parent		= &dpll4_ck,
 645	.init		= &omap2_init_clksel_parent,
 646	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 647	.clksel_mask	= OMAP3630_DIV_96M_MASK,
 648	.clksel		= dpll4_clksel,
 649	.clkdm_name	= "dpll4_clkdm",
 650	.recalc		= &omap2_clksel_recalc,
 651};
 652
 653/* The PWRDN bit is apparently only available on 3430ES2 and above */
 654static struct clk dpll4_m2x2_ck = {
 655	.name		= "dpll4_m2x2_ck",
 656	.ops		= &clkops_omap2_dflt_wait,
 657	.parent		= &dpll4_m2_ck,
 658	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 659	.enable_bit	= OMAP3430_PWRDN_96M_SHIFT,
 660	.flags		= INVERT_ENABLE,
 661	.clkdm_name	= "dpll4_clkdm",
 662	.recalc		= &omap3_clkoutx2_recalc,
 663};
 664
 665/*
 666 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 667 * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 668 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 669 * CM_96K_(F)CLK.
 670 */
 671
 672/* Adding 192MHz Clock node needed by SGX */
 673static struct clk omap_192m_alwon_fck = {
 674	.name		= "omap_192m_alwon_fck",
 675	.ops		= &clkops_null,
 676	.parent		= &dpll4_m2x2_ck,
 677	.recalc		= &followparent_recalc,
 678};
 679
 680static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
 681	{ .div = 1, .val = 1, .flags = RATE_IN_36XX },
 682	{ .div = 2, .val = 2, .flags = RATE_IN_36XX },
 683	{ .div = 0 }
 684};
 685
 686static const struct clksel omap_96m_alwon_fck_clksel[] = {
 687	{ .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
 688	{ .parent = NULL }
 689};
 690
 691static const struct clksel_rate omap_96m_dpll_rates[] = {
 692	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 693	{ .div = 0 }
 694};
 695
 696static const struct clksel_rate omap_96m_sys_rates[] = {
 697	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 698	{ .div = 0 }
 699};
 700
 701static struct clk omap_96m_alwon_fck = {
 702	.name		= "omap_96m_alwon_fck",
 703	.ops		= &clkops_null,
 704	.parent		= &dpll4_m2x2_ck,
 705	.recalc		= &followparent_recalc,
 706};
 707
 708static struct clk omap_96m_alwon_fck_3630 = {
 709	.name		= "omap_96m_alwon_fck",
 710	.parent		= &omap_192m_alwon_fck,
 711	.init		= &omap2_init_clksel_parent,
 712	.ops		= &clkops_null,
 713	.recalc		= &omap2_clksel_recalc,
 714	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 715	.clksel_mask	= OMAP3630_CLKSEL_96M_MASK,
 716	.clksel		= omap_96m_alwon_fck_clksel
 717};
 718
 719static struct clk cm_96m_fck = {
 720	.name		= "cm_96m_fck",
 721	.ops		= &clkops_null,
 722	.parent		= &omap_96m_alwon_fck,
 723	.recalc		= &followparent_recalc,
 724};
 725
 726static const struct clksel omap_96m_fck_clksel[] = {
 727	{ .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 728	{ .parent = &sys_ck,	 .rates = omap_96m_sys_rates },
 729	{ .parent = NULL }
 730};
 731
 732static struct clk omap_96m_fck = {
 733	.name		= "omap_96m_fck",
 734	.ops		= &clkops_null,
 735	.parent		= &sys_ck,
 736	.init		= &omap2_init_clksel_parent,
 737	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 738	.clksel_mask	= OMAP3430_SOURCE_96M_MASK,
 739	.clksel		= omap_96m_fck_clksel,
 740	.recalc		= &omap2_clksel_recalc,
 741};
 742
 743/* This virtual clock is the source for dpll4_m3x2_ck */
 744static struct clk dpll4_m3_ck = {
 745	.name		= "dpll4_m3_ck",
 746	.ops		= &clkops_null,
 747	.parent		= &dpll4_ck,
 748	.init		= &omap2_init_clksel_parent,
 749	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 750	.clksel_mask	= OMAP3630_CLKSEL_TV_MASK,
 751	.clksel		= dpll4_clksel,
 752	.clkdm_name	= "dpll4_clkdm",
 753	.recalc		= &omap2_clksel_recalc,
 754};
 755
 756/* The PWRDN bit is apparently only available on 3430ES2 and above */
 757static struct clk dpll4_m3x2_ck = {
 758	.name		= "dpll4_m3x2_ck",
 759	.ops		= &clkops_omap2_dflt_wait,
 760	.parent		= &dpll4_m3_ck,
 761	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 762	.enable_bit	= OMAP3430_PWRDN_TV_SHIFT,
 763	.flags		= INVERT_ENABLE,
 764	.clkdm_name	= "dpll4_clkdm",
 765	.recalc		= &omap3_clkoutx2_recalc,
 766};
 767
 768static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 769	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 770	{ .div = 0 }
 771};
 772
 773static const struct clksel_rate omap_54m_alt_rates[] = {
 774	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 775	{ .div = 0 }
 776};
 777
 778static const struct clksel omap_54m_clksel[] = {
 779	{ .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
 780	{ .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 781	{ .parent = NULL }
 782};
 783
 784static struct clk omap_54m_fck = {
 785	.name		= "omap_54m_fck",
 786	.ops		= &clkops_null,
 787	.init		= &omap2_init_clksel_parent,
 788	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 789	.clksel_mask	= OMAP3430_SOURCE_54M_MASK,
 790	.clksel		= omap_54m_clksel,
 791	.recalc		= &omap2_clksel_recalc,
 792};
 793
 794static const struct clksel_rate omap_48m_cm96m_rates[] = {
 795	{ .div = 2, .val = 0, .flags = RATE_IN_3XXX },
 796	{ .div = 0 }
 797};
 798
 799static const struct clksel_rate omap_48m_alt_rates[] = {
 800	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 801	{ .div = 0 }
 802};
 803
 804static const struct clksel omap_48m_clksel[] = {
 805	{ .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 806	{ .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 807	{ .parent = NULL }
 808};
 809
 810static struct clk omap_48m_fck = {
 811	.name		= "omap_48m_fck",
 812	.ops		= &clkops_null,
 813	.init		= &omap2_init_clksel_parent,
 814	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 815	.clksel_mask	= OMAP3430_SOURCE_48M_MASK,
 816	.clksel		= omap_48m_clksel,
 817	.recalc		= &omap2_clksel_recalc,
 818};
 819
 820static struct clk omap_12m_fck = {
 821	.name		= "omap_12m_fck",
 822	.ops		= &clkops_null,
 823	.parent		= &omap_48m_fck,
 824	.fixed_div	= 4,
 825	.recalc		= &omap_fixed_divisor_recalc,
 826};
 827
 828/* This virtual clock is the source for dpll4_m4x2_ck */
 829static struct clk dpll4_m4_ck = {
 830	.name		= "dpll4_m4_ck",
 831	.ops		= &clkops_null,
 832	.parent		= &dpll4_ck,
 833	.init		= &omap2_init_clksel_parent,
 834	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 835	.clksel_mask	= OMAP3630_CLKSEL_DSS1_MASK,
 836	.clksel		= dpll4_clksel,
 837	.clkdm_name	= "dpll4_clkdm",
 838	.recalc		= &omap2_clksel_recalc,
 839	.set_rate	= &omap2_clksel_set_rate,
 840	.round_rate	= &omap2_clksel_round_rate,
 841};
 842
 843/* The PWRDN bit is apparently only available on 3430ES2 and above */
 844static struct clk dpll4_m4x2_ck = {
 845	.name		= "dpll4_m4x2_ck",
 846	.ops		= &clkops_omap2_dflt_wait,
 847	.parent		= &dpll4_m4_ck,
 848	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 849	.enable_bit	= OMAP3430_PWRDN_DSS1_SHIFT,
 850	.flags		= INVERT_ENABLE,
 851	.clkdm_name	= "dpll4_clkdm",
 852	.recalc		= &omap3_clkoutx2_recalc,
 853};
 854
 855/* This virtual clock is the source for dpll4_m5x2_ck */
 856static struct clk dpll4_m5_ck = {
 857	.name		= "dpll4_m5_ck",
 858	.ops		= &clkops_null,
 859	.parent		= &dpll4_ck,
 860	.init		= &omap2_init_clksel_parent,
 861	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 862	.clksel_mask	= OMAP3630_CLKSEL_CAM_MASK,
 863	.clksel		= dpll4_clksel,
 864	.clkdm_name	= "dpll4_clkdm",
 865	.set_rate	= &omap2_clksel_set_rate,
 866	.round_rate	= &omap2_clksel_round_rate,
 867	.recalc		= &omap2_clksel_recalc,
 868};
 869
 870/* The PWRDN bit is apparently only available on 3430ES2 and above */
 871static struct clk dpll4_m5x2_ck = {
 872	.name		= "dpll4_m5x2_ck",
 873	.ops		= &clkops_omap2_dflt_wait,
 874	.parent		= &dpll4_m5_ck,
 875	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 876	.enable_bit	= OMAP3430_PWRDN_CAM_SHIFT,
 877	.flags		= INVERT_ENABLE,
 878	.clkdm_name	= "dpll4_clkdm",
 879	.recalc		= &omap3_clkoutx2_recalc,
 880};
 881
 882/* This virtual clock is the source for dpll4_m6x2_ck */
 883static struct clk dpll4_m6_ck = {
 884	.name		= "dpll4_m6_ck",
 885	.ops		= &clkops_null,
 886	.parent		= &dpll4_ck,
 887	.init		= &omap2_init_clksel_parent,
 888	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 889	.clksel_mask	= OMAP3630_DIV_DPLL4_MASK,
 890	.clksel		= dpll4_clksel,
 891	.clkdm_name	= "dpll4_clkdm",
 892	.recalc		= &omap2_clksel_recalc,
 893};
 894
 895/* The PWRDN bit is apparently only available on 3430ES2 and above */
 896static struct clk dpll4_m6x2_ck = {
 897	.name		= "dpll4_m6x2_ck",
 898	.ops		= &clkops_omap2_dflt_wait,
 899	.parent		= &dpll4_m6_ck,
 900	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 901	.enable_bit	= OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 902	.flags		= INVERT_ENABLE,
 903	.clkdm_name	= "dpll4_clkdm",
 904	.recalc		= &omap3_clkoutx2_recalc,
 905};
 906
 907static struct clk emu_per_alwon_ck = {
 908	.name		= "emu_per_alwon_ck",
 909	.ops		= &clkops_null,
 910	.parent		= &dpll4_m6x2_ck,
 911	.clkdm_name	= "dpll4_clkdm",
 912	.recalc		= &followparent_recalc,
 913};
 914
 915/* DPLL5 */
 916/* Supplies 120MHz clock, USIM source clock */
 917/* Type: DPLL */
 918/* 3430ES2 only */
 919static struct dpll_data dpll5_dd = {
 920	.mult_div1_reg	= OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 921	.mult_mask	= OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 922	.div1_mask	= OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 923	.clk_bypass	= &sys_ck,
 924	.clk_ref	= &sys_ck,
 925	.freqsel_mask	= OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 926	.control_reg	= OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 927	.enable_mask	= OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 928	.modes		= (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 929	.auto_recal_bit	= OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 930	.recal_en_bit	= OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 931	.recal_st_bit	= OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 932	.autoidle_reg	= OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 933	.autoidle_mask	= OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 934	.idlest_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 935	.idlest_mask	= OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 936	.max_multiplier = OMAP3_MAX_DPLL_MULT,
 937	.min_divider	= 1,
 938	.max_divider	= OMAP3_MAX_DPLL_DIV,
 939};
 940
 941static struct clk dpll5_ck = {
 942	.name		= "dpll5_ck",
 943	.ops		= &clkops_omap3_noncore_dpll_ops,
 944	.parent		= &sys_ck,
 945	.dpll_data	= &dpll5_dd,
 946	.round_rate	= &omap2_dpll_round_rate,
 947	.set_rate	= &omap3_noncore_dpll_set_rate,
 948	.clkdm_name	= "dpll5_clkdm",
 949	.recalc		= &omap3_dpll_recalc,
 950};
 951
 952static const struct clksel div16_dpll5_clksel[] = {
 953	{ .parent = &dpll5_ck, .rates = div16_dpll_rates },
 954	{ .parent = NULL }
 955};
 956
 957static struct clk dpll5_m2_ck = {
 958	.name		= "dpll5_m2_ck",
 959	.ops		= &clkops_null,
 960	.parent		= &dpll5_ck,
 961	.init		= &omap2_init_clksel_parent,
 962	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 963	.clksel_mask	= OMAP3430ES2_DIV_120M_MASK,
 964	.clksel		= div16_dpll5_clksel,
 965	.clkdm_name	= "dpll5_clkdm",
 966	.recalc		= &omap2_clksel_recalc,
 967};
 968
 969/* CM EXTERNAL CLOCK OUTPUTS */
 970
 971static const struct clksel_rate clkout2_src_core_rates[] = {
 972	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 973	{ .div = 0 }
 974};
 975
 976static const struct clksel_rate clkout2_src_sys_rates[] = {
 977	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 978	{ .div = 0 }
 979};
 980
 981static const struct clksel_rate clkout2_src_96m_rates[] = {
 982	{ .div = 1, .val = 2, .flags = RATE_IN_3XXX },
 983	{ .div = 0 }
 984};
 985
 986static const struct clksel_rate clkout2_src_54m_rates[] = {
 987	{ .div = 1, .val = 3, .flags = RATE_IN_3XXX },
 988	{ .div = 0 }
 989};
 990
 991static const struct clksel clkout2_src_clksel[] = {
 992	{ .parent = &core_ck,		.rates = clkout2_src_core_rates },
 993	{ .parent = &sys_ck,		.rates = clkout2_src_sys_rates },
 994	{ .parent = &cm_96m_fck,	.rates = clkout2_src_96m_rates },
 995	{ .parent = &omap_54m_fck,	.rates = clkout2_src_54m_rates },
 996	{ .parent = NULL }
 997};
 998
 999static struct clk clkout2_src_ck = {
1000	.name		= "clkout2_src_ck",
1001	.ops		= &clkops_omap2_dflt,
1002	.init		= &omap2_init_clksel_parent,
1003	.enable_reg	= OMAP3430_CM_CLKOUT_CTRL,
1004	.enable_bit	= OMAP3430_CLKOUT2_EN_SHIFT,
1005	.clksel_reg	= OMAP3430_CM_CLKOUT_CTRL,
1006	.clksel_mask	= OMAP3430_CLKOUT2SOURCE_MASK,
1007	.clksel		= clkout2_src_clksel,
1008	.clkdm_name	= "core_clkdm",
1009	.recalc		= &omap2_clksel_recalc,
1010};
1011
1012static const struct clksel_rate sys_clkout2_rates[] = {
1013	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1014	{ .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1015	{ .div = 4, .val = 2, .flags = RATE_IN_3XXX },
1016	{ .div = 8, .val = 3, .flags = RATE_IN_3XXX },
1017	{ .div = 16, .val = 4, .flags = RATE_IN_3XXX },
1018	{ .div = 0 },
1019};
1020
1021static const struct clksel sys_clkout2_clksel[] = {
1022	{ .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1023	{ .parent = NULL },
1024};
1025
1026static struct clk sys_clkout2 = {
1027	.name		= "sys_clkout2",
1028	.ops		= &clkops_null,
1029	.init		= &omap2_init_clksel_parent,
1030	.clksel_reg	= OMAP3430_CM_CLKOUT_CTRL,
1031	.clksel_mask	= OMAP3430_CLKOUT2_DIV_MASK,
1032	.clksel		= sys_clkout2_clksel,
1033	.recalc		= &omap2_clksel_recalc,
1034	.round_rate	= &omap2_clksel_round_rate,
1035	.set_rate	= &omap2_clksel_set_rate
1036};
1037
1038/* CM OUTPUT CLOCKS */
1039
1040static struct clk corex2_fck = {
1041	.name		= "corex2_fck",
1042	.ops		= &clkops_null,
1043	.parent		= &dpll3_m2x2_ck,
1044	.recalc		= &followparent_recalc,
1045};
1046
1047/* DPLL power domain clock controls */
1048
1049static const struct clksel_rate div4_rates[] = {
1050	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1051	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1052	{ .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1053	{ .div = 0 }
1054};
1055
1056static const struct clksel div4_core_clksel[] = {
1057	{ .parent = &core_ck, .rates = div4_rates },
1058	{ .parent = NULL }
1059};
1060
1061/*
1062 * REVISIT: Are these in DPLL power domain or CM power domain? docs
1063 * may be inconsistent here?
1064 */
1065static struct clk dpll1_fck = {
1066	.name		= "dpll1_fck",
1067	.ops		= &clkops_null,
1068	.parent		= &core_ck,
1069	.init		= &omap2_init_clksel_parent,
1070	.clksel_reg	= OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1071	.clksel_mask	= OMAP3430_MPU_CLK_SRC_MASK,
1072	.clksel		= div4_core_clksel,
1073	.recalc		= &omap2_clksel_recalc,
1074};
1075
1076static struct clk mpu_ck = {
1077	.name		= "mpu_ck",
1078	.ops		= &clkops_null,
1079	.parent		= &dpll1_x2m2_ck,
1080	.clkdm_name	= "mpu_clkdm",
1081	.recalc		= &followparent_recalc,
1082};
1083
1084/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1085static const struct clksel_rate arm_fck_rates[] = {
1086	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1087	{ .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1088	{ .div = 0 },
1089};
1090
1091static const struct clksel arm_fck_clksel[] = {
1092	{ .parent = &mpu_ck, .rates = arm_fck_rates },
1093	{ .parent = NULL }
1094};
1095
1096static struct clk arm_fck = {
1097	.name		= "arm_fck",
1098	.ops		= &clkops_null,
1099	.parent		= &mpu_ck,
1100	.init		= &omap2_init_clksel_parent,
1101	.clksel_reg	= OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1102	.clksel_mask	= OMAP3430_ST_MPU_CLK_MASK,
1103	.clksel		= arm_fck_clksel,
1104	.clkdm_name	= "mpu_clkdm",
1105	.recalc		= &omap2_clksel_recalc,
1106};
1107
1108/* XXX What about neon_clkdm ? */
1109
1110/*
1111 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1112 * although it is referenced - so this is a guess
1113 */
1114static struct clk emu_mpu_alwon_ck = {
1115	.name		= "emu_mpu_alwon_ck",
1116	.ops		= &clkops_null,
1117	.parent		= &mpu_ck,
1118	.recalc		= &followparent_recalc,
1119};
1120
1121static struct clk dpll2_fck = {
1122	.name		= "dpll2_fck",
1123	.ops		= &clkops_null,
1124	.parent		= &core_ck,
1125	.init		= &omap2_init_clksel_parent,
1126	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1127	.clksel_mask	= OMAP3430_IVA2_CLK_SRC_MASK,
1128	.clksel		= div4_core_clksel,
1129	.recalc		= &omap2_clksel_recalc,
1130};
1131
1132static struct clk iva2_ck = {
1133	.name		= "iva2_ck",
1134	.ops		= &clkops_omap2_dflt_wait,
1135	.parent		= &dpll2_m2_ck,
1136	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1137	.enable_bit	= OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1138	.clkdm_name	= "iva2_clkdm",
1139	.recalc		= &followparent_recalc,
1140};
1141
1142/* Common interface clocks */
1143
1144static const struct clksel div2_core_clksel[] = {
1145	{ .parent = &core_ck, .rates = div2_rates },
1146	{ .parent = NULL }
1147};
1148
1149static struct clk l3_ick = {
1150	.name		= "l3_ick",
1151	.ops		= &clkops_null,
1152	.parent		= &core_ck,
1153	.init		= &omap2_init_clksel_parent,
1154	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1155	.clksel_mask	= OMAP3430_CLKSEL_L3_MASK,
1156	.clksel		= div2_core_clksel,
1157	.clkdm_name	= "core_l3_clkdm",
1158	.recalc		= &omap2_clksel_recalc,
1159};
1160
1161static const struct clksel div2_l3_clksel[] = {
1162	{ .parent = &l3_ick, .rates = div2_rates },
1163	{ .parent = NULL }
1164};
1165
1166static struct clk l4_ick = {
1167	.name		= "l4_ick",
1168	.ops		= &clkops_null,
1169	.parent		= &l3_ick,
1170	.init		= &omap2_init_clksel_parent,
1171	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1172	.clksel_mask	= OMAP3430_CLKSEL_L4_MASK,
1173	.clksel		= div2_l3_clksel,
1174	.clkdm_name	= "core_l4_clkdm",
1175	.recalc		= &omap2_clksel_recalc,
1176
1177};
1178
1179static const struct clksel div2_l4_clksel[] = {
1180	{ .parent = &l4_ick, .rates = div2_rates },
1181	{ .parent = NULL }
1182};
1183
1184static struct clk rm_ick = {
1185	.name		= "rm_ick",
1186	.ops		= &clkops_null,
1187	.parent		= &l4_ick,
1188	.init		= &omap2_init_clksel_parent,
1189	.clksel_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1190	.clksel_mask	= OMAP3430_CLKSEL_RM_MASK,
1191	.clksel		= div2_l4_clksel,
1192	.recalc		= &omap2_clksel_recalc,
1193};
1194
1195/* GFX power domain */
1196
1197/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1198
1199static const struct clksel gfx_l3_clksel[] = {
1200	{ .parent = &l3_ick, .rates = gfx_l3_rates },
1201	{ .parent = NULL }
1202};
1203
1204/*
1205 * Virtual parent clock for gfx_l3_ick and gfx_l3_fck
1206 * This interface clock does not have a CM_AUTOIDLE bit
1207 */
1208static struct clk gfx_l3_ck = {
1209	.name		= "gfx_l3_ck",
1210	.ops		= &clkops_omap2_dflt_wait,
1211	.parent		= &l3_ick,
1212	.enable_reg	= OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1213	.enable_bit	= OMAP_EN_GFX_SHIFT,
1214	.recalc		= &followparent_recalc,
1215};
1216
1217static struct clk gfx_l3_fck = {
1218	.name		= "gfx_l3_fck",
1219	.ops		= &clkops_null,
1220	.parent		= &gfx_l3_ck,
1221	.init		= &omap2_init_clksel_parent,
1222	.clksel_reg	= OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1223	.clksel_mask	= OMAP_CLKSEL_GFX_MASK,
1224	.clksel		= gfx_l3_clksel,
1225	.clkdm_name	= "gfx_3430es1_clkdm",
1226	.recalc		= &omap2_clksel_recalc,
1227};
1228
1229static struct clk gfx_l3_ick = {
1230	.name		= "gfx_l3_ick",
1231	.ops		= &clkops_null,
1232	.parent		= &gfx_l3_ck,
1233	.clkdm_name	= "gfx_3430es1_clkdm",
1234	.recalc		= &followparent_recalc,
1235};
1236
1237static struct clk gfx_cg1_ck = {
1238	.name		= "gfx_cg1_ck",
1239	.ops		= &clkops_omap2_dflt_wait,
1240	.parent		= &gfx_l3_fck, /* REVISIT: correct? */
1241	.enable_reg	= OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1242	.enable_bit	= OMAP3430ES1_EN_2D_SHIFT,
1243	.clkdm_name	= "gfx_3430es1_clkdm",
1244	.recalc		= &followparent_recalc,
1245};
1246
1247static struct clk gfx_cg2_ck = {
1248	.name		= "gfx_cg2_ck",
1249	.ops		= &clkops_omap2_dflt_wait,
1250	.parent		= &gfx_l3_fck, /* REVISIT: correct? */
1251	.enable_reg	= OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1252	.enable_bit	= OMAP3430ES1_EN_3D_SHIFT,
1253	.clkdm_name	= "gfx_3430es1_clkdm",
1254	.recalc		= &followparent_recalc,
1255};
1256
1257/* SGX power domain - 3430ES2 only */
1258
1259static const struct clksel_rate sgx_core_rates[] = {
1260	{ .div = 2, .val = 5, .flags = RATE_IN_36XX },
1261	{ .div = 3, .val = 0, .flags = RATE_IN_3XXX },
1262	{ .div = 4, .val = 1, .flags = RATE_IN_3XXX },
1263	{ .div = 6, .val = 2, .flags = RATE_IN_3XXX },
1264	{ .div = 0 },
1265};
1266
1267static const struct clksel_rate sgx_192m_rates[] = {
1268	{ .div = 1,  .val = 4, .flags = RATE_IN_36XX },
1269	{ .div = 0 },
1270};
1271
1272static const struct clksel_rate sgx_corex2_rates[] = {
1273	{ .div = 3, .val = 6, .flags = RATE_IN_36XX },
1274	{ .div = 5, .val = 7, .flags = RATE_IN_36XX },
1275	{ .div = 0 },
1276};
1277
1278static const struct clksel_rate sgx_96m_rates[] = {
1279	{ .div = 1,  .val = 3, .flags = RATE_IN_3XXX },
1280	{ .div = 0 },
1281};
1282
1283static const struct clksel sgx_clksel[] = {
1284	{ .parent = &core_ck,	 .rates = sgx_core_rates },
1285	{ .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1286	{ .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
1287	{ .parent = &corex2_fck, .rates = sgx_corex2_rates },
1288	{ .parent = NULL }
1289};
1290
1291static struct clk sgx_fck = {
1292	.name		= "sgx_fck",
1293	.ops		= &clkops_omap2_dflt_wait,
1294	.init		= &omap2_init_clksel_parent,
1295	.enable_reg	= OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1296	.enable_bit	= OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1297	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1298	.clksel_mask	= OMAP3430ES2_CLKSEL_SGX_MASK,
1299	.clksel		= sgx_clksel,
1300	.clkdm_name	= "sgx_clkdm",
1301	.recalc		= &omap2_clksel_recalc,
1302	.set_rate	= &omap2_clksel_set_rate,
1303	.round_rate	= &omap2_clksel_round_rate
1304};
1305
1306/* This interface clock does not have a CM_AUTOIDLE bit */
1307static struct clk sgx_ick = {
1308	.name		= "sgx_ick",
1309	.ops		= &clkops_omap2_dflt_wait,
1310	.parent		= &l3_ick,
1311	.enable_reg	= OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1312	.enable_bit	= OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1313	.clkdm_name	= "sgx_clkdm",
1314	.recalc		= &followparent_recalc,
1315};
1316
1317/* CORE power domain */
1318
1319static struct clk d2d_26m_fck = {
1320	.name		= "d2d_26m_fck",
1321	.ops		= &clkops_omap2_dflt_wait,
1322	.parent		= &sys_ck,
1323	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1324	.enable_bit	= OMAP3430ES1_EN_D2D_SHIFT,
1325	.clkdm_name	= "d2d_clkdm",
1326	.recalc		= &followparent_recalc,
1327};
1328
1329static struct clk modem_fck = {
1330	.name		= "modem_fck",
1331	.ops		= &clkops_omap2_mdmclk_dflt_wait,
1332	.parent		= &sys_ck,
1333	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1334	.enable_bit	= OMAP3430_EN_MODEM_SHIFT,
1335	.clkdm_name	= "d2d_clkdm",
1336	.recalc		= &followparent_recalc,
1337};
1338
1339static struct clk sad2d_ick = {
1340	.name		= "sad2d_ick",
1341	.ops		= &clkops_omap2_iclk_dflt_wait,
1342	.parent		= &l3_ick,
1343	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1344	.enable_bit	= OMAP3430_EN_SAD2D_SHIFT,
1345	.clkdm_name	= "d2d_clkdm",
1346	.recalc		= &followparent_recalc,
1347};
1348
1349static struct clk mad2d_ick = {
1350	.name		= "mad2d_ick",
1351	.ops		= &clkops_omap2_iclk_dflt_wait,
1352	.parent		= &l3_ick,
1353	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1354	.enable_bit	= OMAP3430_EN_MAD2D_SHIFT,
1355	.clkdm_name	= "d2d_clkdm",
1356	.recalc		= &followparent_recalc,
1357};
1358
1359static const struct clksel omap343x_gpt_clksel[] = {
1360	{ .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1361	{ .parent = &sys_ck,	   .rates = gpt_sys_rates },
1362	{ .parent = NULL}
1363};
1364
1365static struct clk gpt10_fck = {
1366	.name		= "gpt10_fck",
1367	.ops		= &clkops_omap2_dflt_wait,
1368	.parent		= &sys_ck,
1369	.init		= &omap2_init_clksel_parent,
1370	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1371	.enable_bit	= OMAP3430_EN_GPT10_SHIFT,
1372	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1373	.clksel_mask	= OMAP3430_CLKSEL_GPT10_MASK,
1374	.clksel		= omap343x_gpt_clksel,
1375	.clkdm_name	= "core_l4_clkdm",
1376	.recalc		= &omap2_clksel_recalc,
1377};
1378
1379static struct clk gpt11_fck = {
1380	.name		= "gpt11_fck",
1381	.ops		= &clkops_omap2_dflt_wait,
1382	.parent		= &sys_ck,
1383	.init		= &omap2_init_clksel_parent,
1384	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1385	.enable_bit	= OMAP3430_EN_GPT11_SHIFT,
1386	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1387	.clksel_mask	= OMAP3430_CLKSEL_GPT11_MASK,
1388	.clksel		= omap343x_gpt_clksel,
1389	.clkdm_name	= "core_l4_clkdm",
1390	.recalc		= &omap2_clksel_recalc,
1391};
1392
1393static struct clk cpefuse_fck = {
1394	.name		= "cpefuse_fck",
1395	.ops		= &clkops_omap2_dflt,
1396	.parent		= &sys_ck,
1397	.clkdm_name	= "core_l4_clkdm",
1398	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1399	.enable_bit	= OMAP3430ES2_EN_CPEFUSE_SHIFT,
1400	.recalc		= &followparent_recalc,
1401};
1402
1403static struct clk ts_fck = {
1404	.name		= "ts_fck",
1405	.ops		= &clkops_omap2_dflt,
1406	.parent		= &omap_32k_fck,
1407	.clkdm_name	= "core_l4_clkdm",
1408	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1409	.enable_bit	= OMAP3430ES2_EN_TS_SHIFT,
1410	.recalc		= &followparent_recalc,
1411};
1412
1413static struct clk usbtll_fck = {
1414	.name		= "usbtll_fck",
1415	.ops		= &clkops_omap2_dflt_wait,
1416	.parent		= &dpll5_m2_ck,
1417	.clkdm_name	= "core_l4_clkdm",
1418	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1419	.enable_bit	= OMAP3430ES2_EN_USBTLL_SHIFT,
1420	.recalc		= &followparent_recalc,
1421};
1422
1423/* CORE 96M FCLK-derived clocks */
1424
1425static struct clk core_96m_fck = {
1426	.name		= "core_96m_fck",
1427	.ops		= &clkops_null,
1428	.parent		= &omap_96m_fck,
1429	.clkdm_name	= "core_l4_clkdm",
1430	.recalc		= &followparent_recalc,
1431};
1432
1433static struct clk mmchs3_fck = {
1434	.name		= "mmchs3_fck",
1435	.ops		= &clkops_omap2_dflt_wait,
1436	.parent		= &core_96m_fck,
1437	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1438	.enable_bit	= OMAP3430ES2_EN_MMC3_SHIFT,
1439	.clkdm_name	= "core_l4_clkdm",
1440	.recalc		= &followparent_recalc,
1441};
1442
1443static struct clk mmchs2_fck = {
1444	.name		= "mmchs2_fck",
1445	.ops		= &clkops_omap2_dflt_wait,
1446	.parent		= &core_96m_fck,
1447	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1448	.enable_bit	= OMAP3430_EN_MMC2_SHIFT,
1449	.clkdm_name	= "core_l4_clkdm",
1450	.recalc		= &followparent_recalc,
1451};
1452
1453static struct clk mspro_fck = {
1454	.name		= "mspro_fck",
1455	.ops		= &clkops_omap2_dflt_wait,
1456	.parent		= &core_96m_fck,
1457	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1458	.enable_bit	= OMAP3430_EN_MSPRO_SHIFT,
1459	.clkdm_name	= "core_l4_clkdm",
1460	.recalc		= &followparent_recalc,
1461};
1462
1463static struct clk mmchs1_fck = {
1464	.name		= "mmchs1_fck",
1465	.ops		= &clkops_omap2_dflt_wait,
1466	.parent		= &core_96m_fck,
1467	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1468	.enable_bit	= OMAP3430_EN_MMC1_SHIFT,
1469	.clkdm_name	= "core_l4_clkdm",
1470	.recalc		= &followparent_recalc,
1471};
1472
1473static struct clk i2c3_fck = {
1474	.name		= "i2c3_fck",
1475	.ops		= &clkops_omap2_dflt_wait,
1476	.parent		= &core_96m_fck,
1477	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1478	.enable_bit	= OMAP3430_EN_I2C3_SHIFT,
1479	.clkdm_name	= "core_l4_clkdm",
1480	.recalc		= &followparent_recalc,
1481};
1482
1483static struct clk i2c2_fck = {
1484	.name		= "i2c2_fck",
1485	.ops		= &clkops_omap2_dflt_wait,
1486	.parent		= &core_96m_fck,
1487	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1488	.enable_bit	= OMAP3430_EN_I2C2_SHIFT,
1489	.clkdm_name	= "core_l4_clkdm",
1490	.recalc		= &followparent_recalc,
1491};
1492
1493static struct clk i2c1_fck = {
1494	.name		= "i2c1_fck",
1495	.ops		= &clkops_omap2_dflt_wait,
1496	.parent		= &core_96m_fck,
1497	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1498	.enable_bit	= OMAP3430_EN_I2C1_SHIFT,
1499	.clkdm_name	= "core_l4_clkdm",
1500	.recalc		= &followparent_recalc,
1501};
1502
1503/*
1504 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1505 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1506 */
1507static const struct clksel_rate common_mcbsp_96m_rates[] = {
1508	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1509	{ .div = 0 }
1510};
1511
1512static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1513	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1514	{ .div = 0 }
1515};
1516
1517static const struct clksel mcbsp_15_clksel[] = {
1518	{ .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1519	{ .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1520	{ .parent = NULL }
1521};
1522
1523static struct clk mcbsp5_fck = {
1524	.name		= "mcbsp5_fck",
1525	.ops		= &clkops_omap2_dflt_wait,
1526	.init		= &omap2_init_clksel_parent,
1527	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1528	.enable_bit	= OMAP3430_EN_MCBSP5_SHIFT,
1529	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1530	.clksel_mask	= OMAP2_MCBSP5_CLKS_MASK,
1531	.clksel		= mcbsp_15_clksel,
1532	.clkdm_name	= "core_l4_clkdm",
1533	.recalc		= &omap2_clksel_recalc,
1534};
1535
1536static struct clk mcbsp1_fck = {
1537	.name		= "mcbsp1_fck",
1538	.ops		= &clkops_omap2_dflt_wait,
1539	.init		= &omap2_init_clksel_parent,
1540	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1541	.enable_bit	= OMAP3430_EN_MCBSP1_SHIFT,
1542	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1543	.clksel_mask	= OMAP2_MCBSP1_CLKS_MASK,
1544	.clksel		= mcbsp_15_clksel,
1545	.clkdm_name	= "core_l4_clkdm",
1546	.recalc		= &omap2_clksel_recalc,
1547};
1548
1549/* CORE_48M_FCK-derived clocks */
1550
1551static struct clk core_48m_fck = {
1552	.name		= "core_48m_fck",
1553	.ops		= &clkops_null,
1554	.parent		= &omap_48m_fck,
1555	.clkdm_name	= "core_l4_clkdm",
1556	.recalc		= &followparent_recalc,
1557};
1558
1559static struct clk mcspi4_fck = {
1560	.name		= "mcspi4_fck",
1561	.ops		= &clkops_omap2_dflt_wait,
1562	.parent		= &core_48m_fck,
1563	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1564	.enable_bit	= OMAP3430_EN_MCSPI4_SHIFT,
1565	.recalc		= &followparent_recalc,
1566	.clkdm_name	= "core_l4_clkdm",
1567};
1568
1569static struct clk mcspi3_fck = {
1570	.name		= "mcspi3_fck",
1571	.ops		= &clkops_omap2_dflt_wait,
1572	.parent		= &core_48m_fck,
1573	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1574	.enable_bit	= OMAP3430_EN_MCSPI3_SHIFT,
1575	.recalc		= &followparent_recalc,
1576	.clkdm_name	= "core_l4_clkdm",
1577};
1578
1579static struct clk mcspi2_fck = {
1580	.name		= "mcspi2_fck",
1581	.ops		= &clkops_omap2_dflt_wait,
1582	.parent		= &core_48m_fck,
1583	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1584	.enable_bit	= OMAP3430_EN_MCSPI2_SHIFT,
1585	.recalc		= &followparent_recalc,
1586	.clkdm_name	= "core_l4_clkdm",
1587};
1588
1589static struct clk mcspi1_fck = {
1590	.name		= "mcspi1_fck",
1591	.ops		= &clkops_omap2_dflt_wait,
1592	.parent		= &core_48m_fck,
1593	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1594	.enable_bit	= OMAP3430_EN_MCSPI1_SHIFT,
1595	.recalc		= &followparent_recalc,
1596	.clkdm_name	= "core_l4_clkdm",
1597};
1598
1599static struct clk uart2_fck = {
1600	.name		= "uart2_fck",
1601	.ops		= &clkops_omap2_dflt_wait,
1602	.parent		= &core_48m_fck,
1603	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1604	.enable_bit	= OMAP3430_EN_UART2_SHIFT,
1605	.clkdm_name	= "core_l4_clkdm",
1606	.recalc		= &followparent_recalc,
1607};
1608
1609static struct clk uart1_fck = {
1610	.name		= "uart1_fck",
1611	.ops		= &clkops_omap2_dflt_wait,
1612	.parent		= &core_48m_fck,
1613	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1614	.enable_bit	= OMAP3430_EN_UART1_SHIFT,
1615	.clkdm_name	= "core_l4_clkdm",
1616	.recalc		= &followparent_recalc,
1617};
1618
1619static struct clk fshostusb_fck = {
1620	.name		= "fshostusb_fck",
1621	.ops		= &clkops_omap2_dflt_wait,
1622	.parent		= &core_48m_fck,
1623	.clkdm_name	= "core_l4_clkdm",
1624	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1625	.enable_bit	= OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1626	.recalc		= &followparent_recalc,
1627};
1628
1629/* CORE_12M_FCK based clocks */
1630
1631static struct clk core_12m_fck = {
1632	.name		= "core_12m_fck",
1633	.ops		= &clkops_null,
1634	.parent		= &omap_12m_fck,
1635	.clkdm_name	= "core_l4_clkdm",
1636	.recalc		= &followparent_recalc,
1637};
1638
1639static struct clk hdq_fck = {
1640	.name		= "hdq_fck",
1641	.ops		= &clkops_omap2_dflt_wait,
1642	.parent		= &core_12m_fck,
1643	.clkdm_name	= "core_l4_clkdm",
1644	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1645	.enable_bit	= OMAP3430_EN_HDQ_SHIFT,
1646	.recalc		= &followparent_recalc,
1647};
1648
1649/* DPLL3-derived clock */
1650
1651static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1652	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1653	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1654	{ .div = 3, .val = 3, .flags = RATE_IN_3XXX },
1655	{ .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1656	{ .div = 6, .val = 6, .flags = RATE_IN_3XXX },
1657	{ .div = 8, .val = 8, .flags = RATE_IN_3XXX },
1658	{ .div = 0 }
1659};
1660
1661static const struct clksel ssi_ssr_clksel[] = {
1662	{ .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1663	{ .parent = NULL }
1664};
1665
1666static struct clk ssi_ssr_fck_3430es1 = {
1667	.name		= "ssi_ssr_fck",
1668	.ops		= &clkops_omap2_dflt,
1669	.init		= &omap2_init_clksel_parent,
1670	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1671	.enable_bit	= OMAP3430_EN_SSI_SHIFT,
1672	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1673	.clksel_mask	= OMAP3430_CLKSEL_SSI_MASK,
1674	.clksel		= ssi_ssr_clksel,
1675	.clkdm_name	= "core_l4_clkdm",
1676	.recalc		= &omap2_clksel_recalc,
1677};
1678
1679static struct clk ssi_ssr_fck_3430es2 = {
1680	.name		= "ssi_ssr_fck",
1681	.ops		= &clkops_omap3430es2_ssi_wait,
1682	.init		= &omap2_init_clksel_parent,
1683	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1684	.enable_bit	= OMAP3430_EN_SSI_SHIFT,
1685	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1686	.clksel_mask	= OMAP3430_CLKSEL_SSI_MASK,
1687	.clksel		= ssi_ssr_clksel,
1688	.clkdm_name	= "core_l4_clkdm",
1689	.recalc		= &omap2_clksel_recalc,
1690};
1691
1692static struct clk ssi_sst_fck_3430es1 = {
1693	.name		= "ssi_sst_fck",
1694	.ops		= &clkops_null,
1695	.parent		= &ssi_ssr_fck_3430es1,
1696	.fixed_div	= 2,
1697	.recalc		= &omap_fixed_divisor_recalc,
1698};
1699
1700static struct clk ssi_sst_fck_3430es2 = {
1701	.name		= "ssi_sst_fck",
1702	.ops		= &clkops_null,
1703	.parent		= &ssi_ssr_fck_3430es2,
1704	.fixed_div	= 2,
1705	.recalc		= &omap_fixed_divisor_recalc,
1706};
1707
1708
1709
1710/* CORE_L3_ICK based clocks */
1711
1712/*
1713 * XXX must add clk_enable/clk_disable for these if standard code won't
1714 * handle it
1715 */
1716static struct clk core_l3_ick = {
1717	.name		= "core_l3_ick",
1718	.ops		= &clkops_null,
1719	.parent		= &l3_ick,
1720	.clkdm_name	= "core_l3_clkdm",
1721	.recalc		= &followparent_recalc,
1722};
1723
1724static struct clk hsotgusb_ick_3430es1 = {
1725	.name		= "hsotgusb_ick",
1726	.ops		= &clkops_omap2_iclk_dflt,
1727	.parent		= &core_l3_ick,
1728	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1729	.enable_bit	= OMAP3430_EN_HSOTGUSB_SHIFT,
1730	.clkdm_name	= "core_l3_clkdm",
1731	.recalc		= &followparent_recalc,
1732};
1733
1734static struct clk hsotgusb_ick_3430es2 = {
1735	.name		= "hsotgusb_ick",
1736	.ops		= &clkops_omap3430es2_iclk_hsotgusb_wait,
1737	.parent		= &core_l3_ick,
1738	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1739	.enable_bit	= OMAP3430_EN_HSOTGUSB_SHIFT,
1740	.clkdm_name	= "core_l3_clkdm",
1741	.recalc		= &followparent_recalc,
1742};
1743
1744/* This interface clock does not have a CM_AUTOIDLE bit */
1745static struct clk sdrc_ick = {
1746	.name		= "sdrc_ick",
1747	.ops		= &clkops_omap2_dflt_wait,
1748	.parent		= &core_l3_ick,
1749	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1750	.enable_bit	= OMAP3430_EN_SDRC_SHIFT,
1751	.flags		= ENABLE_ON_INIT,
1752	.clkdm_name	= "core_l3_clkdm",
1753	.recalc		= &followparent_recalc,
1754};
1755
1756static struct clk gpmc_fck = {
1757	.name		= "gpmc_fck",
1758	.ops		= &clkops_null,
1759	.parent		= &core_l3_ick,
1760	.flags		= ENABLE_ON_INIT, /* huh? */
1761	.clkdm_name	= "core_l3_clkdm",
1762	.recalc		= &followparent_recalc,
1763};
1764
1765/* SECURITY_L3_ICK based clocks */
1766
1767static struct clk security_l3_ick = {
1768	.name		= "security_l3_ick",
1769	.ops		= &clkops_null,
1770	.parent		= &l3_ick,
1771	.recalc		= &followparent_recalc,
1772};
1773
1774static struct clk pka_ick = {
1775	.name		= "pka_ick",
1776	.ops		= &clkops_omap2_iclk_dflt_wait,
1777	.parent		= &security_l3_ick,
1778	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1779	.enable_bit	= OMAP3430_EN_PKA_SHIFT,
1780	.recalc		= &followparent_recalc,
1781};
1782
1783/* CORE_L4_ICK based clocks */
1784
1785static struct clk core_l4_ick = {
1786	.name		= "core_l4_ick",
1787	.ops		= &clkops_null,
1788	.parent		= &l4_ick,
1789	.clkdm_name	= "core_l4_clkdm",
1790	.recalc		= &followparent_recalc,
1791};
1792
1793static struct clk usbtll_ick = {
1794	.name		= "usbtll_ick",
1795	.ops		= &clkops_omap2_iclk_dflt_wait,
1796	.parent		= &core_l4_ick,
1797	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1798	.enable_bit	= OMAP3430ES2_EN_USBTLL_SHIFT,
1799	.clkdm_name	= "core_l4_clkdm",
1800	.recalc		= &followparent_recalc,
1801};
1802
1803static struct clk mmchs3_ick = {
1804	.name		= "mmchs3_ick",
1805	.ops		= &clkops_omap2_iclk_dflt_wait,
1806	.parent		= &core_l4_ick,
1807	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1808	.enable_bit	= OMAP3430ES2_EN_MMC3_SHIFT,
1809	.clkdm_name	= "core_l4_clkdm",
1810	.recalc		= &followparent_recalc,
1811};
1812
1813/* Intersystem Communication Registers - chassis mode only */
1814static struct clk icr_ick = {
1815	.name		= "icr_ick",
1816	.ops		= &clkops_omap2_iclk_dflt_wait,
1817	.parent		= &core_l4_ick,
1818	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1819	.enable_bit	= OMAP3430_EN_ICR_SHIFT,
1820	.clkdm_name	= "core_l4_clkdm",
1821	.recalc		= &followparent_recalc,
1822};
1823
1824static struct clk aes2_ick = {
1825	.name		= "aes2_ick",
1826	.ops		= &clkops_omap2_iclk_dflt_wait,
1827	.parent		= &core_l4_ick,
1828	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1829	.enable_bit	= OMAP3430_EN_AES2_SHIFT,
1830	.clkdm_name	= "core_l4_clkdm",
1831	.recalc		= &followparent_recalc,
1832};
1833
1834static struct clk sha12_ick = {
1835	.name		= "sha12_ick",
1836	.ops		= &clkops_omap2_iclk_dflt_wait,
1837	.parent		= &core_l4_ick,
1838	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1839	.enable_bit	= OMAP3430_EN_SHA12_SHIFT,
1840	.clkdm_name	= "core_l4_clkdm",
1841	.recalc		= &followparent_recalc,
1842};
1843
1844static struct clk des2_ick = {
1845	.name		= "des2_ick",
1846	.ops		= &clkops_omap2_iclk_dflt_wait,
1847	.parent		= &core_l4_ick,
1848	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1849	.enable_bit	= OMAP3430_EN_DES2_SHIFT,
1850	.clkdm_name	= "core_l4_clkdm",
1851	.recalc		= &followparent_recalc,
1852};
1853
1854static struct clk mmchs2_ick = {
1855	.name		= "mmchs2_ick",
1856	.ops		= &clkops_omap2_iclk_dflt_wait,
1857	.parent		= &core_l4_ick,
1858	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1859	.enable_bit	= OMAP3430_EN_MMC2_SHIFT,
1860	.clkdm_name	= "core_l4_clkdm",
1861	.recalc		= &followparent_recalc,
1862};
1863
1864static struct clk mmchs1_ick = {
1865	.name		= "mmchs1_ick",
1866	.ops		= &clkops_omap2_iclk_dflt_wait,
1867	.parent		= &core_l4_ick,
1868	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1869	.enable_bit	= OMAP3430_EN_MMC1_SHIFT,
1870	.clkdm_name	= "core_l4_clkdm",
1871	.recalc		= &followparent_recalc,
1872};
1873
1874static struct clk mspro_ick = {
1875	.name		= "mspro_ick",
1876	.ops		= &clkops_omap2_iclk_dflt_wait,
1877	.parent		= &core_l4_ick,
1878	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1879	.enable_bit	= OMAP3430_EN_MSPRO_SHIFT,
1880	.clkdm_name	= "core_l4_clkdm",
1881	.recalc		= &followparent_recalc,
1882};
1883
1884static struct clk hdq_ick = {
1885	.name		= "hdq_ick",
1886	.ops		= &clkops_omap2_iclk_dflt_wait,
1887	.parent		= &core_l4_ick,
1888	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1889	.enable_bit	= OMAP3430_EN_HDQ_SHIFT,
1890	.clkdm_name	= "core_l4_clkdm",
1891	.recalc		= &followparent_recalc,
1892};
1893
1894static struct clk mcspi4_ick = {
1895	.name		= "mcspi4_ick",
1896	.ops		= &clkops_omap2_iclk_dflt_wait,
1897	.parent		= &core_l4_ick,
1898	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1899	.enable_bit	= OMAP3430_EN_MCSPI4_SHIFT,
1900	.clkdm_name	= "core_l4_clkdm",
1901	.recalc		= &followparent_recalc,
1902};
1903
1904static struct clk mcspi3_ick = {
1905	.name		= "mcspi3_ick",
1906	.ops		= &clkops_omap2_iclk_dflt_wait,
1907	.parent		= &core_l4_ick,
1908	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1909	.enable_bit	= OMAP3430_EN_MCSPI3_SHIFT,
1910	.clkdm_name	= "core_l4_clkdm",
1911	.recalc		= &followparent_recalc,
1912};
1913
1914static struct clk mcspi2_ick = {
1915	.name		= "mcspi2_ick",
1916	.ops		= &clkops_omap2_iclk_dflt_wait,
1917	.parent		= &core_l4_ick,
1918	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1919	.enable_bit	= OMAP3430_EN_MCSPI2_SHIFT,
1920	.clkdm_name	= "core_l4_clkdm",
1921	.recalc		= &followparent_recalc,
1922};
1923
1924static struct clk mcspi1_ick = {
1925	.name		= "mcspi1_ick",
1926	.ops		= &clkops_omap2_iclk_dflt_wait,
1927	.parent		= &core_l4_ick,
1928	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1929	.enable_bit	= OMAP3430_EN_MCSPI1_SHIFT,
1930	.clkdm_name	= "core_l4_clkdm",
1931	.recalc		= &followparent_recalc,
1932};
1933
1934static struct clk i2c3_ick = {
1935	.name		= "i2c3_ick",
1936	.ops		= &clkops_omap2_iclk_dflt_wait,
1937	.parent		= &core_l4_ick,
1938	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1939	.enable_bit	= OMAP3430_EN_I2C3_SHIFT,
1940	.clkdm_name	= "core_l4_clkdm",
1941	.recalc		= &followparent_recalc,
1942};
1943
1944static struct clk i2c2_ick = {
1945	.name		= "i2c2_ick",
1946	.ops		= &clkops_omap2_iclk_dflt_wait,
1947	.parent		= &core_l4_ick,
1948	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1949	.enable_bit	= OMAP3430_EN_I2C2_SHIFT,
1950	.clkdm_name	= "core_l4_clkdm",
1951	.recalc		= &followparent_recalc,
1952};
1953
1954static struct clk i2c1_ick = {
1955	.name		= "i2c1_ick",
1956	.ops		= &clkops_omap2_iclk_dflt_wait,
1957	.parent		= &core_l4_ick,
1958	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1959	.enable_bit	= OMAP3430_EN_I2C1_SHIFT,
1960	.clkdm_name	= "core_l4_clkdm",
1961	.recalc		= &followparent_recalc,
1962};
1963
1964static struct clk uart2_ick = {
1965	.name		= "uart2_ick",
1966	.ops		= &clkops_omap2_iclk_dflt_wait,
1967	.parent		= &core_l4_ick,
1968	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1969	.enable_bit	= OMAP3430_EN_UART2_SHIFT,
1970	.clkdm_name	= "core_l4_clkdm",
1971	.recalc		= &followparent_recalc,
1972};
1973
1974static struct clk uart1_ick = {
1975	.name		= "uart1_ick",
1976	.ops		= &clkops_omap2_iclk_dflt_wait,
1977	.parent		= &core_l4_ick,
1978	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1979	.enable_bit	= OMAP3430_EN_UART1_SHIFT,
1980	.clkdm_name	= "core_l4_clkdm",
1981	.recalc		= &followparent_recalc,
1982};
1983
1984static struct clk gpt11_ick = {
1985	.name		= "gpt11_ick",
1986	.ops		= &clkops_omap2_iclk_dflt_wait,
1987	.parent		= &core_l4_ick,
1988	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1989	.enable_bit	= OMAP3430_EN_GPT11_SHIFT,
1990	.clkdm_name	= "core_l4_clkdm",
1991	.recalc		= &followparent_recalc,
1992};
1993
1994static struct clk gpt10_ick = {
1995	.name		= "gpt10_ick",
1996	.ops		= &clkops_omap2_iclk_dflt_wait,
1997	.parent		= &core_l4_ick,
1998	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1999	.enable_bit	= OMAP3430_EN_GPT10_SHIFT,
2000	.clkdm_name	= "core_l4_clkdm",
2001	.recalc		= &followparent_recalc,
2002};
2003
2004static struct clk mcbsp5_ick = {
2005	.name		= "mcbsp5_ick",
2006	.ops		= &clkops_omap2_iclk_dflt_wait,
2007	.parent		= &core_l4_ick,
2008	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2009	.enable_bit	= OMAP3430_EN_MCBSP5_SHIFT,
2010	.clkdm_name	= "core_l4_clkdm",
2011	.recalc		= &followparent_recalc,
2012};
2013
2014static struct clk mcbsp1_ick = {
2015	.name		= "mcbsp1_ick",
2016	.ops		= &clkops_omap2_iclk_dflt_wait,
2017	.parent		= &core_l4_ick,
2018	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2019	.enable_bit	= OMAP3430_EN_MCBSP1_SHIFT,
2020	.clkdm_name	= "core_l4_clkdm",
2021	.recalc		= &followparent_recalc,
2022};
2023
2024static struct clk fac_ick = {
2025	.name		= "fac_ick",
2026	.ops		= &clkops_omap2_iclk_dflt_wait,
2027	.parent		= &core_l4_ick,
2028	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2029	.enable_bit	= OMAP3430ES1_EN_FAC_SHIFT,
2030	.clkdm_name	= "core_l4_clkdm",
2031	.recalc		= &followparent_recalc,
2032};
2033
2034static struct clk mailboxes_ick = {
2035	.name		= "mailboxes_ick",
2036	.ops		= &clkops_omap2_iclk_dflt_wait,
2037	.parent		= &core_l4_ick,
2038	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2039	.enable_bit	= OMAP3430_EN_MAILBOXES_SHIFT,
2040	.clkdm_name	= "core_l4_clkdm",
2041	.recalc		= &followparent_recalc,
2042};
2043
2044static struct clk omapctrl_ick = {
2045	.name		= "omapctrl_ick",
2046	.ops		= &clkops_omap2_iclk_dflt_wait,
2047	.parent		= &core_l4_ick,
2048	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2049	.enable_bit	= OMAP3430_EN_OMAPCTRL_SHIFT,
2050	.flags		= ENABLE_ON_INIT,
2051	.clkdm_name	= "core_l4_clkdm",
2052	.recalc		= &followparent_recalc,
2053};
2054
2055/* SSI_L4_ICK based clocks */
2056
2057static struct clk ssi_l4_ick = {
2058	.name		= "ssi_l4_ick",
2059	.ops		= &clkops_null,
2060	.parent		= &l4_ick,
2061	.clkdm_name	= "core_l4_clkdm",
2062	.recalc		= &followparent_recalc,
2063};
2064
2065static struct clk ssi_ick_3430es1 = {
2066	.name		= "ssi_ick",
2067	.ops		= &clkops_omap2_iclk_dflt,
2068	.parent		= &ssi_l4_ick,
2069	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2070	.enable_bit	= OMAP3430_EN_SSI_SHIFT,
2071	.clkdm_name	= "core_l4_clkdm",
2072	.recalc		= &followparent_recalc,
2073};
2074
2075static struct clk ssi_ick_3430es2 = {
2076	.name		= "ssi_ick",
2077	.ops		= &clkops_omap3430es2_iclk_ssi_wait,
2078	.parent		= &ssi_l4_ick,
2079	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2080	.enable_bit	= OMAP3430_EN_SSI_SHIFT,
2081	.clkdm_name	= "core_l4_clkdm",
2082	.recalc		= &followparent_recalc,
2083};
2084
2085/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2086 * but l4_ick makes more sense to me */
2087
2088static const struct clksel usb_l4_clksel[] = {
2089	{ .parent = &l4_ick, .rates = div2_rates },
2090	{ .parent = NULL },
2091};
2092
2093static struct clk usb_l4_ick = {
2094	.name		= "usb_l4_ick",
2095	.ops		= &clkops_omap2_iclk_dflt_wait,
2096	.parent		= &l4_ick,
2097	.init		= &omap2_init_clksel_parent,
2098	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2099	.enable_bit	= OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2100	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2101	.clksel_mask	= OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2102	.clksel		= usb_l4_clksel,
2103	.clkdm_name	= "core_l4_clkdm",
2104	.recalc		= &omap2_clksel_recalc,
2105};
2106
2107/* SECURITY_L4_ICK2 based clocks */
2108
2109static struct clk security_l4_ick2 = {
2110	.name		= "security_l4_ick2",
2111	.ops		= &clkops_null,
2112	.parent		= &l4_ick,
2113	.recalc		= &followparent_recalc,
2114};
2115
2116static struct clk aes1_ick = {
2117	.name		= "aes1_ick",
2118	.ops		= &clkops_omap2_iclk_dflt_wait,
2119	.parent		= &security_l4_ick2,
2120	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2121	.enable_bit	= OMAP3430_EN_AES1_SHIFT,
2122	.recalc		= &followparent_recalc,
2123};
2124
2125static struct clk rng_ick = {
2126	.name		= "rng_ick",
2127	.ops		= &clkops_omap2_iclk_dflt_wait,
2128	.parent		= &security_l4_ick2,
2129	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2130	.enable_bit	= OMAP3430_EN_RNG_SHIFT,
2131	.recalc		= &followparent_recalc,
2132};
2133
2134static struct clk sha11_ick = {
2135	.name		= "sha11_ick",
2136	.ops		= &clkops_omap2_iclk_dflt_wait,
2137	.parent		= &security_l4_ick2,
2138	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2139	.enable_bit	= OMAP3430_EN_SHA11_SHIFT,
2140	.recalc		= &followparent_recalc,
2141};
2142
2143static struct clk des1_ick = {
2144	.name		= "des1_ick",
2145	.ops		= &clkops_omap2_iclk_dflt_wait,
2146	.parent		= &security_l4_ick2,
2147	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2148	.enable_bit	= OMAP3430_EN_DES1_SHIFT,
2149	.recalc		= &followparent_recalc,
2150};
2151
2152/* DSS */
2153static struct clk dss1_alwon_fck_3430es1 = {
2154	.name		= "dss1_alwon_fck",
2155	.ops		= &clkops_omap2_dflt,
2156	.parent		= &dpll4_m4x2_ck,
2157	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2158	.enable_bit	= OMAP3430_EN_DSS1_SHIFT,
2159	.clkdm_name	= "dss_clkdm",
2160	.recalc		= &followparent_recalc,
2161};
2162
2163static struct clk dss1_alwon_fck_3430es2 = {
2164	.name		= "dss1_alwon_fck",
2165	.ops		= &clkops_omap3430es2_dss_usbhost_wait,
2166	.parent		= &dpll4_m4x2_ck,
2167	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2168	.enable_bit	= OMAP3430_EN_DSS1_SHIFT,
2169	.clkdm_name	= "dss_clkdm",
2170	.recalc		= &followparent_recalc,
2171};
2172
2173static struct clk dss_tv_fck = {
2174	.name		= "dss_tv_fck",
2175	.ops		= &clkops_omap2_dflt,
2176	.parent		= &omap_54m_fck,
2177	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2178	.enable_bit	= OMAP3430_EN_TV_SHIFT,
2179	.clkdm_name	= "dss_clkdm",
2180	.recalc		= &followparent_recalc,
2181};
2182
2183static struct clk dss_96m_fck = {
2184	.name		= "dss_96m_fck",
2185	.ops		= &clkops_omap2_dflt,
2186	.parent		= &omap_96m_fck,
2187	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2188	.enable_bit	= OMAP3430_EN_TV_SHIFT,
2189	.clkdm_name	= "dss_clkdm",
2190	.recalc		= &followparent_recalc,
2191};
2192
2193static struct clk dss2_alwon_fck = {
2194	.name		= "dss2_alwon_fck",
2195	.ops		= &clkops_omap2_dflt,
2196	.parent		= &sys_ck,
2197	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2198	.enable_bit	= OMAP3430_EN_DSS2_SHIFT,
2199	.clkdm_name	= "dss_clkdm",
2200	.recalc		= &followparent_recalc,
2201};
2202
2203static struct clk dss_ick_3430es1 = {
2204	/* Handles both L3 and L4 clocks */
2205	.name		= "dss_ick",
2206	.ops		= &clkops_omap2_iclk_dflt,
2207	.parent		= &l4_ick,
2208	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2209	.enable_bit	= OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2210	.clkdm_name	= "dss_clkdm",
2211	.recalc		= &followparent_recalc,
2212};
2213
2214static struct clk dss_ick_3430es2 = {
2215	/* Handles both L3 and L4 clocks */
2216	.name		= "dss_ick",
2217	.ops		= &clkops_omap3430es2_iclk_dss_usbhost_wait,
2218	.parent		= &l4_ick,
2219	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2220	.enable_bit	= OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2221	.clkdm_name	= "dss_clkdm",
2222	.recalc		= &followparent_recalc,
2223};
2224
2225/* CAM */
2226
2227static struct clk cam_mclk = {
2228	.name		= "cam_mclk",
2229	.ops		= &clkops_omap2_dflt,
2230	.parent		= &dpll4_m5x2_ck,
2231	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2232	.enable_bit	= OMAP3430_EN_CAM_SHIFT,
2233	.clkdm_name	= "cam_clkdm",
2234	.recalc		= &followparent_recalc,
2235};
2236
2237static struct clk cam_ick = {
2238	/* Handles both L3 and L4 clocks */
2239	.name		= "cam_ick",
2240	.ops		= &clkops_omap2_iclk_dflt,
2241	.parent		= &l4_ick,
2242	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2243	.enable_bit	= OMAP3430_EN_CAM_SHIFT,
2244	.clkdm_name	= "cam_clkdm",
2245	.recalc		= &followparent_recalc,
2246};
2247
2248static struct clk csi2_96m_fck = {
2249	.name		= "csi2_96m_fck",
2250	.ops		= &clkops_omap2_dflt,
2251	.parent		= &core_96m_fck,
2252	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2253	.enable_bit	= OMAP3430_EN_CSI2_SHIFT,
2254	.clkdm_name	= "cam_clkdm",
2255	.recalc		= &followparent_recalc,
2256};
2257
2258/* USBHOST - 3430ES2 only */
2259
2260static struct clk usbhost_120m_fck = {
2261	.name		= "usbhost_120m_fck",
2262	.ops		= &clkops_omap2_dflt,
2263	.parent		= &dpll5_m2_ck,
2264	.enable_reg	= OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2265	.enable_bit	= OMAP3430ES2_EN_USBHOST2_SHIFT,
2266	.clkdm_name	= "usbhost_clkdm",
2267	.recalc		= &followparent_recalc,
2268};
2269
2270static struct clk usbhost_48m_fck = {
2271	.name		= "usbhost_48m_fck",
2272	.ops		= &clkops_omap3430es2_dss_usbhost_wait,
2273	.parent		= &omap_48m_fck,
2274	.enable_reg	= OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2275	.enable_bit	= OMAP3430ES2_EN_USBHOST1_SHIFT,
2276	.clkdm_name	= "usbhost_clkdm",
2277	.recalc		= &followparent_recalc,
2278};
2279
2280static struct clk usbhost_ick = {
2281	/* Handles both L3 and L4 clocks */
2282	.name		= "usbhost_ick",
2283	.ops		= &clkops_omap3430es2_iclk_dss_usbhost_wait,
2284	.parent		= &l4_ick,
2285	.enable_reg	= OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2286	.enable_bit	= OMAP3430ES2_EN_USBHOST_SHIFT,
2287	.clkdm_name	= "usbhost_clkdm",
2288	.recalc		= &followparent_recalc,
2289};
2290
2291/* WKUP */
2292
2293static const struct clksel_rate usim_96m_rates[] = {
2294	{ .div = 2,  .val = 3, .flags = RATE_IN_3XXX },
2295	{ .div = 4,  .val = 4, .flags = RATE_IN_3XXX },
2296	{ .div = 8,  .val = 5, .flags = RATE_IN_3XXX },
2297	{ .div = 10, .val = 6, .flags = RATE_IN_3XXX },
2298	{ .div = 0 },
2299};
2300
2301static const struct clksel_rate usim_120m_rates[] = {
2302	{ .div = 4,  .val = 7,	.flags = RATE_IN_3XXX },
2303	{ .div = 8,  .val = 8,	.flags = RATE_IN_3XXX },
2304	{ .div = 16, .val = 9,	.flags = RATE_IN_3XXX },
2305	{ .div = 20, .val = 10, .flags = RATE_IN_3XXX },
2306	{ .div = 0 },
2307};
2308
2309static const struct clksel usim_clksel[] = {
2310	{ .parent = &omap_96m_fck,	.rates = usim_96m_rates },
2311	{ .parent = &dpll5_m2_ck,	.rates = usim_120m_rates },
2312	{ .parent = &sys_ck,		.rates = div2_rates },
2313	{ .parent = NULL },
2314};
2315
2316/* 3430ES2 only */
2317static struct clk usim_fck = {
2318	.name		= "usim_fck",
2319	.ops		= &clkops_omap2_dflt_wait,
2320	.init		= &omap2_init_clksel_parent,
2321	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2322	.enable_bit	= OMAP3430ES2_EN_USIMOCP_SHIFT,
2323	.clksel_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2324	.clksel_mask	= OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2325	.clksel		= usim_clksel,
2326	.recalc		= &omap2_clksel_recalc,
2327};
2328
2329/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2330static struct clk gpt1_fck = {
2331	.name		= "gpt1_fck",
2332	.ops		= &clkops_omap2_dflt_wait,
2333	.init		= &omap2_init_clksel_parent,
2334	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2335	.enable_bit	= OMAP3430_EN_GPT1_SHIFT,
2336	.clksel_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2337	.clksel_mask	= OMAP3430_CLKSEL_GPT1_MASK,
2338	.clksel		= omap343x_gpt_clksel,
2339	.clkdm_name	= "wkup_clkdm",
2340	.recalc		= &omap2_clksel_recalc,
2341};
2342
2343static struct clk wkup_32k_fck = {
2344	.name		= "wkup_32k_fck",
2345	.ops		= &clkops_null,
2346	.parent		= &omap_32k_fck,
2347	.clkdm_name	= "wkup_clkdm",
2348	.recalc		= &followparent_recalc,
2349};
2350
2351static struct clk gpio1_dbck = {
2352	.name		= "gpio1_dbck",
2353	.ops		= &clkops_omap2_dflt,
2354	.parent		= &wkup_32k_fck,
2355	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2356	.enable_bit	= OMAP3430_EN_GPIO1_SHIFT,
2357	.clkdm_name	= "wkup_clkdm",
2358	.recalc		= &followparent_recalc,
2359};
2360
2361static struct clk wdt2_fck = {
2362	.name		= "wdt2_fck",
2363	.ops		= &clkops_omap2_dflt_wait,
2364	.parent		= &wkup_32k_fck,
2365	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2366	.enable_bit	= OMAP3430_EN_WDT2_SHIFT,
2367	.clkdm_name	= "wkup_clkdm",
2368	.recalc		= &followparent_recalc,
2369};
2370
2371static struct clk wkup_l4_ick = {
2372	.name		= "wkup_l4_ick",
2373	.ops		= &clkops_null,
2374	.parent		= &sys_ck,
2375	.clkdm_name	= "wkup_clkdm",
2376	.recalc		= &followparent_recalc,
2377};
2378
2379/* 3430ES2 only */
2380/* Never specifically named in the TRM, so we have to infer a likely name */
2381static struct clk usim_ick = {
2382	.name		= "usim_ick",
2383	.ops		= &clkops_omap2_iclk_dflt_wait,
2384	.parent		= &wkup_l4_ick,
2385	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2386	.enable_bit	= OMAP3430ES2_EN_USIMOCP_SHIFT,
2387	.clkdm_name	= "wkup_clkdm",
2388	.recalc		= &followparent_recalc,
2389};
2390
2391static struct clk wdt2_ick = {
2392	.name		= "wdt2_ick",
2393	.ops		= &clkops_omap2_iclk_dflt_wait,
2394	.parent		= &wkup_l4_ick,
2395	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2396	.enable_bit	= OMAP3430_EN_WDT2_SHIFT,
2397	.clkdm_name	= "wkup_clkdm",
2398	.recalc		= &followparent_recalc,
2399};
2400
2401static struct clk wdt1_ick = {
2402	.name		= "wdt1_ick",
2403	.ops		= &clkops_omap2_iclk_dflt_wait,
2404	.parent		= &wkup_l4_ick,
2405	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2406	.enable_bit	= OMAP3430_EN_WDT1_SHIFT,
2407	.clkdm_name	= "wkup_clkdm",
2408	.recalc		= &followparent_recalc,
2409};
2410
2411static struct clk gpio1_ick = {
2412	.name		= "gpio1_ick",
2413	.ops		= &clkops_omap2_iclk_dflt_wait,
2414	.parent		= &wkup_l4_ick,
2415	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2416	.enable_bit	= OMAP3430_EN_GPIO1_SHIFT,
2417	.clkdm_name	= "wkup_clkdm",
2418	.recalc		= &followparent_recalc,
2419};
2420
2421static struct clk omap_32ksync_ick = {
2422	.name		= "omap_32ksync_ick",
2423	.ops		= &clkops_omap2_iclk_dflt_wait,
2424	.parent		= &wkup_l4_ick,
2425	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2426	.enable_bit	= OMAP3430_EN_32KSYNC_SHIFT,
2427	.clkdm_name	= "wkup_clkdm",
2428	.recalc		= &followparent_recalc,
2429};
2430
2431/* XXX This clock no longer exists in 3430 TRM rev F */
2432static struct clk gpt12_ick = {
2433	.name		= "gpt12_ick",
2434	.ops		= &clkops_omap2_iclk_dflt_wait,
2435	.parent		= &wkup_l4_ick,
2436	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2437	.enable_bit	= OMAP3430_EN_GPT12_SHIFT,
2438	.clkdm_name	= "wkup_clkdm",
2439	.recalc		= &followparent_recalc,
2440};
2441
2442static struct clk gpt1_ick = {
2443	.name		= "gpt1_ick",
2444	.ops		= &clkops_omap2_iclk_dflt_wait,
2445	.parent		= &wkup_l4_ick,
2446	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2447	.enable_bit	= OMAP3430_EN_GPT1_SHIFT,
2448	.clkdm_name	= "wkup_clkdm",
2449	.recalc		= &followparent_recalc,
2450};
2451
2452
2453
2454/* PER clock domain */
2455
2456static struct clk per_96m_fck = {
2457	.name		= "per_96m_fck",
2458	.ops		= &clkops_null,
2459	.parent		= &omap_96m_alwon_fck,
2460	.clkdm_name	= "per_clkdm",
2461	.recalc		= &followparent_recalc,
2462};
2463
2464static struct clk per_48m_fck = {
2465	.name		= "per_48m_fck",
2466	.ops		= &clkops_null,
2467	.parent		= &omap_48m_fck,
2468	.clkdm_name	= "per_clkdm",
2469	.recalc		= &followparent_recalc,
2470};
2471
2472static struct clk uart3_fck = {
2473	.name		= "uart3_fck",
2474	.ops		= &clkops_omap2_dflt_wait,
2475	.parent		= &per_48m_fck,
2476	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2477	.enable_bit	= OMAP3430_EN_UART3_SHIFT,
2478	.clkdm_name	= "per_clkdm",
2479	.recalc		= &followparent_recalc,
2480};
2481
2482static struct clk uart4_fck = {
2483	.name		= "uart4_fck",
2484	.ops		= &clkops_omap2_dflt_wait,
2485	.parent		= &per_48m_fck,
2486	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2487	.enable_bit	= OMAP3630_EN_UART4_SHIFT,
2488	.clkdm_name	= "per_clkdm",
2489	.recalc		= &followparent_recalc,
2490};
2491
2492static struct clk uart4_fck_am35xx = {
2493	.name           = "uart4_fck",
2494	.ops            = &clkops_omap2_dflt_wait,
2495	.parent         = &per_48m_fck,
2496	.enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2497	.enable_bit     = OMAP3430_EN_UART4_SHIFT,
2498	.clkdm_name     = "core_l4_clkdm",
2499	.recalc         = &followparent_recalc,
2500};
2501
2502static struct clk gpt2_fck = {
2503	.name		= "gpt2_fck",
2504	.ops		= &clkops_omap2_dflt_wait,
2505	.init		= &omap2_init_clksel_parent,
2506	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2507	.enable_bit	= OMAP3430_EN_GPT2_SHIFT,
2508	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2509	.clksel_mask	= OMAP3430_CLKSEL_GPT2_MASK,
2510	.clksel		= omap343x_gpt_clksel,
2511	.clkdm_name	= "per_clkdm",
2512	.recalc		= &omap2_clksel_recalc,
2513};
2514
2515static struct clk gpt3_fck = {
2516	.name		= "gpt3_fck",
2517	.ops		= &clkops_omap2_dflt_wait,
2518	.init		= &omap2_init_clksel_parent,
2519	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2520	.enable_bit	= OMAP3430_EN_GPT3_SHIFT,
2521	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2522	.clksel_mask	= OMAP3430_CLKSEL_GPT3_MASK,
2523	.clksel		= omap343x_gpt_clksel,
2524	.clkdm_name	= "per_clkdm",
2525	.recalc		= &omap2_clksel_recalc,
2526};
2527
2528static struct clk gpt4_fck = {
2529	.name		= "gpt4_fck",
2530	.ops		= &clkops_omap2_dflt_wait,
2531	.init		= &omap2_init_clksel_parent,
2532	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2533	.enable_bit	= OMAP3430_EN_GPT4_SHIFT,
2534	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2535	.clksel_mask	= OMAP3430_CLKSEL_GPT4_MASK,
2536	.clksel		= omap343x_gpt_clksel,
2537	.clkdm_name	= "per_clkdm",
2538	.recalc		= &omap2_clksel_recalc,
2539};
2540
2541static struct clk gpt5_fck = {
2542	.name		= "gpt5_fck",
2543	.ops		= &clkops_omap2_dflt_wait,
2544	.init		= &omap2_init_clksel_parent,
2545	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2546	.enable_bit	= OMAP3430_EN_GPT5_SHIFT,
2547	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2548	.clksel_mask	= OMAP3430_CLKSEL_GPT5_MASK,
2549	.clksel		= omap343x_gpt_clksel,
2550	.clkdm_name	= "per_clkdm",
2551	.recalc		= &omap2_clksel_recalc,
2552};
2553
2554static struct clk gpt6_fck = {
2555	.name		= "gpt6_fck",
2556	.ops		= &clkops_omap2_dflt_wait,
2557	.init		= &omap2_init_clksel_parent,
2558	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2559	.enable_bit	= OMAP3430_EN_GPT6_SHIFT,
2560	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2561	.clksel_mask	= OMAP3430_CLKSEL_GPT6_MASK,
2562	.clksel		= omap343x_gpt_clksel,
2563	.clkdm_name	= "per_clkdm",
2564	.recalc		= &omap2_clksel_recalc,
2565};
2566
2567static struct clk gpt7_fck = {
2568	.name		= "gpt7_fck",
2569	.ops		= &clkops_omap2_dflt_wait,
2570	.init		= &omap2_init_clksel_parent,
2571	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2572	.enable_bit	= OMAP3430_EN_GPT7_SHIFT,
2573	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2574	.clksel_mask	= OMAP3430_CLKSEL_GPT7_MASK,
2575	.clksel		= omap343x_gpt_clksel,
2576	.clkdm_name	= "per_clkdm",
2577	.recalc		= &omap2_clksel_recalc,
2578};
2579
2580static struct clk gpt8_fck = {
2581	.name		= "gpt8_fck",
2582	.ops		= &clkops_omap2_dflt_wait,
2583	.init		= &omap2_init_clksel_parent,
2584	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2585	.enable_bit	= OMAP3430_EN_GPT8_SHIFT,
2586	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2587	.clksel_mask	= OMAP3430_CLKSEL_GPT8_MASK,
2588	.clksel		= omap343x_gpt_clksel,
2589	.clkdm_name	= "per_clkdm",
2590	.recalc		= &omap2_clksel_recalc,
2591};
2592
2593static struct clk gpt9_fck = {
2594	.name		= "gpt9_fck",
2595	.ops		= &clkops_omap2_dflt_wait,
2596	.init		= &omap2_init_clksel_parent,
2597	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2598	.enable_bit	= OMAP3430_EN_GPT9_SHIFT,
2599	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2600	.clksel_mask	= OMAP3430_CLKSEL_GPT9_MASK,
2601	.clksel		= omap343x_gpt_clksel,
2602	.clkdm_name	= "per_clkdm",
2603	.recalc		= &omap2_clksel_recalc,
2604};
2605
2606static struct clk per_32k_alwon_fck = {
2607	.name		= "per_32k_alwon_fck",
2608	.ops		= &clkops_null,
2609	.parent		= &omap_32k_fck,
2610	.clkdm_name	= "per_clkdm",
2611	.recalc		= &followparent_recalc,
2612};
2613
2614static struct clk gpio6_dbck = {
2615	.name		= "gpio6_dbck",
2616	.ops		= &clkops_omap2_dflt,
2617	.parent		= &per_32k_alwon_fck,
2618	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2619	.enable_bit	= OMAP3430_EN_GPIO6_SHIFT,
2620	.clkdm_name	= "per_clkdm",
2621	.recalc		= &followparent_recalc,
2622};
2623
2624static struct clk gpio5_dbck = {
2625	.name		= "gpio5_dbck",
2626	.ops		= &clkops_omap2_dflt,
2627	.parent		= &per_32k_alwon_fck,
2628	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2629	.enable_bit	= OMAP3430_EN_GPIO5_SHIFT,
2630	.clkdm_name	= "per_clkdm",
2631	.recalc		= &followparent_recalc,
2632};
2633
2634static struct clk gpio4_dbck = {
2635	.name		= "gpio4_dbck",
2636	.ops		= &clkops_omap2_dflt,
2637	.parent		= &per_32k_alwon_fck,
2638	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2639	.enable_bit	= OMAP3430_EN_GPIO4_SHIFT,
2640	.clkdm_name	= "per_clkdm",
2641	.recalc		= &followparent_recalc,
2642};
2643
2644static struct clk gpio3_dbck = {
2645	.name		= "gpio3_dbck",
2646	.ops		= &clkops_omap2_dflt,
2647	.parent		= &per_32k_alwon_fck,
2648	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2649	.enable_bit	= OMAP3430_EN_GPIO3_SHIFT,
2650	.clkdm_name	= "per_clkdm",
2651	.recalc		= &followparent_recalc,
2652};
2653
2654static struct clk gpio2_dbck = {
2655	.name		= "gpio2_dbck",
2656	.ops		= &clkops_omap2_dflt,
2657	.parent		= &per_32k_alwon_fck,
2658	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2659	.enable_bit	= OMAP3430_EN_GPIO2_SHIFT,
2660	.clkdm_name	= "per_clkdm",
2661	.recalc		= &followparent_recalc,
2662};
2663
2664static struct clk wdt3_fck = {
2665	.name		= "wdt3_fck",
2666	.ops		= &clkops_omap2_dflt_wait,
2667	.parent		= &per_32k_alwon_fck,
2668	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2669	.enable_bit	= OMAP3430_EN_WDT3_SHIFT,
2670	.clkdm_name	= "per_clkdm",
2671	.recalc		= &followparent_recalc,
2672};
2673
2674static struct clk per_l4_ick = {
2675	.name		= "per_l4_ick",
2676	.ops		= &clkops_null,
2677	.parent		= &l4_ick,
2678	.clkdm_name	= "per_clkdm",
2679	.recalc		= &followparent_recalc,
2680};
2681
2682static struct clk gpio6_ick = {
2683	.name		= "gpio6_ick",
2684	.ops		= &clkops_omap2_iclk_dflt_wait,
2685	.parent		= &per_l4_ick,
2686	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2687	.enable_bit	= OMAP3430_EN_GPIO6_SHIFT,
2688	.clkdm_name	= "per_clkdm",
2689	.recalc		= &followparent_recalc,
2690};
2691
2692static struct clk gpio5_ick = {
2693	.name		= "gpio5_ick",
2694	.ops		= &clkops_omap2_iclk_dflt_wait,
2695	.parent		= &per_l4_ick,
2696	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2697	.enable_bit	= OMAP3430_EN_GPIO5_SHIFT,
2698	.clkdm_name	= "per_clkdm",
2699	.recalc		= &followparent_recalc,
2700};
2701
2702static struct clk gpio4_ick = {
2703	.name		= "gpio4_ick",
2704	.ops		= &clkops_omap2_iclk_dflt_wait,
2705	.parent		= &per_l4_ick,
2706	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2707	.enable_bit	= OMAP3430_EN_GPIO4_SHIFT,
2708	.clkdm_name	= "per_clkdm",
2709	.recalc		= &followparent_recalc,
2710};
2711
2712static struct clk gpio3_ick = {
2713	.name		= "gpio3_ick",
2714	.ops		= &clkops_omap2_iclk_dflt_wait,
2715	.parent		= &per_l4_ick,
2716	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2717	.enable_bit	= OMAP3430_EN_GPIO3_SHIFT,
2718	.clkdm_name	= "per_clkdm",
2719	.recalc		= &followparent_recalc,
2720};
2721
2722static struct clk gpio2_ick = {
2723	.name		= "gpio2_ick",
2724	.ops		= &clkops_omap2_iclk_dflt_wait,
2725	.parent		= &per_l4_ick,
2726	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2727	.enable_bit	= OMAP3430_EN_GPIO2_SHIFT,
2728	.clkdm_name	= "per_clkdm",
2729	.recalc		= &followparent_recalc,
2730};
2731
2732static struct clk wdt3_ick = {
2733	.name		= "wdt3_ick",
2734	.ops		= &clkops_omap2_iclk_dflt_wait,
2735	.parent		= &per_l4_ick,
2736	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2737	.enable_bit	= OMAP3430_EN_WDT3_SHIFT,
2738	.clkdm_name	= "per_clkdm",
2739	.recalc		= &followparent_recalc,
2740};
2741
2742static struct clk uart3_ick = {
2743	.name		= "uart3_ick",
2744	.ops		= &clkops_omap2_iclk_dflt_wait,
2745	.parent		= &per_l4_ick,
2746	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2747	.enable_bit	= OMAP3430_EN_UART3_SHIFT,
2748	.clkdm_name	= "per_clkdm",
2749	.recalc		= &followparent_recalc,
2750};
2751
2752static struct clk uart4_ick = {
2753	.name		= "uart4_ick",
2754	.ops		= &clkops_omap2_iclk_dflt_wait,
2755	.parent		= &per_l4_ick,
2756	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2757	.enable_bit	= OMAP3630_EN_UART4_SHIFT,
2758	.clkdm_name	= "per_clkdm",
2759	.recalc		= &followparent_recalc,
2760};
2761
2762static struct clk gpt9_ick = {
2763	.name		= "gpt9_ick",
2764	.ops		= &clkops_omap2_iclk_dflt_wait,
2765	.parent		= &per_l4_ick,
2766	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2767	.enable_bit	= OMAP3430_EN_GPT9_SHIFT,
2768	.clkdm_name	= "per_clkdm",
2769	.recalc		= &followparent_recalc,
2770};
2771
2772static struct clk gpt8_ick = {
2773	.name		= "gpt8_ick",
2774	.ops		= &clkops_omap2_iclk_dflt_wait,
2775	.parent		= &per_l4_ick,
2776	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2777	.enable_bit	= OMAP3430_EN_GPT8_SHIFT,
2778	.clkdm_name	= "per_clkdm",
2779	.recalc		= &followparent_recalc,
2780};
2781
2782static struct clk gpt7_ick = {
2783	.name		= "gpt7_ick",
2784	.ops		= &clkops_omap2_iclk_dflt_wait,
2785	.parent		= &per_l4_ick,
2786	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2787	.enable_bit	= OMAP3430_EN_GPT7_SHIFT,
2788	.clkdm_name	= "per_clkdm",
2789	.recalc		= &followparent_recalc,
2790};
2791
2792static struct clk gpt6_ick = {
2793	.name		= "gpt6_ick",
2794	.ops		= &clkops_omap2_iclk_dflt_wait,
2795	.parent		= &per_l4_ick,
2796	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2797	.enable_bit	= OMAP3430_EN_GPT6_SHIFT,
2798	.clkdm_name	= "per_clkdm",
2799	.recalc		= &followparent_recalc,
2800};
2801
2802static struct clk gpt5_ick = {
2803	.name		= "gpt5_ick",
2804	.ops		= &clkops_omap2_iclk_dflt_wait,
2805	.parent		= &per_l4_ick,
2806	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2807	.enable_bit	= OMAP3430_EN_GPT5_SHIFT,
2808	.clkdm_name	= "per_clkdm",
2809	.recalc		= &followparent_recalc,
2810};
2811
2812static struct clk gpt4_ick = {
2813	.name		= "gpt4_ick",
2814	.ops		= &clkops_omap2_iclk_dflt_wait,
2815	.parent		= &per_l4_ick,
2816	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2817	.enable_bit	= OMAP3430_EN_GPT4_SHIFT,
2818	.clkdm_name	= "per_clkdm",
2819	.recalc		= &followparent_recalc,
2820};
2821
2822static struct clk gpt3_ick = {
2823	.name		= "gpt3_ick",
2824	.ops		= &clkops_omap2_iclk_dflt_wait,
2825	.parent		= &per_l4_ick,
2826	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2827	.enable_bit	= OMAP3430_EN_GPT3_SHIFT,
2828	.clkdm_name	= "per_clkdm",
2829	.recalc		= &followparent_recalc,
2830};
2831
2832static struct clk gpt2_ick = {
2833	.name		= "gpt2_ick",
2834	.ops		= &clkops_omap2_iclk_dflt_wait,
2835	.parent		= &per_l4_ick,
2836	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2837	.enable_bit	= OMAP3430_EN_GPT2_SHIFT,
2838	.clkdm_name	= "per_clkdm",
2839	.recalc		= &followparent_recalc,
2840};
2841
2842static struct clk mcbsp2_ick = {
2843	.name		= "mcbsp2_ick",
2844	.ops		= &clkops_omap2_iclk_dflt_wait,
2845	.parent		= &per_l4_ick,
2846	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2847	.enable_bit	= OMAP3430_EN_MCBSP2_SHIFT,
2848	.clkdm_name	= "per_clkdm",
2849	.recalc		= &followparent_recalc,
2850};
2851
2852static struct clk mcbsp3_ick = {
2853	.name		= "mcbsp3_ick",
2854	.ops		= &clkops_omap2_iclk_dflt_wait,
2855	.parent		= &per_l4_ick,
2856	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2857	.enable_bit	= OMAP3430_EN_MCBSP3_SHIFT,
2858	.clkdm_name	= "per_clkdm",
2859	.recalc		= &followparent_recalc,
2860};
2861
2862static struct clk mcbsp4_ick = {
2863	.name		= "mcbsp4_ick",
2864	.ops		= &clkops_omap2_iclk_dflt_wait,
2865	.parent		= &per_l4_ick,
2866	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2867	.enable_bit	= OMAP3430_EN_MCBSP4_SHIFT,
2868	.clkdm_name	= "per_clkdm",
2869	.recalc		= &followparent_recalc,
2870};
2871
2872static const struct clksel mcbsp_234_clksel[] = {
2873	{ .parent = &per_96m_fck,  .rates = common_mcbsp_96m_rates },
2874	{ .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2875	{ .parent = NULL }
2876};
2877
2878static struct clk mcbsp2_fck = {
2879	.name		= "mcbsp2_fck",
2880	.ops		= &clkops_omap2_dflt_wait,
2881	.init		= &omap2_init_clksel_parent,
2882	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2883	.enable_bit	= OMAP3430_EN_MCBSP2_SHIFT,
2884	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2885	.clksel_mask	= OMAP2_MCBSP2_CLKS_MASK,
2886	.clksel		= mcbsp_234_clksel,
2887	.clkdm_name	= "per_clkdm",
2888	.recalc		= &omap2_clksel_recalc,
2889};
2890
2891static struct clk mcbsp3_fck = {
2892	.name		= "mcbsp3_fck",
2893	.ops		= &clkops_omap2_dflt_wait,
2894	.init		= &omap2_init_clksel_parent,
2895	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2896	.enable_bit	= OMAP3430_EN_MCBSP3_SHIFT,
2897	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2898	.clksel_mask	= OMAP2_MCBSP3_CLKS_MASK,
2899	.clksel		= mcbsp_234_clksel,
2900	.clkdm_name	= "per_clkdm",
2901	.recalc		= &omap2_clksel_recalc,
2902};
2903
2904static struct clk mcbsp4_fck = {
2905	.name		= "mcbsp4_fck",
2906	.ops		= &clkops_omap2_dflt_wait,
2907	.init		= &omap2_init_clksel_parent,
2908	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2909	.enable_bit	= OMAP3430_EN_MCBSP4_SHIFT,
2910	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2911	.clksel_mask	= OMAP2_MCBSP4_CLKS_MASK,
2912	.clksel		= mcbsp_234_clksel,
2913	.clkdm_name	= "per_clkdm",
2914	.recalc		= &omap2_clksel_recalc,
2915};
2916
2917/* EMU clocks */
2918
2919/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2920
2921static const struct clksel_rate emu_src_sys_rates[] = {
2922	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },
2923	{ .div = 0 },
2924};
2925
2926static const struct clksel_rate emu_src_core_rates[] = {
2927	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2928	{ .div = 0 },
2929};
2930
2931static const struct clksel_rate emu_src_per_rates[] = {
2932	{ .div = 1, .val = 2, .flags = RATE_IN_3XXX },
2933	{ .div = 0 },
2934};
2935
2936static const struct clksel_rate emu_src_mpu_rates[] = {
2937	{ .div = 1, .val = 3, .flags = RATE_IN_3XXX },
2938	{ .div = 0 },
2939};
2940
2941static const struct clksel emu_src_clksel[] = {
2942	{ .parent = &sys_ck,		.rates = emu_src_sys_rates },
2943	{ .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2944	{ .parent = &emu_per_alwon_ck,	.rates = emu_src_per_rates },
2945	{ .parent = &emu_mpu_alwon_ck,	.rates = emu_src_mpu_rates },
2946	{ .parent = NULL },
2947};
2948
2949/*
2950 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2951 * to switch the source of some of the EMU clocks.
2952 * XXX Are there CLKEN bits for these EMU clks?
2953 */
2954static struct clk emu_src_ck = {
2955	.name		= "emu_src_ck",
2956	.ops		= &clkops_null,
2957	.init		= &omap2_init_clksel_parent,
2958	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2959	.clksel_mask	= OMAP3430_MUX_CTRL_MASK,
2960	.clksel		= emu_src_clksel,
2961	.clkdm_name	= "emu_clkdm",
2962	.recalc		= &omap2_clksel_recalc,
2963};
2964
2965static const struct clksel_rate pclk_emu_rates[] = {
2966	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2967	{ .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2968	{ .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2969	{ .div = 6, .val = 6, .flags = RATE_IN_3XXX },
2970	{ .div = 0 },
2971};
2972
2973static const struct clksel pclk_emu_clksel[] = {
2974	{ .parent = &emu_src_ck, .rates = pclk_emu_rates },
2975	{ .parent = NULL },
2976};
2977
2978static struct clk pclk_fck = {
2979	.name		= "pclk_fck",
2980	.ops		= &clkops_null,
2981	.init		= &omap2_init_clksel_parent,
2982	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2983	.clksel_mask	= OMAP3430_CLKSEL_PCLK_MASK,
2984	.clksel		= pclk_emu_clksel,
2985	.clkdm_name	= "emu_clkdm",
2986	.recalc		= &omap2_clksel_recalc,
2987};
2988
2989static const struct clksel_rate pclkx2_emu_rates[] = {
2990	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2991	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2992	{ .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2993	{ .div = 0 },
2994};
2995
2996static const struct clksel pclkx2_emu_clksel[] = {
2997	{ .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2998	{ .parent = NULL },
2999};
3000
3001static struct clk pclkx2_fck = {
3002	.name		= "pclkx2_fck",
3003	.ops		= &clkops_null,
3004	.init		= &omap2_init_clksel_parent,
3005	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3006	.clksel_mask	= OMAP3430_CLKSEL_PCLKX2_MASK,
3007	.clksel		= pclkx2_emu_clksel,
3008	.clkdm_name	= "emu_clkdm",
3009	.recalc		= &omap2_clksel_recalc,
3010};
3011
3012static const struct clksel atclk_emu_clksel[] = {
3013	{ .parent = &emu_src_ck, .rates = div2_rates },
3014	{ .parent = NULL },
3015};
3016
3017static struct clk atclk_fck = {
3018	.name		= "atclk_fck",
3019	.ops		= &clkops_null,
3020	.init		= &omap2_init_clksel_parent,
3021	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3022	.clksel_mask	= OMAP3430_CLKSEL_ATCLK_MASK,
3023	.clksel		= atclk_emu_clksel,
3024	.clkdm_name	= "emu_clkdm",
3025	.recalc		= &omap2_clksel_recalc,
3026};
3027
3028static struct clk traceclk_src_fck = {
3029	.name		= "traceclk_src_fck",
3030	.ops		= &clkops_null,
3031	.init		= &omap2_init_clksel_parent,
3032	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3033	.clksel_mask	= OMAP3430_TRACE_MUX_CTRL_MASK,
3034	.clksel		= emu_src_clksel,
3035	.clkdm_name	= "emu_clkdm",
3036	.recalc		= &omap2_clksel_recalc,
3037};
3038
3039static const struct clksel_rate traceclk_rates[] = {
3040	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
3041	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
3042	{ .div = 4, .val = 4, .flags = RATE_IN_3XXX },
3043	{ .div = 0 },
3044};
3045
3046static const struct clksel traceclk_clksel[] = {
3047	{ .parent = &traceclk_src_fck, .rates = traceclk_rates },
3048	{ .parent = NULL },
3049};
3050
3051static struct clk traceclk_fck = {
3052	.name		= "traceclk_fck",
3053	.ops		= &clkops_null,
3054	.init		= &omap2_init_clksel_parent,
3055	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3056	.clksel_mask	= OMAP3430_CLKSEL_TRACECLK_MASK,
3057	.clksel		= traceclk_clksel,
3058	.clkdm_name	= "emu_clkdm",
3059	.recalc		= &omap2_clksel_recalc,
3060};
3061
3062/* SR clocks */
3063
3064/* SmartReflex fclk (VDD1) */
3065static struct clk sr1_fck = {
3066	.name		= "sr1_fck",
3067	.ops		= &clkops_omap2_dflt_wait,
3068	.parent		= &sys_ck,
3069	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3070	.enable_bit	= OMAP3430_EN_SR1_SHIFT,
3071	.clkdm_name	= "wkup_clkdm",
3072	.recalc		= &followparent_recalc,
3073};
3074
3075/* SmartReflex fclk (VDD2) */
3076static struct clk sr2_fck = {
3077	.name		= "sr2_fck",
3078	.ops		= &clkops_omap2_dflt_wait,
3079	.parent		= &sys_ck,
3080	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3081	.enable_bit	= OMAP3430_EN_SR2_SHIFT,
3082	.clkdm_name	= "wkup_clkdm",
3083	.recalc		= &followparent_recalc,
3084};
3085
3086static struct clk sr_l4_ick = {
3087	.name		= "sr_l4_ick",
3088	.ops		= &clkops_null, /* RMK: missing? */
3089	.parent		= &l4_ick,
3090	.clkdm_name	= "core_l4_clkdm",
3091	.recalc		= &followparent_recalc,
3092};
3093
3094/* SECURE_32K_FCK clocks */
3095
3096static struct clk gpt12_fck = {
3097	.name		= "gpt12_fck",
3098	.ops		= &clkops_null,
3099	.parent		= &secure_32k_fck,
3100	.clkdm_name	= "wkup_clkdm",
3101	.recalc		= &followparent_recalc,
3102};
3103
3104static struct clk wdt1_fck = {
3105	.name		= "wdt1_fck",
3106	.ops		= &clkops_null,
3107	.parent		= &secure_32k_fck,
3108	.clkdm_name	= "wkup_clkdm",
3109	.recalc		= &followparent_recalc,
3110};
3111
3112/* Clocks for AM35XX */
3113static struct clk ipss_ick = {
3114	.name		= "ipss_ick",
3115	.ops		= &clkops_am35xx_ipss_wait,
3116	.parent		= &core_l3_ick,
3117	.clkdm_name	= "core_l3_clkdm",
3118	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3119	.enable_bit	= AM35XX_EN_IPSS_SHIFT,
3120	.recalc		= &followparent_recalc,
3121};
3122
3123static struct clk emac_ick = {
3124	.name		= "emac_ick",
3125	.ops		= &clkops_am35xx_ipss_module_wait,
3126	.parent		= &ipss_ick,
3127	.clkdm_name	= "core_l3_clkdm",
3128	.enable_reg	= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3129	.enable_bit	= AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
3130	.recalc		= &followparent_recalc,
3131};
3132
3133static struct clk rmii_ck = {
3134	.name		= "rmii_ck",
3135	.ops		= &clkops_null,
3136	.rate		= 50000000,
3137};
3138
3139static struct clk emac_fck = {
3140	.name		= "emac_fck",
3141	.ops		= &clkops_omap2_dflt,
3142	.parent		= &rmii_ck,
3143	.enable_reg	= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3144	.enable_bit	= AM35XX_CPGMAC_FCLK_SHIFT,
3145	.recalc		= &followparent_recalc,
3146};
3147
3148static struct clk hsotgusb_ick_am35xx = {
3149	.name		= "hsotgusb_ick",
3150	.ops		= &clkops_am35xx_ipss_module_wait,
3151	.parent		= &ipss_ick,
3152	.clkdm_name	= "core_l3_clkdm",
3153	.enable_reg	= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3154	.enable_bit	= AM35XX_USBOTG_VBUSP_CLK_SHIFT,
3155	.recalc		= &followparent_recalc,
3156};
3157
3158static struct clk hsotgusb_fck_am35xx = {
3159	.name		= "hsotgusb_fck",
3160	.ops		= &clkops_omap2_dflt,
3161	.parent		= &sys_ck,
3162	.clkdm_name	= "core_l3_clkdm",
3163	.enable_reg	= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3164	.enable_bit	= AM35XX_USBOTG_FCLK_SHIFT,
3165	.recalc		= &followparent_recalc,
3166};
3167
3168static struct clk hecc_ck = {
3169	.name		= "hecc_ck",
3170	.ops		= &clkops_am35xx_ipss_module_wait,
3171	.parent		= &sys_ck,
3172	.clkdm_name	= "core_l3_clkdm",
3173	.enable_reg	= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3174	.enable_bit	= AM35XX_HECC_VBUSP_CLK_SHIFT,
3175	.recalc		= &followparent_recalc,
3176};
3177
3178static struct clk vpfe_ick = {
3179	.name		= "vpfe_ick",
3180	.ops		= &clkops_am35xx_ipss_module_wait,
3181	.parent		= &ipss_ick,
3182	.clkdm_name	= "core_l3_clkdm",
3183	.enable_reg	= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3184	.enable_bit	= AM35XX_VPFE_VBUSP_CLK_SHIFT,
3185	.recalc		= &followparent_recalc,
3186};
3187
3188static struct clk pclk_ck = {
3189	.name		= "pclk_ck",
3190	.ops		= &clkops_null,
3191	.rate		= 27000000,
3192};
3193
3194static struct clk vpfe_fck = {
3195	.name		= "vpfe_fck",
3196	.ops		= &clkops_omap2_dflt,
3197	.parent		= &pclk_ck,
3198	.enable_reg	= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3199	.enable_bit	= AM35XX_VPFE_FCLK_SHIFT,
3200	.recalc		= &followparent_recalc,
3201};
3202
3203/*
3204 * The UART1/2 functional clock acts as the functional
3205 * clock for UART4. No separate fclk control available.
3206 */
3207static struct clk uart4_ick_am35xx = {
3208	.name		= "uart4_ick",
3209	.ops		= &clkops_omap2_iclk_dflt_wait,
3210	.parent		= &core_l4_ick,
3211	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3212	.enable_bit	= AM35XX_EN_UART4_SHIFT,
3213	.clkdm_name	= "core_l4_clkdm",
3214	.recalc		= &followparent_recalc,
3215};
3216
3217static struct clk dummy_apb_pclk = {
3218	.name		= "apb_pclk",
3219	.ops		= &clkops_null,
3220};
3221
3222/*
3223 * clkdev
3224 */
3225
3226/* XXX At some point we should rename this file to clock3xxx_data.c */
3227static struct omap_clk omap3xxx_clks[] = {
3228	CLK(NULL,	"apb_pclk",	&dummy_apb_pclk,	CK_3XXX),
3229	CLK(NULL,	"omap_32k_fck",	&omap_32k_fck,	CK_3XXX),
3230	CLK(NULL,	"virt_12m_ck",	&virt_12m_ck,	CK_3XXX),
3231	CLK(NULL,	"virt_13m_ck",	&virt_13m_ck,	CK_3XXX),
3232	CLK(NULL,	"virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX  | CK_36XX),
3233	CLK(NULL,	"virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
3234	CLK(NULL,	"virt_26m_ck",	&virt_26m_ck,	CK_3XXX),
3235	CLK(NULL,	"virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
3236	CLK(NULL,	"osc_sys_ck",	&osc_sys_ck,	CK_3XXX),
3237	CLK(NULL,	"sys_ck",	&sys_ck,	CK_3XXX),
3238	CLK(NULL,	"sys_altclk",	&sys_altclk,	CK_3XXX),
3239	CLK("omap-mcbsp.1",	"pad_fck",	&mcbsp_clks,	CK_3XXX),
3240	CLK("omap-mcbsp.2",	"pad_fck",	&mcbsp_clks,	CK_3XXX),
3241	CLK("omap-mcbsp.3",	"pad_fck",	&mcbsp_clks,	CK_3XXX),
3242	CLK("omap-mcbsp.4",	"pad_fck",	&mcbsp_clks,	CK_3XXX),
3243	CLK("omap-mcbsp.5",	"pad_fck",	&mcbsp_clks,	CK_3XXX),
3244	CLK(NULL,	"mcbsp_clks",	&mcbsp_clks,	CK_3XXX),
3245	CLK(NULL,	"sys_clkout1",	&sys_clkout1,	CK_3XXX),
3246	CLK(NULL,	"dpll1_ck",	&dpll1_ck,	CK_3XXX),
3247	CLK(NULL,	"dpll1_x2_ck",	&dpll1_x2_ck,	CK_3XXX),
3248	CLK(NULL,	"dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
3249	CLK(NULL,	"dpll2_ck",	&dpll2_ck,	CK_34XX | CK_36XX),
3250	CLK(NULL,	"dpll2_m2_ck",	&dpll2_m2_ck,	CK_34XX | CK_36XX),
3251	CLK(NULL,	"dpll3_ck",	&dpll3_ck,	CK_3XXX),
3252	CLK(NULL,	"core_ck",	&core_ck,	CK_3XXX),
3253	CLK(NULL,	"dpll3_x2_ck",	&dpll3_x2_ck,	CK_3XXX),
3254	CLK(NULL,	"dpll3_m2_ck",	&dpll3_m2_ck,	CK_3XXX),
3255	CLK(NULL,	"dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
3256	CLK(NULL,	"dpll3_m3_ck",	&dpll3_m3_ck,	CK_3XXX),
3257	CLK(NULL,	"dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
3258	CLK("etb",	"emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
3259	CLK(NULL,	"dpll4_ck",	&dpll4_ck,	CK_3XXX),
3260	CLK(NULL,	"dpll4_x2_ck",	&dpll4_x2_ck,	CK_3XXX),
3261	CLK(NULL,	"omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
3262	CLK(NULL,	"omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
3263	CLK(NULL,	"omap_96m_fck",	&omap_96m_fck,	CK_3XXX),
3264	CLK(NULL,	"cm_96m_fck",	&cm_96m_fck,	CK_3XXX),
3265	CLK(NULL,	"omap_54m_fck",	&omap_54m_fck,	CK_3XXX),
3266	CLK(NULL,	"omap_48m_fck",	&omap_48m_fck,	CK_3XXX),
3267	CLK(NULL,	"omap_12m_fck",	&omap_12m_fck,	CK_3XXX),
3268	CLK(NULL,	"dpll4_m2_ck",	&dpll4_m2_ck,	CK_3XXX),
3269	CLK(NULL,	"dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
3270	CLK(NULL,	"dpll4_m3_ck",	&dpll4_m3_ck,	CK_3XXX),
3271	CLK(NULL,	"dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
3272	CLK(NULL,	"dpll4_m4_ck",	&dpll4_m4_ck,	CK_3XXX),
3273	CLK(NULL,	"dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
3274	CLK(NULL,	"dpll4_m5_ck",	&dpll4_m5_ck,	CK_3XXX),
3275	CLK(NULL,	"dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
3276	CLK(NULL,	"dpll4_m6_ck",	&dpll4_m6_ck,	CK_3XXX),
3277	CLK(NULL,	"dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
3278	CLK("etb",	"emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
3279	CLK(NULL,	"dpll5_ck",	&dpll5_ck,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3280	CLK(NULL,	"dpll5_m2_ck",	&dpll5_m2_ck,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3281	CLK(NULL,	"clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
3282	CLK(NULL,	"sys_clkout2",	&sys_clkout2,	CK_3XXX),
3283	CLK(NULL,	"corex2_fck",	&corex2_fck,	CK_3XXX),
3284	CLK(NULL,	"dpll1_fck",	&dpll1_fck,	CK_3XXX),
3285	CLK(NULL,	"mpu_ck",	&mpu_ck,	CK_3XXX),
3286	CLK(NULL,	"arm_fck",	&arm_fck,	CK_3XXX),
3287	CLK("etb",	"emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
3288	CLK(NULL,	"dpll2_fck",	&dpll2_fck,	CK_34XX | CK_36XX),
3289	CLK(NULL,	"iva2_ck",	&iva2_ck,	CK_34XX | CK_36XX),
3290	CLK(NULL,	"l3_ick",	&l3_ick,	CK_3XXX),
3291	CLK(NULL,	"l4_ick",	&l4_ick,	CK_3XXX),
3292	CLK(NULL,	"rm_ick",	&rm_ick,	CK_3XXX),
3293	CLK(NULL,	"gfx_l3_ck",	&gfx_l3_ck,	CK_3430ES1),
3294	CLK(NULL,	"gfx_l3_fck",	&gfx_l3_fck,	CK_3430ES1),
3295	CLK(NULL,	"gfx_l3_ick",	&gfx_l3_ick,	CK_3430ES1),
3296	CLK(NULL,	"gfx_cg1_ck",	&gfx_cg1_ck,	CK_3430ES1),
3297	CLK(NULL,	"gfx_cg2_ck",	&gfx_cg2_ck,	CK_3430ES1),
3298	CLK(NULL,	"sgx_fck",	&sgx_fck,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3299	CLK(NULL,	"sgx_ick",	&sgx_ick,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3300	CLK(NULL,	"d2d_26m_fck",	&d2d_26m_fck,	CK_3430ES1),
3301	CLK(NULL,	"modem_fck",	&modem_fck,	CK_34XX | CK_36XX),
3302	CLK(NULL,	"sad2d_ick",	&sad2d_ick,	CK_34XX | CK_36XX),
3303	CLK(NULL,	"mad2d_ick",	&mad2d_ick,	CK_34XX | CK_36XX),
3304	CLK(NULL,	"gpt10_fck",	&gpt10_fck,	CK_3XXX),
3305	CLK(NULL,	"gpt11_fck",	&gpt11_fck,	CK_3XXX),
3306	CLK(NULL,	"cpefuse_fck",	&cpefuse_fck,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3307	CLK(NULL,	"ts_fck",	&ts_fck,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3308	CLK(NULL,	"usbtll_fck",	&usbtll_fck,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3309	CLK("usbhs_omap",	"usbtll_fck",	&usbtll_fck,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3310	CLK("omap-mcbsp.1",	"prcm_fck",	&core_96m_fck,	CK_3XXX),
3311	CLK("omap-mcbsp.5",	"prcm_fck",	&core_96m_fck,	CK_3XXX),
3312	CLK(NULL,	"core_96m_fck",	&core_96m_fck,	CK_3XXX),
3313	CLK(NULL,	"mmchs3_fck",	&mmchs3_fck,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3314	CLK(NULL,	"mmchs2_fck",	&mmchs2_fck,	CK_3XXX),
3315	CLK(NULL,	"mspro_fck",	&mspro_fck,	CK_34XX | CK_36XX),
3316	CLK(NULL,	"mmchs1_fck",	&mmchs1_fck,	CK_3XXX),
3317	CLK(NULL,	"i2c3_fck",	&i2c3_fck,	CK_3XXX),
3318	CLK(NULL,	"i2c2_fck",	&i2c2_fck,	CK_3XXX),
3319	CLK(NULL,	"i2c1_fck",	&i2c1_fck,	CK_3XXX),
3320	CLK(NULL,	"mcbsp5_fck",	&mcbsp5_fck,	CK_3XXX),
3321	CLK(NULL,	"mcbsp1_fck",	&mcbsp1_fck,	CK_3XXX),
3322	CLK(NULL,	"core_48m_fck",	&core_48m_fck,	CK_3XXX),
3323	CLK(NULL,	"mcspi4_fck",	&mcspi4_fck,	CK_3XXX),
3324	CLK(NULL,	"mcspi3_fck",	&mcspi3_fck,	CK_3XXX),
3325	CLK(NULL,	"mcspi2_fck",	&mcspi2_fck,	CK_3XXX),
3326	CLK(NULL,	"mcspi1_fck",	&mcspi1_fck,	CK_3XXX),
3327	CLK(NULL,	"uart2_fck",	&uart2_fck,	CK_3XXX),
3328	CLK(NULL,	"uart1_fck",	&uart1_fck,	CK_3XXX),
3329	CLK(NULL,	"fshostusb_fck", &fshostusb_fck, CK_3430ES1),
3330	CLK(NULL,	"core_12m_fck",	&core_12m_fck,	CK_3XXX),
3331	CLK("omap_hdq.0",	"fck",	&hdq_fck,	CK_3XXX),
3332	CLK(NULL,	"ssi_ssr_fck",	&ssi_ssr_fck_3430es1,	CK_3430ES1),
3333	CLK(NULL,	"ssi_ssr_fck",	&ssi_ssr_fck_3430es2,	CK_3430ES2PLUS | CK_36XX),
3334	CLK(NULL,	"ssi_sst_fck",	&ssi_sst_fck_3430es1,	CK_3430ES1),
3335	CLK(NULL,	"ssi_sst_fck",	&ssi_sst_fck_3430es2,	CK_3430ES2PLUS | CK_36XX),
3336	CLK(NULL,	"core_l3_ick",	&core_l3_ick,	CK_3XXX),
3337	CLK("musb-omap2430",	"ick",	&hsotgusb_ick_3430es1,	CK_3430ES1),
3338	CLK("musb-omap2430",	"ick",	&hsotgusb_ick_3430es2,	CK_3430ES2PLUS | CK_36XX),
3339	CLK(NULL,	"sdrc_ick",	&sdrc_ick,	CK_3XXX),
3340	CLK(NULL,	"gpmc_fck",	&gpmc_fck,	CK_3XXX),
3341	CLK(NULL,	"security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
3342	CLK(NULL,	"pka_ick",	&pka_ick,	CK_34XX | CK_36XX),
3343	CLK(NULL,	"core_l4_ick",	&core_l4_ick,	CK_3XXX),
3344	CLK(NULL,	"usbtll_ick",	&usbtll_ick,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3345	CLK("usbhs_omap",	"usbtll_ick",	&usbtll_ick,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3346	CLK("omap_hsmmc.2",	"ick",	&mmchs3_ick,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3347	CLK(NULL,	"icr_ick",	&icr_ick,	CK_34XX | CK_36XX),
3348	CLK("omap-aes",	"ick",	&aes2_ick,	CK_34XX | CK_36XX),
3349	CLK("omap-sham",	"ick",	&sha12_ick,	CK_34XX | CK_36XX),
3350	CLK(NULL,	"des2_ick",	&des2_ick,	CK_34XX | CK_36XX),
3351	CLK("omap_hsmmc.1",	"ick",	&mmchs2_ick,	CK_3XXX),
3352	CLK("omap_hsmmc.0",	"ick",	&mmchs1_ick,	CK_3XXX),
3353	CLK(NULL,	"mspro_ick",	&mspro_ick,	CK_34XX | CK_36XX),
3354	CLK("omap_hdq.0", "ick",	&hdq_ick,	CK_3XXX),
3355	CLK("omap2_mcspi.4", "ick",	&mcspi4_ick,	CK_3XXX),
3356	CLK("omap2_mcspi.3", "ick",	&mcspi3_ick,	CK_3XXX),
3357	CLK("omap2_mcspi.2", "ick",	&mcspi2_ick,	CK_3XXX),
3358	CLK("omap2_mcspi.1", "ick",	&mcspi1_ick,	CK_3XXX),
3359	CLK("omap_i2c.3", "ick",	&i2c3_ick,	CK_3XXX),
3360	CLK("omap_i2c.2", "ick",	&i2c2_ick,	CK_3XXX),
3361	CLK("omap_i2c.1", "ick",	&i2c1_ick,	CK_3XXX),
3362	CLK(NULL,	"uart2_ick",	&uart2_ick,	CK_3XXX),
3363	CLK(NULL,	"uart1_ick",	&uart1_ick,	CK_3XXX),
3364	CLK(NULL,	"gpt11_ick",	&gpt11_ick,	CK_3XXX),
3365	CLK(NULL,	"gpt10_ick",	&gpt10_ick,	CK_3XXX),
3366	CLK("omap-mcbsp.5", "ick",	&mcbsp5_ick,	CK_3XXX),
3367	CLK("omap-mcbsp.1", "ick",	&mcbsp1_ick,	CK_3XXX),
3368	CLK(NULL,	"fac_ick",	&fac_ick,	CK_3430ES1),
3369	CLK(NULL,	"mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
3370	CLK(NULL,	"omapctrl_ick",	&omapctrl_ick,	CK_3XXX),
3371	CLK(NULL,	"ssi_l4_ick",	&ssi_l4_ick,	CK_34XX | CK_36XX),
3372	CLK(NULL,	"ssi_ick",	&ssi_ick_3430es1,	CK_3430ES1),
3373	CLK(NULL,	"ssi_ick",	&ssi_ick_3430es2,	CK_3430ES2PLUS | CK_36XX),
3374	CLK(NULL,	"usb_l4_ick",	&usb_l4_ick,	CK_3430ES1),
3375	CLK(NULL,	"security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX),
3376	CLK(NULL,	"aes1_ick",	&aes1_ick,	CK_34XX | CK_36XX),
3377	CLK("omap_rng",	"ick",		&rng_ick,	CK_34XX | CK_36XX),
3378	CLK(NULL,	"sha11_ick",	&sha11_ick,	CK_34XX | CK_36XX),
3379	CLK(NULL,	"des1_ick",	&des1_ick,	CK_34XX | CK_36XX),
3380	CLK(NULL,	"dss1_alwon_fck",		&dss1_alwon_fck_3430es1, CK_3430ES1),
3381	CLK(NULL,	"dss1_alwon_fck",		&dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3382	CLK(NULL,	"dss_tv_fck",	&dss_tv_fck,	CK_3XXX),
3383	CLK(NULL,	"dss_96m_fck",	&dss_96m_fck,	CK_3XXX),
3384	CLK(NULL,	"dss2_alwon_fck",	&dss2_alwon_fck, CK_3XXX),
3385	CLK("omapdss_dss",	"ick",		&dss_ick_3430es1,	CK_3430ES1),
3386	CLK("omapdss_dss",	"ick",		&dss_ick_3430es2,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3387	CLK(NULL,	"cam_mclk",	&cam_mclk,	CK_34XX | CK_36XX),
3388	CLK(NULL,	"cam_ick",	&cam_ick,	CK_34XX | CK_36XX),
3389	CLK(NULL,	"csi2_96m_fck",	&csi2_96m_fck,	CK_34XX | CK_36XX),
3390	CLK(NULL,	"usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3391	CLK(NULL,	"usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3392	CLK(NULL,	"usbhost_ick",	&usbhost_ick,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3393	CLK("usbhs_omap",	"usbhost_ick",	&usbhost_ick,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3394	CLK("usbhs_omap",	"utmi_p1_gfclk",	&dummy_ck,	CK_3XXX),
3395	CLK("usbhs_omap",	"utmi_p2_gfclk",	&dummy_ck,	CK_3XXX),
3396	CLK("usbhs_omap",	"xclk60mhsp1_ck",	&dummy_ck,	CK_3XXX),
3397	CLK("usbhs_omap",	"xclk60mhsp2_ck",	&dummy_ck,	CK_3XXX),
3398	CLK("usbhs_omap",	"usb_host_hs_utmi_p1_clk",	&dummy_ck,	CK_3XXX),
3399	CLK("usbhs_omap",	"usb_host_hs_utmi_p2_clk",	&dummy_ck,	CK_3XXX),
3400	CLK("usbhs_omap",	"usb_tll_hs_usb_ch0_clk",	&dummy_ck,	CK_3XXX),
3401	CLK("usbhs_omap",	"usb_tll_hs_usb_ch1_clk",	&dummy_ck,	CK_3XXX),
3402	CLK("usbhs_omap",	"init_60m_fclk",	&dummy_ck,	CK_3XXX),
3403	CLK(NULL,	"usim_fck",	&usim_fck,	CK_3430ES2PLUS | CK_36XX),
3404	CLK(NULL,	"gpt1_fck",	&gpt1_fck,	CK_3XXX),
3405	CLK(NULL,	"wkup_32k_fck",	&wkup_32k_fck,	CK_3XXX),
3406	CLK(NULL,	"gpio1_dbck",	&gpio1_dbck,	CK_3XXX),
3407	CLK(NULL,	"wdt2_fck",		&wdt2_fck,	CK_3XXX),
3408	CLK(NULL,	"wkup_l4_ick",	&wkup_l4_ick,	CK_34XX | CK_36XX),
3409	CLK(NULL,	"usim_ick",	&usim_ick,	CK_3430ES2PLUS | CK_36XX),
3410	CLK("omap_wdt",	"ick",		&wdt2_ick,	CK_3XXX),
3411	CLK(NULL,	"wdt1_ick",	&wdt1_ick,	CK_3XXX),
3412	CLK(NULL,	"gpio1_ick",	&gpio1_ick,	CK_3XXX),
3413	CLK(NULL,	"omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
3414	CLK(NULL,	"gpt12_ick",	&gpt12_ick,	CK_3XXX),
3415	CLK(NULL,	"gpt1_ick",	&gpt1_ick,	CK_3XXX),
3416	CLK("omap-mcbsp.2",	"prcm_fck",	&per_96m_fck,	CK_3XXX),
3417	CLK("omap-mcbsp.3",	"prcm_fck",	&per_96m_fck,	CK_3XXX),
3418	CLK("omap-mcbsp.4",	"prcm_fck",	&per_96m_fck,	CK_3XXX),
3419	CLK(NULL,	"per_96m_fck",	&per_96m_fck,	CK_3XXX),
3420	CLK(NULL,	"per_48m_fck",	&per_48m_fck,	CK_3XXX),
3421	CLK(NULL,	"uart3_fck",	&uart3_fck,	CK_3XXX),
3422	CLK(NULL,	"uart4_fck",	&uart4_fck,	CK_36XX),
3423	CLK(NULL,	"uart4_fck",	&uart4_fck_am35xx, CK_AM35XX),
3424	CLK(NULL,	"gpt2_fck",	&gpt2_fck,	CK_3XXX),
3425	CLK(NULL,	"gpt3_fck",	&gpt3_fck,	CK_3XXX),
3426	CLK(NULL,	"gpt4_fck",	&gpt4_fck,	CK_3XXX),
3427	CLK(NULL,	"gpt5_fck",	&gpt5_fck,	CK_3XXX),
3428	CLK(NULL,	"gpt6_fck",	&gpt6_fck,	CK_3XXX),
3429	CLK(NULL,	"gpt7_fck",	&gpt7_fck,	CK_3XXX),
3430	CLK(NULL,	"gpt8_fck",	&gpt8_fck,	CK_3XXX),
3431	CLK(NULL,	"gpt9_fck",	&gpt9_fck,	CK_3XXX),
3432	CLK(NULL,	"per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
3433	CLK(NULL,	"gpio6_dbck",	&gpio6_dbck,	CK_3XXX),
3434	CLK(NULL,	"gpio5_dbck",	&gpio5_dbck,	CK_3XXX),
3435	CLK(NULL,	"gpio4_dbck",	&gpio4_dbck,	CK_3XXX),
3436	CLK(NULL,	"gpio3_dbck",	&gpio3_dbck,	CK_3XXX),
3437	CLK(NULL,	"gpio2_dbck",	&gpio2_dbck,	CK_3XXX),
3438	CLK(NULL,	"wdt3_fck",	&wdt3_fck,	CK_3XXX),
3439	CLK(NULL,	"per_l4_ick",	&per_l4_ick,	CK_3XXX),
3440	CLK(NULL,	"gpio6_ick",	&gpio6_ick,	CK_3XXX),
3441	CLK(NULL,	"gpio5_ick",	&gpio5_ick,	CK_3XXX),
3442	CLK(NULL,	"gpio4_ick",	&gpio4_ick,	CK_3XXX),
3443	CLK(NULL,	"gpio3_ick",	&gpio3_ick,	CK_3XXX),
3444	CLK(NULL,	"gpio2_ick",	&gpio2_ick,	CK_3XXX),
3445	CLK(NULL,	"wdt3_ick",	&wdt3_ick,	CK_3XXX),
3446	CLK(NULL,	"uart3_ick",	&uart3_ick,	CK_3XXX),
3447	CLK(NULL,	"uart4_ick",	&uart4_ick,	CK_36XX),
3448	CLK(NULL,	"gpt9_ick",	&gpt9_ick,	CK_3XXX),
3449	CLK(NULL,	"gpt8_ick",	&gpt8_ick,	CK_3XXX),
3450	CLK(NULL,	"gpt7_ick",	&gpt7_ick,	CK_3XXX),
3451	CLK(NULL,	"gpt6_ick",	&gpt6_ick,	CK_3XXX),
3452	CLK(NULL,	"gpt5_ick",	&gpt5_ick,	CK_3XXX),
3453	CLK(NULL,	"gpt4_ick",	&gpt4_ick,	CK_3XXX),
3454	CLK(NULL,	"gpt3_ick",	&gpt3_ick,	CK_3XXX),
3455	CLK(NULL,	"gpt2_ick",	&gpt2_ick,	CK_3XXX),
3456	CLK("omap-mcbsp.2", "ick",	&mcbsp2_ick,	CK_3XXX),
3457	CLK("omap-mcbsp.3", "ick",	&mcbsp3_ick,	CK_3XXX),
3458	CLK("omap-mcbsp.4", "ick",	&mcbsp4_ick,	CK_3XXX),
3459	CLK(NULL,	"mcbsp2_fck",	&mcbsp2_fck,	CK_3XXX),
3460	CLK(NULL,	"mcbsp3_fck",	&mcbsp3_fck,	CK_3XXX),
3461	CLK(NULL,	"mcbsp4_fck",	&mcbsp4_fck,	CK_3XXX),
3462	CLK("etb",	"emu_src_ck",	&emu_src_ck,	CK_3XXX),
3463	CLK(NULL,	"pclk_fck",	&pclk_fck,	CK_3XXX),
3464	CLK(NULL,	"pclkx2_fck",	&pclkx2_fck,	CK_3XXX),
3465	CLK(NULL,	"atclk_fck",	&atclk_fck,	CK_3XXX),
3466	CLK(NULL,	"traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
3467	CLK(NULL,	"traceclk_fck",	&traceclk_fck,	CK_3XXX),
3468	CLK(NULL,	"sr1_fck",	&sr1_fck,	CK_34XX | CK_36XX),
3469	CLK(NULL,	"sr2_fck",	&sr2_fck,	CK_34XX | CK_36XX),
3470	CLK(NULL,	"sr_l4_ick",	&sr_l4_ick,	CK_34XX | CK_36XX),
3471	CLK(NULL,	"secure_32k_fck", &secure_32k_fck, CK_3XXX),
3472	CLK(NULL,	"gpt12_fck",	&gpt12_fck,	CK_3XXX),
3473	CLK(NULL,	"wdt1_fck",	&wdt1_fck,	CK_3XXX),
3474	CLK(NULL,	"ipss_ick",	&ipss_ick,	CK_AM35XX),
3475	CLK(NULL,	"rmii_ck",	&rmii_ck,	CK_AM35XX),
3476	CLK(NULL,	"pclk_ck",	&pclk_ck,	CK_AM35XX),
3477	CLK("davinci_emac",	NULL,	&emac_ick,	CK_AM35XX),
3478	CLK("davinci_mdio.0",	NULL,	&emac_fck,	CK_AM35XX),
3479	CLK("vpfe-capture",	"master",	&vpfe_ick,	CK_AM35XX),
3480	CLK("vpfe-capture",	"slave",	&vpfe_fck,	CK_AM35XX),
3481	CLK("musb-am35x",	"ick",		&hsotgusb_ick_am35xx,	CK_AM35XX),
3482	CLK("musb-am35x",	"fck",		&hsotgusb_fck_am35xx,	CK_AM35XX),
3483	CLK(NULL,	"hecc_ck",	&hecc_ck,	CK_AM35XX),
3484	CLK(NULL,	"uart4_ick",	&uart4_ick_am35xx,	CK_AM35XX),
3485	CLK("omap_timer.1",	"32k_ck",	&omap_32k_fck,  CK_3XXX),
3486	CLK("omap_timer.2",	"32k_ck",	&omap_32k_fck,  CK_3XXX),
3487	CLK("omap_timer.3",	"32k_ck",	&omap_32k_fck,  CK_3XXX),
3488	CLK("omap_timer.4",	"32k_ck",	&omap_32k_fck,  CK_3XXX),
3489	CLK("omap_timer.5",	"32k_ck",	&omap_32k_fck,  CK_3XXX),
3490	CLK("omap_timer.6",	"32k_ck",	&omap_32k_fck,  CK_3XXX),
3491	CLK("omap_timer.7",	"32k_ck",	&omap_32k_fck,  CK_3XXX),
3492	CLK("omap_timer.8",	"32k_ck",	&omap_32k_fck,  CK_3XXX),
3493	CLK("omap_timer.9",	"32k_ck",	&omap_32k_fck,  CK_3XXX),
3494	CLK("omap_timer.10",	"32k_ck",	&omap_32k_fck,  CK_3XXX),
3495	CLK("omap_timer.11",	"32k_ck",	&omap_32k_fck,  CK_3XXX),
3496	CLK("omap_timer.12",	"32k_ck",	&omap_32k_fck,  CK_3XXX),
3497	CLK("omap_timer.1",	"sys_ck",	&sys_ck,	CK_3XXX),
3498	CLK("omap_timer.2",	"sys_ck",	&sys_ck,	CK_3XXX),
3499	CLK("omap_timer.3",	"sys_ck",	&sys_ck,	CK_3XXX),
3500	CLK("omap_timer.4",	"sys_ck",	&sys_ck,	CK_3XXX),
3501	CLK("omap_timer.5",	"sys_ck",	&sys_ck,	CK_3XXX),
3502	CLK("omap_timer.6",	"sys_ck",	&sys_ck,	CK_3XXX),
3503	CLK("omap_timer.7",	"sys_ck",	&sys_ck,	CK_3XXX),
3504	CLK("omap_timer.8",	"sys_ck",	&sys_ck,	CK_3XXX),
3505	CLK("omap_timer.9",	"sys_ck",	&sys_ck,	CK_3XXX),
3506	CLK("omap_timer.10",	"sys_ck",	&sys_ck,	CK_3XXX),
3507	CLK("omap_timer.11",	"sys_ck",	&sys_ck,	CK_3XXX),
3508	CLK("omap_timer.12",	"sys_ck",	&sys_ck,	CK_3XXX),
3509};
3510
3511
3512int __init omap3xxx_clk_init(void)
3513{
3514	struct omap_clk *c;
3515	u32 cpu_clkflg = 0;
3516
3517	if (soc_is_am35xx()) {
3518		cpu_mask = RATE_IN_34XX;
3519		cpu_clkflg = CK_AM35XX;
3520	} else if (cpu_is_omap3630()) {
3521		cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
3522		cpu_clkflg = CK_36XX;
3523	} else if (cpu_is_ti816x()) {
3524		cpu_mask = RATE_IN_TI816X;
3525		cpu_clkflg = CK_TI816X;
3526	} else if (cpu_is_am33xx()) {
3527		cpu_mask = RATE_IN_AM33XX;
3528	} else if (cpu_is_ti814x()) {
3529		cpu_mask = RATE_IN_TI814X;
3530	} else if (cpu_is_omap34xx()) {
3531		if (omap_rev() == OMAP3430_REV_ES1_0) {
3532			cpu_mask = RATE_IN_3430ES1;
3533			cpu_clkflg = CK_3430ES1;
3534		} else {
3535			/*
3536			 * Assume that anything that we haven't matched yet
3537			 * has 3430ES2-type clocks.
3538			 */
3539			cpu_mask = RATE_IN_3430ES2PLUS;
3540			cpu_clkflg = CK_3430ES2PLUS;
3541		}
3542	} else {
3543		WARN(1, "clock: could not identify OMAP3 variant\n");
3544	}
3545
3546	if (omap3_has_192mhz_clk())
3547		omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3548
3549	if (cpu_is_omap3630()) {
3550		/*
3551		 * XXX This type of dynamic rewriting of the clock tree is
3552		 * deprecated and should be revised soon.
3553		 *
3554		 * For 3630: override clkops_omap2_dflt_wait for the
3555		 * clocks affected from PWRDN reset Limitation
3556		 */
3557		dpll3_m3x2_ck.ops =
3558				&clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3559		dpll4_m2x2_ck.ops =
3560				&clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3561		dpll4_m3x2_ck.ops =
3562				&clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3563		dpll4_m4x2_ck.ops =
3564				&clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3565		dpll4_m5x2_ck.ops =
3566				&clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3567		dpll4_m6x2_ck.ops =
3568				&clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3569	}
3570
3571	/*
3572	 * XXX This type of dynamic rewriting of the clock tree is
3573	 * deprecated and should be revised soon.
3574	 */
3575	if (cpu_is_omap3630())
3576		dpll4_dd = dpll4_dd_3630;
3577	else
3578		dpll4_dd = dpll4_dd_34xx;
3579
3580	clk_init(&omap2_clk_functions);
3581
3582	for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3583	     c++)
3584		clk_preinit(c->lk.clk);
3585
3586	for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3587	     c++)
3588		if (c->cpu & cpu_clkflg) {
3589			clkdev_add(&c->lk);
3590			clk_register(c->lk.clk);
3591			omap2_init_clk_clkdm(c->lk.clk);
3592		}
3593
3594	/* Disable autoidle on all clocks; let the PM code enable it later */
3595	omap_clk_disable_autoidle_all();
3596
3597	recalculate_root_clocks();
3598
3599	pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
3600		(osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
3601		(core_ck.rate / 1000000), (arm_fck.rate / 1000000));
3602
3603	/*
3604	 * Only enable those clocks we will need, let the drivers
3605	 * enable other clocks as necessary
3606	 */
3607	clk_enable_init_clocks();
3608
3609	/*
3610	 * Lock DPLL5 -- here only until other device init code can
3611	 * handle this
3612	 */
3613	if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
3614		omap3_clk_lock_dpll5();
3615
3616	/* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3617	sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3618	arm_fck_p = clk_get(NULL, "arm_fck");
3619
3620	return 0;
3621}