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1/*
2 * OMAP2/3/4 DPLL clock functions
3 *
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15#undef DEBUG
16
17#include <linux/kernel.h>
18#include <linux/errno.h>
19#include <linux/clk.h>
20#include <linux/io.h>
21
22#include <asm/div64.h>
23
24#include <plat/clock.h>
25#include <plat/cpu.h>
26
27#include "clock.h"
28#include "cm-regbits-24xx.h"
29#include "cm-regbits-34xx.h"
30
31/* DPLL rate rounding: minimum DPLL multiplier, divider values */
32#define DPLL_MIN_MULTIPLIER 2
33#define DPLL_MIN_DIVIDER 1
34
35/* Possible error results from _dpll_test_mult */
36#define DPLL_MULT_UNDERFLOW -1
37
38/*
39 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
40 * The higher the scale factor, the greater the risk of arithmetic overflow,
41 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
42 * must be a power of DPLL_SCALE_BASE.
43 */
44#define DPLL_SCALE_FACTOR 64
45#define DPLL_SCALE_BASE 2
46#define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
47 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
48
49/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
50#define OMAP3430_DPLL_FINT_BAND1_MIN 750000
51#define OMAP3430_DPLL_FINT_BAND1_MAX 2100000
52#define OMAP3430_DPLL_FINT_BAND2_MIN 7500000
53#define OMAP3430_DPLL_FINT_BAND2_MAX 21000000
54
55/*
56 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
57 * From device data manual section 4.3 "DPLL and DLL Specifications".
58 */
59#define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 500000
60#define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 2500000
61#define OMAP3PLUS_DPLL_FINT_MIN 32000
62#define OMAP3PLUS_DPLL_FINT_MAX 52000000
63
64/* _dpll_test_fint() return codes */
65#define DPLL_FINT_UNDERFLOW -1
66#define DPLL_FINT_INVALID -2
67
68/* Private functions */
69
70/*
71 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
72 * @clk: DPLL struct clk to test
73 * @n: divider value (N) to test
74 *
75 * Tests whether a particular divider @n will result in a valid DPLL
76 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
77 * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate
78 * (assuming that it is counting N upwards), or -2 if the enclosing loop
79 * should skip to the next iteration (again assuming N is increasing).
80 */
81static int _dpll_test_fint(struct clk *clk, u8 n)
82{
83 struct dpll_data *dd;
84 long fint, fint_min, fint_max;
85 int ret = 0;
86
87 dd = clk->dpll_data;
88
89 /* DPLL divider must result in a valid jitter correction val */
90 fint = clk->parent->rate / n;
91
92 if (cpu_is_omap24xx()) {
93 /* Should not be called for OMAP2, so warn if it is called */
94 WARN(1, "No fint limits available for OMAP2!\n");
95 return DPLL_FINT_INVALID;
96 } else if (cpu_is_omap3430()) {
97 fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
98 fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
99 } else if (dd->flags & DPLL_J_TYPE) {
100 fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN;
101 fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX;
102 } else {
103 fint_min = OMAP3PLUS_DPLL_FINT_MIN;
104 fint_max = OMAP3PLUS_DPLL_FINT_MAX;
105 }
106
107 if (fint < fint_min) {
108 pr_debug("rejecting n=%d due to Fint failure, "
109 "lowering max_divider\n", n);
110 dd->max_divider = n;
111 ret = DPLL_FINT_UNDERFLOW;
112 } else if (fint > fint_max) {
113 pr_debug("rejecting n=%d due to Fint failure, "
114 "boosting min_divider\n", n);
115 dd->min_divider = n;
116 ret = DPLL_FINT_INVALID;
117 } else if (cpu_is_omap3430() && fint > OMAP3430_DPLL_FINT_BAND1_MAX &&
118 fint < OMAP3430_DPLL_FINT_BAND2_MIN) {
119 pr_debug("rejecting n=%d due to Fint failure\n", n);
120 ret = DPLL_FINT_INVALID;
121 }
122
123 return ret;
124}
125
126static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
127 unsigned int m, unsigned int n)
128{
129 unsigned long long num;
130
131 num = (unsigned long long)parent_rate * m;
132 do_div(num, n);
133 return num;
134}
135
136/*
137 * _dpll_test_mult - test a DPLL multiplier value
138 * @m: pointer to the DPLL m (multiplier) value under test
139 * @n: current DPLL n (divider) value under test
140 * @new_rate: pointer to storage for the resulting rounded rate
141 * @target_rate: the desired DPLL rate
142 * @parent_rate: the DPLL's parent clock rate
143 *
144 * This code tests a DPLL multiplier value, ensuring that the
145 * resulting rate will not be higher than the target_rate, and that
146 * the multiplier value itself is valid for the DPLL. Initially, the
147 * integer pointed to by the m argument should be prescaled by
148 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
149 * a non-scaled m upon return. This non-scaled m will result in a
150 * new_rate as close as possible to target_rate (but not greater than
151 * target_rate) given the current (parent_rate, n, prescaled m)
152 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
153 * non-scaled m attempted to underflow, which can allow the calling
154 * function to bail out early; or 0 upon success.
155 */
156static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
157 unsigned long target_rate,
158 unsigned long parent_rate)
159{
160 int r = 0, carry = 0;
161
162 /* Unscale m and round if necessary */
163 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
164 carry = 1;
165 *m = (*m / DPLL_SCALE_FACTOR) + carry;
166
167 /*
168 * The new rate must be <= the target rate to avoid programming
169 * a rate that is impossible for the hardware to handle
170 */
171 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
172 if (*new_rate > target_rate) {
173 (*m)--;
174 *new_rate = 0;
175 }
176
177 /* Guard against m underflow */
178 if (*m < DPLL_MIN_MULTIPLIER) {
179 *m = DPLL_MIN_MULTIPLIER;
180 *new_rate = 0;
181 r = DPLL_MULT_UNDERFLOW;
182 }
183
184 if (*new_rate == 0)
185 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
186
187 return r;
188}
189
190/* Public functions */
191
192void omap2_init_dpll_parent(struct clk *clk)
193{
194 u32 v;
195 struct dpll_data *dd;
196
197 dd = clk->dpll_data;
198 if (!dd)
199 return;
200
201 v = __raw_readl(dd->control_reg);
202 v &= dd->enable_mask;
203 v >>= __ffs(dd->enable_mask);
204
205 /* Reparent the struct clk in case the dpll is in bypass */
206 if (cpu_is_omap24xx()) {
207 if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
208 v == OMAP2XXX_EN_DPLL_FRBYPASS)
209 clk_reparent(clk, dd->clk_bypass);
210 } else if (cpu_is_omap34xx()) {
211 if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
212 v == OMAP3XXX_EN_DPLL_FRBYPASS)
213 clk_reparent(clk, dd->clk_bypass);
214 } else if (cpu_is_omap44xx()) {
215 if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
216 v == OMAP4XXX_EN_DPLL_FRBYPASS ||
217 v == OMAP4XXX_EN_DPLL_MNBYPASS)
218 clk_reparent(clk, dd->clk_bypass);
219 }
220 return;
221}
222
223/**
224 * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
225 * @clk: struct clk * of a DPLL
226 *
227 * DPLLs can be locked or bypassed - basically, enabled or disabled.
228 * When locked, the DPLL output depends on the M and N values. When
229 * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
230 * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
231 * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
232 * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
233 * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
234 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
235 * if the clock @clk is not a DPLL.
236 */
237u32 omap2_get_dpll_rate(struct clk *clk)
238{
239 long long dpll_clk;
240 u32 dpll_mult, dpll_div, v;
241 struct dpll_data *dd;
242
243 dd = clk->dpll_data;
244 if (!dd)
245 return 0;
246
247 /* Return bypass rate if DPLL is bypassed */
248 v = __raw_readl(dd->control_reg);
249 v &= dd->enable_mask;
250 v >>= __ffs(dd->enable_mask);
251
252 if (cpu_is_omap24xx()) {
253 if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
254 v == OMAP2XXX_EN_DPLL_FRBYPASS)
255 return dd->clk_bypass->rate;
256 } else if (cpu_is_omap34xx()) {
257 if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
258 v == OMAP3XXX_EN_DPLL_FRBYPASS)
259 return dd->clk_bypass->rate;
260 } else if (cpu_is_omap44xx()) {
261 if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
262 v == OMAP4XXX_EN_DPLL_FRBYPASS ||
263 v == OMAP4XXX_EN_DPLL_MNBYPASS)
264 return dd->clk_bypass->rate;
265 }
266
267 v = __raw_readl(dd->mult_div1_reg);
268 dpll_mult = v & dd->mult_mask;
269 dpll_mult >>= __ffs(dd->mult_mask);
270 dpll_div = v & dd->div1_mask;
271 dpll_div >>= __ffs(dd->div1_mask);
272
273 dpll_clk = (long long)dd->clk_ref->rate * dpll_mult;
274 do_div(dpll_clk, dpll_div + 1);
275
276 return dpll_clk;
277}
278
279/* DPLL rate rounding code */
280
281/**
282 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
283 * @clk: struct clk * for a DPLL
284 * @target_rate: desired DPLL clock rate
285 *
286 * Given a DPLL and a desired target rate, round the target rate to a
287 * possible, programmable rate for this DPLL. Attempts to select the
288 * minimum possible n. Stores the computed (m, n) in the DPLL's
289 * dpll_data structure so set_rate() will not need to call this
290 * (expensive) function again. Returns ~0 if the target rate cannot
291 * be rounded, or the rounded rate upon success.
292 */
293long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
294{
295 int m, n, r, scaled_max_m;
296 unsigned long scaled_rt_rp;
297 unsigned long new_rate = 0;
298 struct dpll_data *dd;
299
300 if (!clk || !clk->dpll_data)
301 return ~0;
302
303 dd = clk->dpll_data;
304
305 pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
306 clk->name, target_rate);
307
308 scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
309 scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
310
311 dd->last_rounded_rate = 0;
312
313 for (n = dd->min_divider; n <= dd->max_divider; n++) {
314
315 /* Is the (input clk, divider) pair valid for the DPLL? */
316 r = _dpll_test_fint(clk, n);
317 if (r == DPLL_FINT_UNDERFLOW)
318 break;
319 else if (r == DPLL_FINT_INVALID)
320 continue;
321
322 /* Compute the scaled DPLL multiplier, based on the divider */
323 m = scaled_rt_rp * n;
324
325 /*
326 * Since we're counting n up, a m overflow means we
327 * can bail out completely (since as n increases in
328 * the next iteration, there's no way that m can
329 * increase beyond the current m)
330 */
331 if (m > scaled_max_m)
332 break;
333
334 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
335 dd->clk_ref->rate);
336
337 /* m can't be set low enough for this n - try with a larger n */
338 if (r == DPLL_MULT_UNDERFLOW)
339 continue;
340
341 pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
342 clk->name, m, n, new_rate);
343
344 if (target_rate == new_rate) {
345 dd->last_rounded_m = m;
346 dd->last_rounded_n = n;
347 dd->last_rounded_rate = target_rate;
348 break;
349 }
350 }
351
352 if (target_rate != new_rate) {
353 pr_debug("clock: %s: cannot round to rate %ld\n", clk->name,
354 target_rate);
355 return ~0;
356 }
357
358 return target_rate;
359}
360