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1/*
2 * derived from linux/arch/arm/mach-versatile/core.c
3 * linux/arch/arm/mach-bcmring/core.c
4 *
5 * Copyright (C) 1999 - 2003 ARM Limited
6 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22/* Portions copyright Broadcom 2008 */
23
24#include <linux/init.h>
25#include <linux/device.h>
26#include <linux/dma-mapping.h>
27#include <linux/platform_device.h>
28#include <linux/interrupt.h>
29#include <linux/amba/bus.h>
30#include <linux/clkdev.h>
31
32#include <mach/csp/mm_addr.h>
33#include <mach/hardware.h>
34#include <linux/io.h>
35#include <asm/irq.h>
36#include <asm/hardware/arm_timer.h>
37#include <asm/hardware/timer-sp.h>
38#include <asm/mach-types.h>
39
40#include <asm/mach/arch.h>
41#include <asm/mach/flash.h>
42#include <asm/mach/irq.h>
43#include <asm/mach/time.h>
44#include <asm/mach/map.h>
45
46#include <cfg_global.h>
47
48#include "clock.h"
49
50#include <csp/secHw.h>
51#include <mach/csp/secHw_def.h>
52#include <mach/csp/chipcHw_inline.h>
53#include <mach/csp/tmrHw_reg.h>
54
55static AMBA_APB_DEVICE(uartA, "uartA", 0, MM_ADDR_IO_UARTA, {IRQ_UARTA}, NULL);
56static AMBA_APB_DEVICE(uartB, "uartB", 0, MM_ADDR_IO_UARTB, {IRQ_UARTB}, NULL);
57
58static struct clk pll1_clk = {
59 .name = "PLL1",
60 .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL1,
61 .rate_hz = 2000000000,
62 .use_cnt = 7,
63};
64
65static struct clk uart_clk = {
66 .name = "UART",
67 .type = CLK_TYPE_PROGRAMMABLE,
68 .csp_id = chipcHw_CLOCK_UART,
69 .rate_hz = HW_CFG_UART_CLK_HZ,
70 .parent = &pll1_clk,
71};
72
73static struct clk dummy_apb_pclk = {
74 .name = "BUSCLK",
75 .type = CLK_TYPE_PRIMARY,
76 .mode = CLK_MODE_XTAL,
77};
78
79/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically 150-166 MHz */
80#if defined(CONFIG_ARCH_FPGA11107)
81/* fpga cpu/bus are currently 30 times slower so scale frequency as well to */
82/* slow down Linux's sense of time */
83#define TIMER0_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
84#define TIMER1_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
85#define TIMER3_FREQUENCY_MHZ (tmrHw_HIGH_FREQUENCY_MHZ * 30)
86#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
87#else
88#define TIMER0_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
89#define TIMER1_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
90#define TIMER3_FREQUENCY_MHZ tmrHw_HIGH_FREQUENCY_MHZ
91#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000)
92#endif
93
94static struct clk sp804_timer012_clk = {
95 .name = "sp804-timer-0,1,2",
96 .type = CLK_TYPE_PRIMARY,
97 .mode = CLK_MODE_XTAL,
98 .rate_hz = TIMER1_FREQUENCY_MHZ * 1000000,
99};
100
101static struct clk sp804_timer3_clk = {
102 .name = "sp804-timer-3",
103 .type = CLK_TYPE_PRIMARY,
104 .mode = CLK_MODE_XTAL,
105 .rate_hz = TIMER3_FREQUENCY_KHZ * 1000,
106};
107
108static struct clk_lookup lookups[] = {
109 { /* Bus clock */
110 .con_id = "apb_pclk",
111 .clk = &dummy_apb_pclk,
112 }, { /* UART0 */
113 .dev_id = "uarta",
114 .clk = &uart_clk,
115 }, { /* UART1 */
116 .dev_id = "uartb",
117 .clk = &uart_clk,
118 }, { /* SP804 timer 0 */
119 .dev_id = "sp804",
120 .con_id = "timer0",
121 .clk = &sp804_timer012_clk,
122 }, { /* SP804 timer 1 */
123 .dev_id = "sp804",
124 .con_id = "timer1",
125 .clk = &sp804_timer012_clk,
126 }, { /* SP804 timer 3 */
127 .dev_id = "sp804",
128 .con_id = "timer3",
129 .clk = &sp804_timer3_clk,
130 }
131};
132
133static struct amba_device *amba_devs[] __initdata = {
134 &uartA_device,
135 &uartB_device,
136};
137
138void __init bcmring_amba_init(void)
139{
140 int i;
141 u32 bus_clock;
142
143/* Linux is run initially in non-secure mode. Secure peripherals */
144/* generate FIQ, and must be handled in secure mode. Until we have */
145/* a linux security monitor implementation, keep everything in */
146/* non-secure mode. */
147 chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_SPU);
148 secHw_setUnsecure(secHw_BLK_MASK_CHIP_CONTROL |
149 secHw_BLK_MASK_KEY_SCAN |
150 secHw_BLK_MASK_TOUCH_SCREEN |
151 secHw_BLK_MASK_UART0 |
152 secHw_BLK_MASK_UART1 |
153 secHw_BLK_MASK_WATCHDOG |
154 secHw_BLK_MASK_SPUM |
155 secHw_BLK_MASK_DDR2 |
156 secHw_BLK_MASK_SPU |
157 secHw_BLK_MASK_PKA |
158 secHw_BLK_MASK_RNG |
159 secHw_BLK_MASK_RTC |
160 secHw_BLK_MASK_OTP |
161 secHw_BLK_MASK_BOOT |
162 secHw_BLK_MASK_MPU |
163 secHw_BLK_MASK_TZCTRL | secHw_BLK_MASK_INTR);
164
165 /* Only the devices attached to the AMBA bus are enabled just before the bus is */
166 /* scanned and the drivers are loaded. The clocks need to be on for the AMBA bus */
167 /* driver to access these blocks. The bus is probed, and the drivers are loaded. */
168 /* FIXME Need to remove enable of PIF once CLCD clock enable used properly in FPGA. */
169 bus_clock = chipcHw_REG_BUS_CLOCK_GE
170 | chipcHw_REG_BUS_CLOCK_SDIO0 | chipcHw_REG_BUS_CLOCK_SDIO1;
171
172 chipcHw_busInterfaceClockEnable(bus_clock);
173
174 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
175 struct amba_device *d = amba_devs[i];
176 amba_device_register(d, &iomem_resource);
177 }
178}
179
180/*
181 * Where is the timer (VA)?
182 */
183#define TIMER0_VA_BASE ((void __iomem *)MM_IO_BASE_TMR)
184#define TIMER1_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x20))
185#define TIMER2_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x40))
186#define TIMER3_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x60))
187
188static int __init bcmring_clocksource_init(void)
189{
190 /* setup timer1 as free-running clocksource */
191 sp804_clocksource_init(TIMER1_VA_BASE, "timer1");
192
193 /* setup timer3 as free-running clocksource */
194 sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
195
196 return 0;
197}
198
199/*
200 * Set up timer interrupt, and return the current time in seconds.
201 */
202void __init bcmring_init_timer(void)
203{
204 printk(KERN_INFO "bcmring_init_timer\n");
205 /*
206 * Initialise to a known state (all timers off)
207 */
208 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
209 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
210 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
211 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
212
213 /*
214 * Make irqs happen for the system timer
215 */
216 bcmring_clocksource_init();
217
218 sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMER0, "timer0");
219}
220
221struct sys_timer bcmring_timer = {
222 .init = bcmring_init_timer,
223};
224
225void __init bcmring_init_early(void)
226{
227 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
228}